JP2009246307A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining a lower contact resistance to a nitride semiconductor containing Al, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes a substrate, a first semiconductor layer provided on the substrate and consisting of nitride semiconductor, a second semiconductor layer provided on the first semiconductor layer and consisting of a nitride semiconductor higher in the concentration of aluminum than the first semiconductor layer and an electrode provided on the second semiconductor layer while a plurality of holes are formed on the second semiconductor layer and the respective plurality of holes are filled with a material same as that of the electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically, to a semiconductor device using gallium nitride and a manufacturing method thereof.

  As a semiconductor device using a nitride semiconductor such as gallium nitride, for example, a light emitting element such as a light emitting diode or a semiconductor laser capable of emitting light in a blue to ultraviolet region, or an electronic element such as a field effect transistor using a two-dimensional electron gas Can be mentioned. As an example, a high electron mobility transistor (HEMT) using a heterojunction of gallium nitride (GaN) and aluminum gallium nitride (AlGaN) can be applied to a high-frequency power transistor for a mobile base station. It is expected (for example, Patent Document 1).

Specifically, in the AlGaN / GaN heterostructure, charges concentrate on the heterointerface due to spontaneous polarization and piezopolarization effects on the (0001) plane, and a sheet of 1 × 10 ¹³ / cm ⁻² or more without dopant injection Carrier concentration is obtained. Concentration of charges generated at the heterointerface is called 2-dimensional electron gas (2-DEG), and by using this carrier layer, a heterojunction field effect transistor having a large current density can be realized.

In an electronic device or a light emitting device using such a nitride semiconductor, an electrode extraction structure with low contact resistance is important. However, AlGaN has a wide band gap, and it is not easy to obtain a low contact resistance when the electrodes are brought into contact with each other.
JP 2007-207820 A

  The present invention provides a semiconductor device capable of obtaining a lower contact resistance with respect to a nitride semiconductor containing Al and a method for manufacturing the same.

  According to one aspect of the present invention, a substrate, a first semiconductor layer made of a nitride semiconductor provided on the substrate, and the first semiconductor layer provided on the first semiconductor layer A second semiconductor layer made of a nitride semiconductor having a higher aluminum concentration, and an electrode provided on the second semiconductor layer, wherein a plurality of holes are formed in the second semiconductor layer. Each of the plurality of holes is filled with the same kind of material as that of the electrode.

  According to another aspect of the present invention, a substrate, a first semiconductor layer made of a nitride semiconductor provided on the substrate, and the first semiconductor layer provided on the first semiconductor layer. And a second semiconductor layer made of a nitride semiconductor having a higher aluminum concentration than that of the semiconductor layer, and etching the second semiconductor layer of the stack with phosphoric acid to form a plurality of holes. There is provided a method of manufacturing a semiconductor device, comprising: a step of forming; and a step of forming an electrode on the second semiconductor layer.

ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can obtain lower contact resistance with respect to the nitride semiconductor containing Al, and its manufacturing method are provided.
Is provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is an enlarged cross-sectional view of a part of a semiconductor device according to an embodiment of the present invention.
That is, FIG. 1 shows an electrode portion of the semiconductor device. The semiconductor device of this embodiment includes a first semiconductor layer 10, a second semiconductor layer 20 provided thereon, and an electrode 30 provided thereon. The first semiconductor layer 10 is made of a nitride semiconductor having a relatively low aluminum (Al) concentration. The second layer 20 is made of a nitride semiconductor having a relatively high Al concentration. The second semiconductor layer 20 is formed with a plurality of holes 20H penetrating in the thickness direction, and these holes 20H are filled with substantially the same kind of material as the electrode 30.

According to the present embodiment, the electrode 30 contacts the second semiconductor layer 10 having a relatively low Al concentration through the plurality of holes 20H. As a result, the contact resistance can be lowered while maintaining the heterojunction between the first semiconductor layer 10 and the second semiconductor layer 20.
Here, the opening shape of the hole 20H can be, for example, round. Moreover, the diameter of the opening can be set to about several tens nanometers to several hundred nanometers, for example.

  FIG. 2 is an enlarged cross-sectional view of a part of a modification of the semiconductor device of the present embodiment. 2 and the subsequent drawings, the same reference numerals are given to the same elements as those described in the previous drawings, and detailed description thereof will be omitted as appropriate.

  In this modified example, the hole 20H does not penetrate the second semiconductor layer 20. The hole 20H is filled with the same material as the electrode 30. In this way, even when the hole 20H does not penetrate the second semiconductor layer 20, by filling the same type of material as the electrode 30 there, the hole 20H can be brought closer to the first semiconductor layer 10 and charge due to the tunnel effect or the like. Movement is promoted. As a result, the contact resistance can be lowered.

The holes 20H illustrated in FIGS. 1 and 2 can be formed by dry etching, for example. Specifically, a hole (not shown) is formed on the second semiconductor layer 20, and the hole 20H is formed by etching the second semiconductor layer 20 exposed in the opening formed in the mask. it can. In the case of a nitride semiconductor such as AlGaN, for example, the hole 20H can be opened by dry etching using a chlorine-based gas.
Alternatively, the hole 20H can be formed by wet etching without using a mask. That is, as will be described in detail later, when etching is performed with hot phosphoric acid, a defect portion such as threading dislocation becomes a core and is preferentially etched. As a result, a plurality of holes 20H as shown in FIGS. 1 and 2 can be formed.

3 and 4 are schematic cross-sectional views illustrating the case where defects such as threading dislocations are present.
For example, when a GaN layer (first semiconductor layer) 10 and an AlGaN layer (second semiconductor layer) 20 are epitaxially grown on a substrate (not shown), dislocations 10D penetrating these semiconductor layers in the thickness direction are formed. There is. According to the present embodiment, as will be described in detail later, the threading dislocation portion of the AlGaN layer 20 can be preferentially etched using an etchant such as hot phosphoric acid. In that case, the underlying GaN layer 10 is hardly etched. Therefore, in this case, threading dislocations 10D exist in the GaN layer 10 below the holes 20H.

  3 and 4 exemplify the case where threading dislocations 10D exist as an example of the defect, the present invention is not limited to this. That is, defects 10D other than threading dislocations may exist or such defects may not exist.

  The specific examples shown in FIGS. 1 to 4 can be applied to a light emitting element such as a light emitting diode or a semiconductor laser. Specifically, for example, in the case of forming an electrode on a semiconductor layer having a relatively high Al concentration on at least one side of a double hetero structure in which an active layer is sandwiched between a clad layer and a light guide layer By adopting the structure shown in FIG. 1 or FIG. 2, the contact resistance can be lowered.

  In this way, even when the drive current is increased, heat generation at the electrode portion can be suppressed, and a high output optical element can be realized. Further, since a contact layer having a narrow band gap such as GaN can be omitted, the device structure and process can be simplified.

  On the other hand, the specific examples shown in FIGS. 1 to 4 can be applied to an electronic device such as a field effect transistor.

FIG. 5 is a cross-sectional view showing a specific example in which the present embodiment is applied to a field effect transistor.
As shown in FIG. 5A, the field effect transistor includes a first semiconductor layer 10 made of, for example, GaN, and a second semiconductor layer 20 made of, for example, AlGaN provided thereon. The first semiconductor layer 10 is formed on a substrate 100 such as sapphire, SiC, or GaN. The first semiconductor layer 10 and the second semiconductor layer 20 can be formed by a technique such as HVPE (hydride vapor phase epitaxy), MOCVD (metal-organic chemical vapor deposition), MBE (molecular beam epitaxy), or the like. . Note that a buffer layer made of AlN or the like (not shown) may be provided between the substrate 100 and the first semiconductor layer 10.

A source electrode 30 and a drain electrode 30 are provided on the second semiconductor layer 20. A gate electrode 50 is provided between the source electrode 30 and the drain electrode 30.
As described above, by bringing the first semiconductor layer 10 and the second semiconductor layer 20 made of a nitride semiconductor into contact with each other, 2DEG is formed at the heterojunction. By using this 2DEG, a heterojunction field effect transistor having a large current density can be realized.

  That is, in a state where no voltage is applied to the gate electrode 50, a current having a high current density can be conducted by the 2DEG between the source electrode 30 and the drain electrode 30 (on state). On the other hand, when a predetermined voltage is applied to the gate electrode 50, 2DEG is depleted thereunder, and the source electrode 30 and the drain electrode 30 are in a non-conducting state (off state).

  Under the source electrode 30 and the drain electrode 30, the second semiconductor layer 20 is provided with a plurality of holes 20H.

5 (b) and 5 (c) are enlarged views of a broken line portion in FIG. 5 (a).
The hole 20H may pass through the second semiconductor layer 20 as shown in FIG. 5B, or pass through the second semiconductor layer 20 as shown in FIG. 5C. It does not have to be. As shown in FIGS. 3 and 4, a defect 10 </ b> D such as threading dislocation may exist in the first semiconductor layer 10. These holes 20H are filled with the same material as the source electrode 30 and the drain electrode 30.

According to this embodiment, the contact resistance of the source electrode 30 and the drain electrode 30 can be significantly reduced by providing the hole 20H and filling the hole 20H with the same type of material as those electrodes.
Conventionally, when a contact between the source electrode and the drain electrode of such a transistor is formed, for example, AlGaN (second semiconductor layer 20) in the contact portion is removed by etching, and GaN (first semiconductor layer 10) is formed. ) Has been proposed. However, when the second semiconductor layer 20 is selectively removed in this manner, not only is the process burden imposed, but the GaN (first semiconductor layer 10) is often damaged. Further, if the second semiconductor layer 20 is removed, 2DEG is not generated in that portion, so that it is difficult to efficiently extract 2DEG generated in the channel region (portion below the gate 50) to the electrode 30. It becomes. That is, the series resistance between the source and the drain increases, and the operation characteristics of the transistor tend to deteriorate due to heat generation.

  On the other hand, a method of doping AlGaN (second semiconductor layer 20) at a high concentration at the contact portion between the source electrode 30 and the drain electrode 30 has also been proposed. However, even if AlGaN is doped with an impurity at a high concentration, it is not easy to sufficiently reduce the contact resistance, and there is room for improvement.

  On the other hand, according to the present embodiment, by providing a plurality of fine holes 20H in the second semiconductor layer 20 and filling with the material of the electrode 30, the contact resistance is remarkably maintained while maintaining the heterojunction. Can be lowered.

  That is, since the heterojunction of the first semiconductor layer 10 and the second semiconductor layer 20 is formed also under the source electrode 30 and the drain electrode 30, 2DEG can be generated. The contact resistance can be remarkably lowered by bringing the electrode 30 close to the interface with the first semiconductor layer 10 through the hole 20H.

Hereinafter, embodiments of the present invention will be described in more detail with reference to examples.
As the field effect transistor shown in FIG. 5, the GaN layer 10 and the Al _0.28 Ga _0.72 N layer 20 were epitaxially grown on the sapphire substrate 100. The thickness of the GaN layer 10 can be 3000 nanometers, and the thickness of the AlGaN layer 20 can be 20 nanometers.

  Then, etching was performed with hot phosphoric acid to form holes 20H in the AlGaN layer 20. Note that by patterning using a general resist such as OFPR as a mask, only the portions of the source electrode 30 and the drain electrode 30 can be selectively etched with hot phosphoric acid.

  After forming the hole 20H, the material for the source electrode 30 and the drain electrode 30 is vapor-deposited and sintered annealing is performed in the same manner as a generally known method for manufacturing a field effect transistor. Then, a resist having a pattern for forming the gate electrode 50 is applied, the gate electrode 50 material is deposited, and the gate electrode 50 can be formed by lift-off.

As the source electrode 30 and the drain electrode 30, for example, titanium can be used. Note that aluminum or the like may be stacked over titanium.
On the other hand, as the Schottky gate electrode 50, for example, nickel can be used. Also in this case, gold or the like may be laminated on nickel.

Here, the present inventor observed the formation of the holes 20H by hot phosphoric acid using an atomic force microscope (AFM).
FIG. 6 is an AFM image showing the etching effect by hot phosphoric acid.
6A and 6B are AFM images of the surfaces of the GaN layer and the Al _0.28 Ga _0.72 N layer before etching, respectively. 6C and 6D are AFM images of the GaN layer and the AlGaN layer after etching with hot phosphoric acid.

  Here, the hot phosphoric acid is phosphoric acid having a concentration of 98 percent and a temperature of 70 ° C., and the etching time is 20 minutes.

As shown in FIGS. 6A and 6B, there is no hole in GaN and AlGaN before etching. On the other hand, after the etching with hot phosphoric acid, as shown in FIG. 6C, almost no change is observed on the surface of GaN. In contrast, as shown in FIG. 6D, it can be seen that a plurality of holes 20H are opened on the surface of AlGaN. It can also be seen that both GaN and AlGaN have an atomic terrace structure after wet etching with hot phosphoric acid.
From these results, it is surmised that the hole 20H was formed by etching AlGaN with a defect such as a dislocation penetrating the AlGaN layer as a core. In the case of the GaN layer, it is presumed that the etching with phosphoric acid is promoted by the presence of aluminum (Al), considering that the GaN layer is not etched. When threading dislocations promote AlGaN etching, it may be advantageous to use sapphire or the like as the substrate 100 (see FIGS. 1 to 4). That is, since sapphire has a relatively large lattice constant mismatch with GaN, crystal defects such as threading dislocations are easily formed in a nitride semiconductor layer such as GaN. In the present embodiment, the holes 20H can be formed in the AlGaN layer 20 using these defects.

  On the other hand, since GaN is hardly etched, it turns out that the 1st semiconductor layer 10 can be used as an etching stop layer in the laminated structure as illustrated in FIGS. Here, even when the first semiconductor layer 10 contains aluminum, if the aluminum concentration is lower than that of the second semiconductor layer 20, the etching rate with respect to hot phosphoric acid is considered to be low. Therefore, it is possible to form the hole 20H in the second semiconductor layer 20 and suppress the progress of etching by the first semiconductor layer 10 below the hole 20H.

Next, the result of etching the Al _0.28 Ga _0.72 N layer with hot phosphoric acid at 95 ° C. will be described.

FIG. 7 is a graph showing the relationship between the etching time when etched with hot phosphoric acid at 95 ° C., the depth of the hole 20H, and the diameter of the hole 20 phrase. That is, the horizontal axis of the figure represents the etching time (minutes), the left vertical axis represents the depth (nanometer) of the hole 20H, and the right vertical axis represents the diameter (full width at half maximum) of the hole 20H.
Here, the depth and diameter (full width at half maximum) of the hole 20H were each measured by AFM. The curvature of the tip of the AFM probe is approximately 20 nanometers.

  From FIG. 7, it can be seen that the depth of the hole 20H is less than 10 nanometers and the diameter (full width at half maximum) is about 100 nanometers after etching for 10 minutes. Moreover, the depth of the hole 20H exceeds 10 nanometers by etching for 20 minutes, and the diameter (full width at half maximum) becomes about 150 nanometers. The depth of the hole 20H reaches 20 nanometers by etching for 30 minutes, and the diameter (half value) It can be seen that the total width is about 150 nanometers.

  From this result, it can be confirmed that the depth of the hole 20H is saturated at about 20 nanometers. This indicates that the GaN layer is not etched even in hot phosphoric acid at 95 ° C.

The present inventor also measured the contact resistance by filling the hole 20H thus formed with an electrode.
The wafer used here has a structure in which a GaN layer 10 and an Al _0.28 Ga _0.72 N layer 20 are stacked in this order on a sapphire substrate. The thickness of the GaN layer 10 was 3200 nanometers, and the thickness of the AlGaN layer 20 was 20 nanometers. The carrier concentration of the 2DEG generated in the heterojunction is approximately 1.15 × ¹⁰ 13 ^{cm -2,} the mobility is 1235cm ² / Vs.

As pretreatment, this wafer was subjected to acetone boiling for 20 minutes, ultrasonic cleaning using ethanol for 10 minutes, and replacement cleaning with pure water for 3 minutes. After the pretreatment, etching was performed using the following three types of etchants. Note that the etching time was 20 minutes.

(Sample 1) hydrochloric acid (34 percent): pure water = 1: 2
(Sample 2) Hydrogen peroxide solution: sulfuric acid (96 percent) = 2: 1 (110 ° C.)
(Sample 3) Hot phosphoric acid (85 percent: 95 ° C)

After this etching, titanium was deposited to a thickness of 30 nanometers, and aluminum was further deposited to a thickness of 200 nanometers, followed by sintering annealing at 800 ° C. for 30 minutes in a nitrogen atmosphere.

And about these samples, IV (current-voltage) measurement was carried out with the prober, and contact resistance was measured.

As a result, the relative values of the contact resistance (Ωcm ² ) of the samples obtained by etching (1) to (3) described above were as follows.

(Sample 1) 2.9
(Sample 2) 3.4
(Sample 3) 0.38

That is, it was found that the contact resistance of Sample 3 using hot phosphoric acid was as low as about 1/10 compared to the other two types of etching. As described above with reference to FIGS. 1 to 6, a plurality of holes 20 </ b> H are formed in the AlGaN layer 20, and by charging the material of the electrode 30 here, the contact with the underlying GaN layer 10 is dramatically increased. This is thought to be due to the improvement. In particular, in the case of the present example, 2DEG is formed at the heterointerface between the GaN layer and the AlGaN layer on the GaN layer. However, according to this embodiment, the 2DEG can be maintained and taken out by the electrode. It becomes.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.
For example, the plurality of holes 20H can be formed by dry etching using a gas containing phosphoric acid instead of wet etching with hot phosphoric acid.
5 illustrates a so-called normally-on transistor that is turned on when no gate voltage is applied to the gate electrode 50, the present invention is not limited to this. In other words, the present invention can be similarly applied to a so-called normally-off transistor that is turned off when no gate voltage is applied to the gate electrode 50 and is turned on when the gate voltage is applied.

  5 illustrates the structure using the Schottky type gate electrode 50, the gate insulating film may be provided instead of the gate electrode provided thereon. Further, instead of the AlGaN layer 20, an AlN layer may be used.

  In addition, all semiconductor devices and manufacturing methods that can be implemented by those skilled in the art based on the above-described semiconductor device and manufacturing method described above as embodiments of the present invention include the gist of the present invention. As long as it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further including a group V element other than N (nitrogen) and those further including any of various dopants added for controlling the conductivity type are also referred to as “nitride semiconductors”. Shall be included.

It is sectional drawing to which some semiconductor devices based on embodiment of this invention were expanded. It is sectional drawing which expanded a part of modification of the semiconductor device of this embodiment. It is a schematic cross section which illustrates the case where defects, such as a threading dislocation, exist. It is a schematic cross section which illustrates the case where defects, such as a threading dislocation, exist. It is sectional drawing showing the specific example which applied embodiment of this invention to the field effect transistor. It is an AFM image showing the etching effect by hot phosphoric acid. It is a graph showing the relationship between the etching time when etched with hot phosphoric acid at 95 ° C., the depth of the hole 20H, and the diameter of the hole 20 phrase.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 1st semiconductor layer 10D Defect 20 2nd semiconductor layer 20H Hole 30 Electrode (source electrode, drain electrode)
50 Gate electrode 100 Substrate

Claims (7)

A substrate,
A first semiconductor layer made of a nitride semiconductor provided on the substrate;
A second semiconductor layer provided on the first semiconductor layer and made of a nitride semiconductor having a higher aluminum concentration than the first semiconductor layer;
An electrode provided on the second semiconductor layer;
With
A semiconductor device, wherein a plurality of holes are formed in the second semiconductor layer, and each of the plurality of holes is filled with the same kind of material as the electrode.   The semiconductor device according to claim 1, wherein the hole penetrates the second semiconductor layer.   The semiconductor device according to claim 1, wherein the hole does not penetrate the second semiconductor layer to the first semiconductor layer.   The semiconductor device according to claim 1, wherein the electrode is at least one of a source electrode and a drain electrode.   The semiconductor device according to claim 1, wherein the first has threading dislocations in a portion below the hole. A substrate, a first semiconductor layer made of a nitride semiconductor provided on the substrate, and a nitride semiconductor provided on the first semiconductor layer and having a higher aluminum concentration than the first semiconductor layer A laminated body having a second semiconductor layer comprising:
Etching the second semiconductor layer of the stack with phosphoric acid to form a plurality of holes;
Forming an electrode on the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising:   7. The semiconductor according to claim 6, wherein the step of forming the electrode includes a step of depositing a conductive material on the second semiconductor layer and filling the plurality of holes with the conductive material. Device manufacturing method.