JP6534993B2 - Nitride semiconductor device, method of manufacturing the same, diode and field effect transistor - Google Patents

Description

  The present invention relates to a nitride semiconductor device and a method of manufacturing the same, and a diode and a field effect transistor.

  Wide band gap semiconductors represented by nitride semiconductors have high dielectric breakdown voltage, good electron transport characteristics, and good thermal conductivity, and therefore they are used as materials for high temperature environment, high power, or high frequency semiconductor devices. Very attractive. Typical wide band gap semiconductors include nitride semiconductors of GaN, AlN, InN, BN or mixed crystals of two or more of them. Also, for example, in a field effect transistor (FET) having an AlGaN / GaN heterojunction structure, a two-dimensional electron gas is generated at the heterojunction interface due to piezoelectric polarization and spontaneous polarization. This two-dimensional electron gas has high electron mobility and carrier density. Therefore, a Schottky barrier diode (Schottky Barrier Diode: SBD) and a heterojunction field effect transistor (HFET) using such an AlGaN / GaN heterojunction structure have high breakdown voltage, low on resistance, and high speed. It has a switching speed and is very suitable for power switching applications.

  Patent Document 1 describes a configuration in which current collapse is suppressed and leakage is reduced by selectively providing a field plate layer (GaNFP layer) made of gallium nitride on the electron supply layer.

JP, 2011-54845, A JP, 2010-199441, A U.S. Patent Publication 20110244663

APPLIED PHYSICS LETTERS 98, 252105 (2011)

  However, when the inventor of the present invention made a trial manufacture of a nitride semiconductor device as described in, for example, Patent Document 1, the inventors found a problem that the leak current may be larger than the value expected from the design and the withstand voltage may be lowered. The

  The present invention has been made in view of the above, and an object thereof is to suppress a leakage current in a nitride semiconductor device and to suppress a reduction in breakdown voltage, a method of manufacturing the same, and a diode And providing a field effect transistor.

In order to solve the problems described above and achieve the above object, a nitride semiconductor device according to the present invention is provided on a substrate, a buffer layer provided on the upper layer of the substrate and doped with carbon, and an upper layer on the buffer layer. A semiconductor laminate comprising: a first semiconductor layer made of a nitride semiconductor; a second semiconductor layer provided on the first semiconductor layer and having a band gap wider on average than the first semiconductor layer; A first electrode provided on at least a part of the layers, and a second electrode provided on at least a part of the layers constituting the semiconductor stack, separately from the first electrode; And a third semiconductor layer containing carbon at a concentration of 1.0 × 10 ¹⁸ cm ⁻³ or less is provided between the substrate and the buffer layer, and the third semiconductor layer has a thickness of 500 nm or more. Characterized by less than 3000 nm That.

The nitride semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the third semiconductor layer is made of an Al _x Ga ₁ -xN layer (0 ≦ x ≦ 1) with an Al composition ratio x.

  The nitride semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the film thickness of the third semiconductor layer is 1000 nm or more and less than 3000 nm.

The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the carbon concentration of the buffer layer is 5.0 × 10 ¹⁸ cm ⁻³ or more and 5.0 × 10 ¹⁹ cm ⁻³ or less.

In the nitride semiconductor device according to the present invention, in the above invention, the third semiconductor layer is composed of a plurality of Al _x Ga _1-x N layers (0 ≦ x ≦ 1) having different Al composition ratios x. It is characterized by Further, in this configuration, the Al composition ratio x of the Al _x Ga ₁ -xN layer is characterized by decreasing toward the upper side in the stacking direction.

  The nitride semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the third semiconductor layer is a stack of a plurality of aluminum nitride layers and gallium nitride layers. Further, in this configuration, the third semiconductor layer is characterized by being formed by repeatedly laminating a gallium nitride layer having a thickness of 100 nm to 700 nm and an aluminum nitride layer having a thickness of 20 nm to 60 nm a plurality of times. I assume.

  In the nitride semiconductor device according to the present invention, in the above-described invention, the fourth semiconductor layer made of a nitride semiconductor having an average band gap narrower than that of the second semiconductor layer is selectively provided in the upper layer of the second semiconductor layer. It is characterized by

In the nitride semiconductor device according to the present invention, in the above-mentioned invention, the third semiconductor layer contains surfactant atoms as an impurity, and the concentration of surfactant atoms is 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.0 × 10 10 It is characterized by being ¹⁸ cm ^-3 or less.

A nitride semiconductor device according to the present invention comprises a substrate, a buffer layer provided in the upper layer of the substrate and doped with carbon, a first semiconductor layer made of a nitride semiconductor provided in the upper layer of the buffer layer, and a first semiconductor It is provided on at least a part of the semiconductor stack including the second semiconductor layer provided in the upper layer of the layers and having an average band gap larger than that of the first semiconductor layer, and a layer constituting the semiconductor stack. A first electrode and a second electrode provided spaced apart from the first electrode on at least a part of layers of the layers forming the semiconductor stack, and between the substrate and the buffer layer, the surfactant atom contained at a concentration of 5.0 × 10 ¹⁸ cm ^-3 or less carbon atoms with containing as impurities, thickness is provided a third semiconductor layer of less than 500 nm 3000 nm, impure surfactant atoms Wherein the concentration is 1.0 × 10 ¹⁶ cm ^-3 or more 1.0 × 10 ¹⁸ cm ^-3 or less.

  In the nitride semiconductor device according to the present invention, in the above-mentioned invention, the nitride semiconductor device according to the third aspect of the present invention is provided on at least a portion of layers of the layers forming the semiconductor stack, spaced apart from the first electrode and the second electrode. The method further comprises an electrode.

  A field effect transistor according to the present invention has the configuration of the nitride semiconductor device according to the above invention, characterized in that the first electrode is a gate electrode, the second electrode is a drain electrode, and the third electrode is a source electrode. Do.

  A diode according to the present invention is characterized by having the configuration of the nitride semiconductor device according to the above invention, wherein the first electrode is an anode electrode and the second electrode is a cathode electrode.

A method of manufacturing a nitride semiconductor device according to the present invention includes a substrate, a buffer layer provided in the upper layer of the substrate and doped with carbon, a first semiconductor layer made of a nitride semiconductor provided in the upper layer of the buffer layer, A semiconductor laminate having a second semiconductor layer provided in the upper layer of the first semiconductor layer and having an average band gap wider than that of the first semiconductor layer, and at least a part of the layers constituting the semiconductor laminate Method of manufacturing a nitride semiconductor device comprising: a first electrode provided in the first layer; and a second electrode provided on at least a part of layers of the layers forming the semiconductor stack, spaced apart from the first electrode. In the upper layer of the substrate, the third semiconductor layer made of a nitride semiconductor is grown to a thickness of 500 nm or more and less than 3000 nm under growth conditions in which carbon is doped at a concentration of 1.0 × 10 ¹⁸ cm ⁻³ or less. rear Wherein the growing the buffer layer on the upper layer of the third semiconductor layer.

  According to the nitride semiconductor device and the method of manufacturing the same, and the diode and the field effect transistor according to the present invention, it is possible to suppress the leak current in the nitride semiconductor device and to suppress the decrease in withstand voltage.

FIG. 1 is a cross-sectional view showing a semiconductor multilayer substrate for manufacturing a nitride semiconductor device according to a first embodiment of the present invention. FIG. 2 is a graph showing an example of the Al composition ratio dependency of the film thickness necessary for filling a pit of 1 μm in diameter by the Al _x Ga ₁ -xN layer. FIG. 3 is a cross-sectional view showing a Schottky barrier diode manufactured using the semiconductor multilayer substrate according to the first embodiment of the present invention. FIG. 4 shows the film thickness dependency of the ratio of the ratio of the device which becomes the reference withstand voltage or more in the case where the carbon concentration of the planarization layer according to the first embodiment of the present invention is fixed to 1 × 10 ¹⁷ cm ⁻³ . Is a graph showing FIG. 5 is a graph showing the carbon concentration dependency of the planarizing layer of the ratio of the device which is equal to or higher than the reference withstand voltage when the film thickness of the planarizing layer according to the first embodiment of the present invention is 2000 nm. FIG. 6 is a schematic cross-sectional view showing a high mobility field effect transistor according to a second embodiment of the present invention. FIG. 7 is a graph showing the surfactant concentration dependency in the ratio of the device which is equal to or higher than the reference withstand voltage of the nitride semiconductor device. FIG. 8 is a cross-sectional view showing a portion of an anomalous growth region of the SBD, for explaining the intensive study by the inventor. FIG. 9 is a cross-sectional view of a portion of the semiconductor multilayer substrate according to Experimental Example 1 in which an abnormal growth region is formed, for illustrating the intensive study by the inventor. FIG. 10 is a cross-sectional view of a portion of the semiconductor multilayer substrate according to Experimental Example 2 in which an anomalous growth region is formed, for illustrating the intensive studies by the inventor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited by the following embodiments. Further, in the drawings, the same or corresponding elements are given the same reference numerals as appropriate, and redundant description will be appropriately omitted. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships among elements may differ from actual ones. Even between the drawings, there may be a case where the dimensional relationships and ratios differ from one another. In addition, “upper”, “upper” or “upper”, and “lower”, “lower” or “lower” used in the description of the following embodiments are far apart at right angles to the main surface of the substrate of the semiconductor device. It shows the orientation as well as the orientation towards the main surface of the substrate. That is, “upper”, “upper”, “upper”, “lower”, “lower”, and “lower” used in the description of the embodiment do not necessarily coincide with the vertical direction in the mounted state of the semiconductor device.

First, in describing the embodiments of the present invention, in order to facilitate the understanding of the present invention, earnest studies conducted by the present inventors in order to solve the problems described above will be described. First, the conventional nitride semiconductor multilayer substrates which the present inventors have been intensively studied, and the problems they have will be described. In the following figures and tables, αE + β indicates α × 10 ^β .

  First, in the conventional nitride semiconductor device, the inventor variously examines the reason why the leak current is large and the ratio that the withstand voltage of the device is equal to or higher than the desired withstand voltage, specifically, the ratio that the withstand voltage is 600 V or more is low. went. In the process of the study, the inventor focused on a nitride semiconductor device which has been determined to have a large leak current specifically and defectively as compared to a normal nitride semiconductor device such as SBD or HEMT. Then, the inventor has found that a non-growth region is generated in the semiconductor laminated structure in the nitride semiconductor device due to various causes. That is, foreign matter may be mixed in the interface between the silicon (Si) substrate in the nitride semiconductor layer and the intervening layer made of aluminum nitride (AlN) epitaxially grown on the substrate. In addition, foreign matter may be mixed into the interface between the intervening layer and the epitaxial growth layer made of gallium nitride (GaN) or aluminum gallium nitride (AlGaN). Such contamination of foreign matter is considered to occur, for example, in the process of cleaning the surface of the substrate, the process of transporting the substrate, and the like. Furthermore, if there is a sparse place in the intervening layer for some reason, melt back etching (reaction between Si substrate and Ga) may occur. Then, due to these causes, a non-growth region is generated in the semiconductor multilayer structure in the nitride semiconductor device. Such a non-growth region is difficult to embed only by epitaxially growing the semiconductor layer on the upper layer. In particular, in a nitride semiconductor layer epitaxially grown according to growth conditions in which carbon (C) is heavily doped to form a high resistance buffer layer or the like, it has been extremely difficult to embed the non-growth region. As a result, it is inevitable that the non-growth region remains as the abnormal growth region even in the vicinity of the surface of the semiconductor multilayer structure.

  As described above, when the abnormal growth region remains as a pit, it is known that in the nitride semiconductor device, the abnormal growth region serves as a leak source and a leak path is generated (see Non-Patent Document 1). Therefore, when the inventors conducted experiments and intensive studies, it was found that the anomalous growth region may be buried depending on the growth conditions when the u-GaN layer constituting the electron transit layer is formed on the upper layer. did. However, according to the inventors of the present invention, even if the abnormal growth region is buried by the u-GaN layer, the buried region becomes a leak source, which is one of the causes of the occurrence of the leak path in the nitride semiconductor device. It turned out to be one. When a leak path occurs, the leak current increases and the withstand voltage of the nitride semiconductor device decreases.

  Therefore, based on the above findings, the inventor focused on a nitride semiconductor device having a withstand voltage against a voltage of 600 V or more, such as SBD or HEMT, in order to reduce the leakage current and improve the withstand voltage. I made a careful study. FIG. 8 is a schematic cross-sectional view showing a Schottky barrier diode (SBD) as a nitride semiconductor device in which foreign matter adheres to the intervening layer, which has been the subject of this examination.

  As shown in FIG. 8, in the conventional SBD 90, an intervening layer 92, a high resistance buffer layer 93, an electron transit layer 94, and an electron supply layer 95 are sequentially stacked on a substrate 91. In addition, a field plate layer 96 a is selectively provided on the electron supply layer 95. Further, on the electron supply layer 95, an anode electrode 97A and a cathode electrode 97C separated from the anode electrode 97A are selectively provided. An insulating film 98 is provided to cover the electron supply layer 95 and the field plate layer 96a and at least a part of the anode electrode 97A and the cathode electrode 97C. Then, 2DEG layers A and a are generated at the interface between the electron transit layer 94 and the electron supply layer 95. The 2DEG layer a is a region where the 2DEG concentration is reduced by the field plate layer 96a as compared to the 2DEG layer A. Further, FIG. 8 shows a state in which a foreign matter 110 such as a particle is present in the upper layer portion of the intervening layer 92.

  As shown in FIG. 8, on the upper layer of a substrate 91 such as a Si substrate, an intervening layer 92 made of aluminum nitride (AlN) for suppressing the reaction between Ga and Si is stacked. Then, a high resistance buffer layer 93 as a nitride semiconductor layer containing GaN is stacked on the intervening layer 92. However, if foreign matter 110 such as particles is present on substrate 91 or intervening layer 92, crystal growth does not proceed in the portion where foreign matter 110 is present, so the growth of high-resistance buffer layer 93 is delayed and becomes an abnormal growth region. Defects 93a may occur. If such a defect 93a exists, an abnormal growth region caused by the defect 93a is reflected also in the nitride semiconductor layer stacked further on the upper layer. The existence of this abnormal growth region is a leak in the nitride semiconductor device as a final product because the high resistance buffer layer 93 becomes partially thin even if they are embedded by the material constituting the electron transit layer 94. Was found to be the cause of an increase in pressure or a decrease in pressure resistance. The increase of the leak and the decrease of the breakdown voltage are phenomena common to various nitride semiconductor devices such as SBD and HEMT.

  Therefore, the present inventor has re-examined a method for reducing the leak caused by the defect 93a. Then, the inventor recalled that in order to suppress the defects 93 a on the surface of the high resistance buffer layer 93, a planarization layer whose surface shape is planarized is provided below the high resistance buffer layer 93. When the planarizing layer is provided below the buffer layer, the buffer layer can be stacked on the planarizing layer while maintaining the flatness, so that the leak current flowing in the buffer layer can be reduced, and the reduction in withstand voltage can be suppressed. Therefore, the leak can be reduced in the nitride semiconductor device as the final product, and the withstand voltage can also be improved. In addition, even if the planarizing layer has a low resistance, by increasing the resistance of the buffer layer, the electric field generated in the nitride semiconductor layer below the upper surface of the planarizing layer can be reduced. Extremely low.

  Then, the inventor conducted various experiments to realize the surface planarization of the semiconductor layer in the lower layer of the buffer layer described above. FIG. 9 shows anomalous growth in a semiconductor multilayer substrate according to Experimental Example 1 in which a plurality of nitride semiconductor layers are stacked by metal organic chemical vapor deposition (MOCVD) for the present inventor to study. It is a typical sectional view showing a field part. As shown in FIG. 9, in the semiconductor multilayer substrate 100 according to Experimental Example 1, an AlN layer 102 assuming an intervening layer is provided on the substrate 101. A nitride semiconductor layer 103 made of GaN is formed on the AlN layer 102. The nitride semiconductor layer 103 has a defect 103 a due to the presence of the foreign matter 110. Then, the inventor conducted an experiment of sequentially performing epitaxial growth on the nitride semiconductor layer 103 by changing various growth conditions of the nitride semiconductor layers 104, 105, 106, 107, 108, and 109, respectively. Although not shown in FIG. 9, a thin AlN layer is sandwiched between the interfaces of the nitride semiconductor layers 103 to 109. Table 1 is a table showing growth conditions of these nitride semiconductor layers 104 to 109.

  In Table 1, layers 104 to 109 indicate nitride semiconductor layers 104 to 109, respectively. Then, in Table 1, the growth temperature, the growth pressure, and the ratio of group V (nitrogen: N) to group III (gallium: Ga) (V / III ratio) in the growth of the respective nitride semiconductor layers 104 to 109. And the carbon concentration when crystal growth is performed under those conditions. Here, secondary ion mass spectrometry (SIMS), for example, is used as a method of measuring the carbon concentration. Specifically, in the measurement of carbon concentration, using quadrupole SIMS manufactured by Physical Electronics Co., Ltd. and using cesium as a primary ion species, the acceleration voltage is 5 keV, the beam current is 100 nA, and the secondary ion polarity is It was negative. Furthermore, the sputtered area is 200 μm × 400 μm, and the gate area is about 12% of the central area of the sputtered area. Then, the carbon concentration was measured five times, and the arithmetic average of the measured values of these five carbon concentrations was taken as the carbon concentration in Table 1. In addition, the measuring method of the carbon concentration in the following experimental example and embodiment is the same.

As shown in Table 1, under the growth conditions of the nitride semiconductor layer 104, the V / III ratio is increased by 3 to 6 times, for example, about 4 times, as compared with the growth conditions of the other nitride semiconductor layers 105 to 109. The growth rate is set to about 1⁄4 of 1⁄6 to 1⁄3. When the nitride semiconductor layer 104 is grown in this state, carbon is auto-doped in the nitride semiconductor layer 104 and the carbon concentration becomes about 3 × 10 ¹⁸ cm ⁻³ . Further, under the growth conditions of the nitride semiconductor layer 105, the V / III ratio is reduced as compared with the growth conditions of the other nitride semiconductor layers 104 and 106-109. In this case, the carbon concentration of the nitride semiconductor layer 105 is increased to about 2 × 10 ¹⁹ cm ⁻³ . Under the growth conditions of the nitride semiconductor layer 106, the growth temperature is lowered relative to the other nitride semiconductor layers 104, 105, 107-109. In this case, the carbon concentration of the nitride semiconductor layer 106 is approximately 2 × 10 ¹⁹ cm ⁻³ . Under the growth conditions of the nitride semiconductor layer 107, the growth pressure is increased relative to the other nitride semiconductor layers 104 to 106, 108, and 109. In this case, the carbon concentration of the nitride semiconductor layer 107 is approximately 2 × 10 ¹⁸ cm ^−3, which is lower than the carbon concentration of the nitride semiconductor layers 105 and 106. Under the growth conditions of the nitride semiconductor layer 108, the growth temperature is increased as compared to the other nitride semiconductor layers 104 to 107 and 109. In this case, the carbon concentration of the nitride semiconductor layer 108 is about 2 × 10 ¹⁸ cm ⁻³ , which is lower than that of the nitride semiconductor layers 105 and 106. Furthermore, the growth conditions of the nitride semiconductor layer 109 are growth conditions for growing a GaN layer constituting a conventional buffer layer, and the carbon concentration is as high as about 1 × 10 ¹⁹ cm ⁻³ . The shape of the defect 103 a is reflected on the surface side of each of the nitride semiconductor layers 104 to 109.

  Furthermore, based on the above examination, the inventor examined materials and growth conditions that are easily planarized in the upper layer of the defect 103a. Then, the inventor of the present invention is a growth condition in which the material grows even with respect to the non-growth region generated by the foreign matter 110 as the growth condition which is easily planarized in the above-mentioned experimental example 1; In the lateral direction, attention is focused on the need to grow nitride semiconductors. Therefore, in the semiconductor multilayer substrate 100 shown in FIG. 9, the present inventor pays attention to the growth conditions of the nitride semiconductor layers 104, 107 and 108 which are grown relatively in the lateral direction among the nitride semiconductor layers 103 to 109. did. That is, the inventor found from Experimental Example 1 that the carbon concentration of the semiconductor layer in the growth of the nitride semiconductor is difficult to grow laterally when it is relatively high, and it is likely to grow laterally when it is relatively low. I found it.

  Therefore, the present inventors conducted, as Experimental Example 2, a growth experiment of a nitride semiconductor layer in order to study growth conditions capable of planarization. FIG. 10 is a cross-sectional view showing the vicinity of a defect in a semiconductor multilayer substrate in which nitride semiconductor layers are stacked based on the study of the inventor. As shown in FIG. 10, in the semiconductor multilayer substrate 200 according to Experimental Example 2, an AlN layer 202 assuming an intervening layer is provided on a substrate 201. Further, on the AlN layer 202, a nitride semiconductor layer 203 made of GaN is formed in which a defect 203a is generated due to the presence of the foreign matter 210. Then, in order to examine growth conditions for achieving planarization, the present inventors have grown nitride semiconductor layers 204, 205, 206, 207, 208, and 209 on the nitride semiconductor layer 203, respectively. The epitaxial growth was made sequentially by changing the Although not shown in FIG. 10, a thin AlN layer is sandwiched between the interfaces of the nitride semiconductor layers 203 to 209. The growth conditions of these nitride semiconductor layers 204 to 209 are shown in Table 2.

  In Table 2, the layers 204 to 209 indicate the nitride semiconductor layers 204 to 209, respectively. Then, in Table 2, the growth temperature, the growth pressure, and the ratio of group V (nitrogen: N) to group III (gallium: Ga) (V / III ratio) in the growth of the respective nitride semiconductor layers 204 to 209. And a carbon concentration when crystal growth is performed under these conditions.

As shown in Table 2, in Experimental Example 2, the growth conditions of nitride semiconductor layers 204 to 207 and 209 are set to be the same as the growth conditions of nitride semiconductor layer 109 constituting the conventional buffer layer in Experimental Example 1. . On the other hand, the growth conditions of the nitride semiconductor layer 208 are set to conditions in which the growth conditions different from the growth conditions of the other nitride semiconductor layers in the nitride semiconductor layers 104, 107 and 108 described above are extracted. That is, in the growth of nitride semiconductor layer 208, the growth temperature and the growth pressure are made relatively high, and the flow rate of the group III element is decreased to increase the V / III ratio. As a result, the carbon concentration of the nitride semiconductor layer 208 is approximately 2.0 × 10 ¹⁷ cm ⁻³ . Then, when the inventor causes the nitride semiconductor layer 208 to grow under the above-described growth conditions, as shown in FIG. 10, in the nitride semiconductor layer 208, the growth rate along the lateral direction is along the stacking direction. Promoted equal to or better than growth rate. As a result, it has been confirmed that the concave portion present in the nitride semiconductor layer 207 whose shape is reflected due to the defect 203a is buried by the nitride semiconductor layer 208, and the surface thereof can be planarized.

As described above, the present inventor can form a planarizing layer by embedding a defect (concave portion) caused by a foreign substance by growing a nitride semiconductor so that the concentration of carbon to be auto-doped becomes low. It has come to be found that a buffer layer in which flatness is ensured can be formed in the upper layer. Therefore, the present inventors examined the conditions by changing the carbon concentration of carbon automatically doped to the nitride semiconductor layer to various concentrations. As a result, the inventor made the carbon concentration less than the carbon concentration (about 1.0 × 10 ¹⁹ cm ⁻³ ), specifically less than 2.0 × 10 ¹⁸ cm ^−3, in the buffer layer to be stacked on the upper layer. It was found that when grown to be as described above, the recess caused by the defect 203a began to be filled. Furthermore, the present inventor also found that when the nitride semiconductor is grown to have a carbon concentration of 1 × 10 ¹⁸ cm ⁻³ or less, the nitride semiconductor is easily grown in the lateral direction and the recess is further easily filled. As a result, an abnormal growth region caused by a defect or the like can be prevented from remaining in the buffer layer constituting the nitride semiconductor device, so that the generation of a leak path in the nitride semiconductor device can be suppressed, and a reduction in breakdown voltage can be suppressed. Therefore, in the nitride semiconductor device as the final product, it is possible to improve the ratio of the number of devices whose withstand voltage is equal to or higher than the reference withstand voltage with respect to the number of manufactured devices (hereinafter, the ratio of devices which become equal to or higher than the reference withstand voltage). The reference breakdown voltage is a breakdown voltage obtained based on the desired rated value or standard value of the nitride semiconductor device. The embodiments described below are devised based on the above intensive studies.

First Embodiment
FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor multilayer substrate for manufacturing a nitride semiconductor device according to a first embodiment of the present invention. That is, in the semiconductor multilayer substrate 10 in the first embodiment, the intervening layer 12, the planarization layer 13 as the third semiconductor layer, the high resistance buffer layer 14, the electron transit layer 15, and the electron supply layer on the substrate 11. 16 and the semiconductor layer 17 are sequentially laminated. In addition, foreign matter 20 such as particles may be present on the substrate 11 or in the upper layer portion of the intervening layer 12. FIG. 1 is a cross-sectional view of a portion where foreign matter 20 is present on intervening layer 12.

The substrate 11 is, for example, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphorus (GaP) substrate, a GaN substrate, an AlN substrate, an AlN substrate, a silicon carbide (SiC) substrate, a carbon (C) substrate, or sapphire (Al ₂ O) ₃ ) It consists of a board etc. In the first embodiment, the substrate 11 is made of, for example, a Si substrate.

  The intervening layer 12 is made of, for example, AlN having a lattice constant between Si and GaN. The intervening layer 12 is a layer for suppressing the reaction between Ga and Si, and is interposed between the substrate 11 and the layer containing Ga. The intervening layer 12 reduces the difference in lattice constant between the substrate 11 and the nitride-based compound semiconductor layer such as GaN, and enables the buffer layer 14 and the semiconductor stack to be stacked on the substrate 11. When the substrate 11 is made of a material that does not react with Ga or the like, the intervening layer 12 may not necessarily be provided. In this case, the foreign matter 20 may be present on the substrate 11. Here, in the first embodiment, the thickness of the intervening layer 12 is, for example, 25 nm.

In the planarization layer 13 as the third semiconductor layer, for example, Al _X Ga _{1 -X} N (0 ≦ X) with an Al composition ratio X, in which carbon (C) is doped at a relatively lower concentration than the buffer layer 14 in the upper layer. It consists of <= 1). The concentration of carbon doped in the planarizing layer 13 is likely to grow in a direction (lateral direction) parallel to the surface of the substrate 11 in order to suppress the occurrence of the above-mentioned defects and the like caused by the foreign matter 20 and the like. Preferably, it is ¹⁸ cm ⁻³ or less, preferably 1 × 10 ¹⁷ cm ⁻³ or less.

Further, the planarization layer 13 is formed by laminating a plurality of Al _x Ga _{1 -x} N layers (0 ≦ x ≦ 1) different in Al composition ratio x even when the GaN layer and the AlN layer are laminated. It is good also as composition. In addition, the planarization layer 13 includes a plurality of Al _x Ga _1-x N layers (0 ≦ x ≦ 1) having different Al composition ratios x such that the Al composition ratio x decreases toward the upper side in the stacking direction. It is also possible to have a structure in which the layers are stacked. Then, a planarization layer 13, when these configurations, it is preferable to a carbon concentration of average 1.0 × 10 ¹⁸ cm ^-3 or less, preferably to 1.0 × 10 ¹⁷ cm ^-3 or less It is preferable to do.

In addition, the planarizing layer 13 produces a quantum size effect on the intervening layer 12 and a GaN layer having a thickness of 100 nm to 700 nm and a low carbon concentration, which is thick enough to cause no quantum size effect. It is also possible to constitute from a laminate of an AlN layer having a film thickness of 20 nm to 60 nm that is not thick enough and repeatedly stacked several times. When the planarizing layer 13 has this configuration, the carbon concentration in the GaN layer in the laminated film is preferably 1.0 × 10 ¹⁸ cm ⁻³ or less, preferably 1.0 × 10 ¹⁷ cm ^{−. It} is preferable to make it ³ or less. Note that with respect to the film thickness of the GaN layer constituting the planarization layer 13, the film thicknesses of the plurality of GaN layers may not be the same. Similarly, the film thickness of each of the plurality of AlN layers constituting the planarization layer 13 may not be the same. That is, in order to suppress an increase in stress generated in the planarizing layer 13, the film thicknesses of the plurality of GaN layers constituting the planarizing layer 13 may be different from each other, and the film thickness of the AlN layer may be different. It is similar. Specifically, the thickness of the lower GaN layer may be reduced to, for example, about 200 nm, and the thickness of the upper GaN layer may be increased to, for example, about 700 nm.

  The thickness of the planarizing layer 13 will be described in detail later, but is preferably 500 nm to less than 3000 nm, more preferably 500 nm to 2500 nm, and still more preferably 1000 nm to 2200 nm, in order to secure the surface flatness. . Note that another semiconductor layer may be formed in the planarization layer 13, and the film thickness of the planarization layer 13 in this case is the total of the film thicknesses of the respective planarization layers. Then, by forming the planarizing layer 13 as described above, the upper surface of the planarizing layer 13 is planarized to such an extent that the buffer layer 14 formed in the upper layer can be laminated while maintaining the planarity.

The buffer layer 14 is an Al _u Ga _1-u N layer having a thickness of _{1 to 10} nm and an Al _v Ga _1-v N layer having a thickness of 15 to 25 nm (v <u), which is thin enough to cause quantum size effect And a superlattice structure in which the layers are repeatedly stacked several times. The reason for using these film thicknesses is that unintended carriers (two-dimensional electron gas: 2 DEG) are generated in the structure of the buffer layer 14 due to piezoelectric polarization and spontaneous polarization, and no electric field shielding layer is generated. Also, by adding an impurity such as C to the buffer layer 14, the buffer layer 14 can be made to have a high resistance or a semi-insulation. Here, the carbon concentration of the buffer layer 14 is 5.0 × 10 ¹⁸ cm ⁻³ or more, which is greater than 1.0 × 10 ¹⁸ cm ⁻³ of the carbon concentration of the planarizing layer 13, in order to increase resistance. It is preferably not more than 10 ¹⁹ cm ^{-3 and} , in the first embodiment, for example, about 1.0 10 ¹⁹ cm ^-3 or so. The buffer layer 14 may be formed of a GaN layer (C-GaN layer), an AlN layer, or the like in which carbon is relatively heavily doped. Furthermore, various layers necessary for the configuration of the nitride semiconductor device may be provided in the buffer layer 14 as necessary.

  The electron transit layer 15 as the first semiconductor layer is made of, for example, undoped gallium nitride (u-GaN) having a film thickness of 700 nm (0.7 μm). Note that a nitride semiconductor material other than GaN may be used as the material forming the electron transit layer 15, and in the case of using AlGaN, the Al composition ratio is preferably 5% or less.

The electron supply layer 16 as the second semiconductor layer is, for example, a single layer of an Al _x Ga ₁ -xN layer, a pseudo mixed crystal layer made of at least two kinds of nitride semiconductors having different Al composition ratios and different band gaps, or Al It is composed of a superlattice layer in which a plurality of nitride semiconductors having different composition ratios and different band gaps are stacked. In the first embodiment, the electron supply layer 16 has a pseudo mixed crystal structure of, for example, Al _Y Ga _{1 -Y} N having an average Al composition ratio Y, and at least two different maximum Al composition ratios y1 or minimum Al. The layer is composed of an AlGaN super lattice layer in which a plurality of Al _y Ga _1-y N layers having an Al composition ratio y having various values of the composition ratio y2 are stacked. In addition, it is y2 <Y <y1 about Al composition ratio. Then, the electron supply layer 16, and an average Al composition ratio Y, Al _y Ga by such as a layer number of _1-y N layer, the carrier concentration (2DEG concentration of the 2DEG at the interface between the electron supply layer 16 of the electron transit layer 15 ) To the desired concentration. In the first embodiment, the 2DEG concentration of the 2DEG generated in the electron transit layer 15 is adjusted to be, for example, less than 3 × 10 ¹³ cm ⁻² . Specifically, the average Al composition ratio Y of the electron supply layer 16 is preferably 10% to 40% (0.1 ≦ Y ≦ 0.4) on the premise of 0 <Y <1, and is preferably 15% to 35%. (0.15 ≦ Y ≦ 0.35) is more preferable, and 20% to 30% (0.2 ≦ Y ≦ 0.3) is more preferable. Further, the band gap of the electron supply layer 16 is a band gap of the average, specifically the value of the band gap is weighted (integrated) by the thickness ratio of each Al _y Ga _1-y N layer constituting the laminate structure It is. The electron supply layer 16 is configured such that its average band gap is larger than the band gap of the electron transit layer 15. In the electron supply layer 16, the thickness of each Al _y Ga _1-y N layer, and a layer number or number of sets, the most suitable values depending on the design of the set concentration and the nitride semiconductor device of the 2DEG concentration It is selected.

Further, as the lower limit of the film thickness of the electron supply layer 16, the electron supply layer 16 is composed of an Al _y1 Ga _{1-y 1} N layer with the maximum Al composition ratio y1 and an Al _y2 Ga _1-y2 N layer with the minimum Al composition ratio y2. In consideration of the constitution of one pair of laminated _{Aly1Ga1 -y1N} / _{Aly2Ga1 -y2N} superlattice layer, the thickness is preferably 2 nm or more, and in consideration of increasing the 2DEG concentration, 5 nm. The above is more preferable, and 10 nm or more is more preferable. The upper limit of the film thickness of the electron supply layer 16 is preferably a critical film thickness or less at which misfit dislocations do not occur, and considering the limit of ohmic contact, 100 nm or less, preferably 50 nm or less, more preferably 30 nm or less Is preferred. And in this 1st embodiment, it is 20 nm, for example.

Further, in accordance with the structure of the nitride semiconductor device manufactured from the semiconductor multilayer substrate 10, the semiconductor layer 17 as the fourth semiconductor layer is provided on the electron supply layer 16. The semiconductor layer 17 has a group III nitride compound semiconductor narrower than the average band gap of the electron supply layer 16, specifically, an Al composition ratio, in order to change the 2DEG concentration of 2DEG generated in the electron transit layer 15 by at least two levels. It consists of _az Al _z Ga _1-z N layer (0 ≦ z ≦ 1), preferably a GaN layer. The film thickness of the semiconductor layer 17 will be described later.

  The electron transit layer 15, the electron supply layer 16 and the semiconductor layer 17 described above constitute the semiconductor laminate in the first embodiment. Note that, depending on the configuration of the nitride semiconductor device manufactured from the semiconductor multilayer substrate 10, the semiconductor multilayer may be configured from the electron transit layer 15 and the electron supply layer 16. It is also possible to provide an etching sacrificial layer between the electron supply layer 16 and the semiconductor layer 17. When the etching sacrificial layer is provided, it is preferable that the material of the etching sacrificial layer be a material such that the upper semiconductor layer 17 has a high etching selectivity to the etching sacrificial layer. The average Al composition ratio of the etching sacrificial layer is preferably 40% or more, which is larger than the average Al composition ratio Y of the electron supply layer 16. In this case, the electron transit layer 15, the electron supply layer 16, the etching sacrificial layer, and the semiconductor layer 17 constitute a semiconductor laminate. Thus, the semiconductor multilayer substrate 10 for manufacturing the nitride semiconductor device according to the first embodiment is configured.

(Method of manufacturing semiconductor multilayer substrate)
Next, a method of manufacturing the semiconductor multilayer substrate 10 in the first embodiment will be described. In the method of manufacturing the semiconductor multilayer substrate 10 according to the first embodiment, each layer is grown on the substrate 11 by the MOCVD method. Table 3 is a table showing growth conditions when manufacturing the semiconductor multilayer substrate 10. Table 3 shows growth conditions of the intervening layer 12, the planarization layer 13, the buffer layer 14, the electron transit layer 15, the electron supply layer 16, and the semiconductor layer 17 in the first embodiment. Specifically, growth temperature, growth pressure, ratio of group V (nitrogen: N) to group III (element of at least one of Al and Ga) (V / III ratio), and growth according to these growth conditions It shows the carbon concentration and film thickness of the different layers. The various growth conditions described in Table 3 are merely examples, and the present invention is not necessarily limited to these conditions.

Then, in the method of manufacturing the semiconductor multilayer substrate 10 in the first embodiment, first, the source gas and the carrier gas are respectively supplied into the MOCVD reaction furnace (not shown) into which the substrate 11 shown in FIG. 1 is carried. Do. Specifically, for example, trimethylaluminum (TMAl) is used as the group III source gas, ammonia (NH ₃ ) as the group V source gas, and hydrogen (H ₂ ) and nitrogen (N ₂ ) as the carrier gas. Thus, AlN is grown on the substrate 11 to form the intervening layer 12. At this time, carbon (C) is auto-doped in the intervening layer 12. Note that one example of growth conditions and carbon concentration of the intervening layer 12 made of AlN are as shown in Table 3, and 1 torr is 133.3 Pa in pressure.

Next, the planarizing layer 13 having a thickness of 500 nm or more and less than 3000 nm is formed on the intervening layer 12. Here, in the formation of the planarizing layer 13, specifically, for example, at least one of trimethylgallium (TMGa) and trimethylaluminum (TMAl) is used as a Group III source gas, and ammonia (NH ₃ ) is used as a Group V source gas. Use Also, as the carrier gas, for example, hydrogen (H ₂ ) and nitrogen (N ₂ ) are used. Thus, Al _X Ga _1-X N layer on the intermediate layer 12 (0 ≦ X ≦ 1) Al X Ga 1-X N layer is grown carbon (C) is doped (0 ≦ X ≦ 1) A planarization layer 13 is formed.

Here, the case where the planarizing layer 13 is not limited to the GaN layer but is formed of an Al _x Ga ₁ -xN layer (0 <x ≦ 1) with an average Al composition ratio X will be described. FIG. 2 shows the Al composition ratio dependence of the film thickness of the Al _x Ga _{1 -x} N layer necessary to fill a pit (recess) of 1 μm diameter when the carbon concentration is fixed at 1 × 10 ¹⁷ cm ^-3 , for example. It is a graph which shows an example of sex. As shown in FIG. 2, when the Al composition ratio X is 0, that is, when the 1 μm diameter pit is filled with the GaN layer, the film thickness required is, for example, about 0.5 μm (500 nm). In contrast, in the Al _X Ga _1-X N layer of Al composition ratio X is for example 0.1, the required thickness to fill the pits increases to the extent for example 0.7 [mu] m (700 nm). Furthermore, as the Al composition ratio X increases, the film thickness necessary to fill pits of 1 μm diameter increases, and in the case of an Al composition ratio X of 1, ie, in the case of an AlN layer, for example, about 2 μm A film thickness of about four times that of the GaN layer is required. As a result, as the Al composition ratio X of the Al _x Ga ₁ -xN layer (0 <x ≦ 1) increases, the film thickness necessary to form the planarized layer 13 whose surface is flattened becomes larger. I understand. That is, in the planarizing layer 13 made of the Al _x Ga ₁ -xN layer (0 <X ≦ 1), the Al composition ratio X is preferably smaller, and in order to ensure the planarity of the surface of the planarizing layer 13 The designed film thickness is made to increase as the Al composition ratio X increases. Then, by setting the planarization layer 13 to a designed film thickness according to the Al composition ratio X, planarization of the surface is secured.

Further, as shown in FIG. 1, after forming the planarization layer 13, an Al _u Ga _1-u N layer having an Al composition ratio u and an Al composition ratio v lower than the Al composition ratio u are formed on the planarization layer 13. The buffer layer 14 is formed of a superlattice structure in which an Al _v Ga _1-v N layer (v <u) is repeatedly stacked several times. Specifically, the buffer layer 14 is formed by repeatedly laminating the GaN layer having a thickness of 20 nm and the AlN layer having a thickness of 5 nm plural times. Considering that the buffer layer 14 increases the carbon concentration of added carbon to increase resistance, the growth temperature and the growth pressure are relatively lower than the growth conditions of other semiconductor layers, and the group III raw material The supply amounts (group III flow rates) of the gases (TMGa, TMAl) are made relatively larger than the growth conditions of the other semiconductor layers. An example of growth conditions of this buffer layer 14 and the carbon concentration are as shown in Table 3. In addition, about the carbon concentration of the buffer layer 14, since the film thickness of each layer which comprises the buffer layer 14 is very small, it measured without distinguishing each layer.

  Next, GaN is grown on the buffer layer 14 to form an electron transit layer 15 composed of a u-GaN layer. Thereafter, for example, TMAl is used as a group III source gas, and an electron supply layer 16 made of an AlGaN layer is grown on the electron transit layer 15. Subsequently, using TMGa as a group III source gas, a semiconductor layer 17 made of, for example, a GaN layer is formed on the electron supply layer 16. An example of the growth conditions of these electron transit layer 15, the electron supply layer 16, and the semiconductor layer 17 and the carbon concentration are as shown in Table 3. Thus, the semiconductor multilayer substrate 10 shown in FIG. 1 is formed.

(Nitride semiconductor device)
Next, a Schottky barrier diode (SBD) as a nitride semiconductor device having a planarization layer manufactured from the semiconductor laminated substrate according to the first embodiment configured as described above will be described. FIG. 3 is a schematic cross-sectional view of the SBD as the nitride semiconductor device according to the first embodiment.

As shown in FIG. 3, the SBD 1 according to the first embodiment has an anode electrode 18A as a Schottky electrode selectively on the electron supply layer 16, in addition to the structure of the semiconductor multilayer substrate 10 described above, and An anode electrode 18A and a cathode electrode 18C as an ohmic electrode separated from each other are provided. Further, on the electron supply layer 16, a field plate layer 17a formed of a part of the semiconductor layer 17 is provided on the anode electrode 18A side so as to be separated from the cathode electrode 18C. An insulating film 19 is provided to cover the electron supply layer 16 and the field plate layer 17a and at least a part of the anode electrode 18A and the cathode electrode 18C. Here, as an example of the dimensions of the SBD 1, the width of the nitride semiconductor device in the case where a plurality of SBDs 1 are integrated is, for example, 150 mm parallel to the surface of the substrate 11 and in the width direction. Further, along parallel width direction on the surface of the substrate 11, the spacing of the width L _A of the anode electrode 18A, for example 20 [mu] m, the width L _C of the cathode electrode 18C, for example 20 [mu] m, and the anode electrode 18A and cathode electrode 18C l _AC is, for example, 20 μm.

  In the SBD 1, the 2DEG concentration of the 2DEG layer a is made lower than the 2DEG concentration of the 2DEG layer A other than the 2DEG layer a by providing the field plate layer 17a. Thereby, the electric field intensity of the portion provided with the field plate layer 17a can be reduced to suppress the electric field concentration. Further, as described above, the 2DEG concentration of the 2DEG layer a in the electron transit layer 15 decreases as the film thickness of the field plate layer 17a increases. Therefore, in the first embodiment, the film thickness of the field plate layer 17a (semiconductor layer 17) is 20 nm or more and 200 nm or less, preferably, control of the 2DEG concentration is facilitated by film thickness control using growth and etching. More preferably, the thickness is 25 nm to 80 nm which is less likely to be affected by variations in 2DEG concentration due to variations in film thickness. In the first embodiment, the field plate layer 17a, that is, the semiconductor layer 17 is made of, for example, a GaN layer having a thickness of 30 nm.

  The anode electrode 18A as the first electrode has, for example, a layered structure of Ni / Au in which the lower electrode layer is a Ni layer and the upper electrode layer is an Au layer. Thereby, the anode electrode 18A is in Schottky contact with the 2DEG layer A generated in the electron transit layer 15 via the electron supply layer 16. The anode electrode 18A may be removed by recess etching the formation region of the anode electrode 18A in the electron supply layer 16, and may be in Schottky contact with the 2DEG present under the field plate layer 17a from the side surface.

  The anode electrode 18A runs on the field plate layer 17a to form at least one step, and extends so as to protrude toward the cathode electrode 18C. In the first embodiment, the anode electrode 18A is provided in contact with part of the side surface and the upper surface of the field plate layer 17a. Another semiconductor film or dielectric film may be interposed between the anode electrode 18A and the field plate layer 17a so as not to be in contact with each other. Furthermore, in the first embodiment, the field plate portion is provided in the anode electrode 18A in a shape having multiple steps, for example, two steps.

  The cathode electrode 18C as the second electrode has, for example, a laminated structure of Ti / Al in which the lower electrode layer is a Ti layer and the upper electrode layer is an Al layer. As a result, the cathode electrode 18 C makes ohmic contact with the 2DEG layer A generated in the electron transit layer 15 via the electron supply layer 16.

Insulating film 19 is made of, for example, SiO ₂ , but may be made of other materials, specifically silicon nitride (SiN), aluminum oxide (alumina: Al ₂ O ₃ ), etc. May be appropriately combined or sequentially laminated. The insulating film 19 mainly protects the surfaces of the field plate layer 17 a, the anode electrode 18 A, the cathode electrode 18 C, and the electron supply layer 16. The SBD 1 according to the first embodiment is configured as described above.

The inventor of the present invention, in the SBD 1 as a nitride semiconductor device configured as described above, includes the planarization layer 13 including an AlN layer (x = 1) and an Al _x Ga _{1 -x} N layer (0 ≦ x <1). And a plurality of stacked layers. The Al _x Ga ₁ -xN layer increases the film thickness by 200 nm to 100 nm in the upward direction of the stacking direction. Further, the thickness of the AlN layer is increased by 20 nm to 10 nm in the upward direction of the stacking direction. The carbon concentration of the planarization layer 13 was 1 × 10 ¹⁷ cm ⁻³ . In addition, the breakdown voltage was measured for each film thickness of the planarization layer 13 of the SBD 1 by setting the Al composition ratio x of the Al _x Ga ₁ -xN layer described above constituting the planarization layer 13 to various values. Specifically, the Al _x Ga _1-x N layer is a GaN layer with an Al composition ratio x of 0, an Al _0.4 Ga _0.6 N layer with an Al composition ratio x of 0.4, or an Al composition ratio x of 0.8 The breakdown voltage of the SBD 1 was measured for each film thickness of the planarizing layer 13 in the case of the configuration from the Al _0.8 Ga _0.2 N layer. In the first embodiment, the reference withstand voltage is 600V. FIG. 4 is a graph showing the film thickness dependency of the level of the planarizing layer 13 of the ratio of the device which is equal to or higher than the reference withstand voltage. Here, the pressure resistance measurement of SBD 1 was performed as follows. That is, first, the substrate 11 and the anode electrode 18A are grounded. Then, a voltage of 600 V is applied between the anode electrode 18A and the cathode electrode 18C so that the anode electrode 18A is negative and the cathode electrode 18C is positive, and the breakdown voltage is measured.

From FIG. 4, regardless of the Al composition ratio x, when the film thickness of the planarization layer 13 is 0 nm, that is, in the case of the conventional configuration in which the planarization layer 13 is not provided, the ratio of devices having the withstand voltage or more is 30% It turns out that it is an extent. On the other hand, by forming the Al _x Ga ₁ -xN layer (0 ≦ x <1) of the planarizing layer 13 from the GaN layer and setting the film thickness to 500 nm or more, the ratio of the device having the reference withstand voltage or more is It can be seen that it can be 70% or more, which is a preferable ratio for manufacturing. Furthermore, when the film thickness of the planarizing layer 13 is set to 750 nm and 1000 nm (1 μm), it can be seen that the ratio of the device having the reference withstand voltage or more is 80% or more. In addition, when the film thickness of the planarizing layer 13 is 2000 nm (2 μm) or more, it can be seen that the ratio of the device which is equal to or higher than the reference withstand voltage increases to 90% or more.

Further, from FIG. 4, when the Al _x Ga _{1 -x} N layer (0 ≦ x <1) of the planarization layer 13 is an Al _0.4 Ga _0.6 N layer, the reference withstand voltage is obtained when the film thickness is 500 nm. While the ratio of the devices is about 40%, it can be seen that by setting the film thickness to 1200 nm or more, the ratio of the devices having the reference withstand voltage or more can be 70% or more. Furthermore, in the case where the Al _x Ga _{1 -x} N layer (0 ≦ x <1) of the planarizing layer 13 is an Al _0.8 Ga _0.2 N layer, 50% of the devices have a standard withstand voltage or more when the film thickness is 1000 nm. On the other hand, it can be seen that, by setting the film thickness to 2000 nm or more, the ratio of the device having the reference withstand voltage or more can be 70% or more. That is, after setting the carbon concentration of the planarization layer 13 to 1 × 10 ¹⁷ cm ⁻³ , in the planarization layer 13 including the Al _x Ga _1-x N layer (0 ≦ x <1), the reference withstand voltage or more is obtained. It can be seen that the film thickness D _min (nm) required to make the ratio of the device 70% or more can be approximated by, for example, the following equation (1). In addition, it can be seen that the Al composition ratio dependency of the required film thickness D _min exhibits the same tendency as the Al composition ratio dependency of the film thickness necessary for filling the 1 μm diameter shown in FIG.
D _min 2000 2000 x + 500 (1)
The equation (1) is merely an example showing the tendency of the Al composition ratio dependency of the film thickness D _min necessary for the planarization layer 13, and the numerical values are not limited to these.

Further, in the SBD 1 as the nitride semiconductor device configured as described above, the inventor set the film thickness of the planarization layer 13 to, for example, 2000 nm. Then, the Al _x Ga ₁ -xN layer (0 ≦ x <1) of the planarizing layer 13 is used as a GaN layer with an Al composition ratio x of 0, Al _0.4 Ga _0.6 N with an Al composition ratio x of 0.4. Layer or the ratio of the device which is equal to or higher than the reference breakdown voltage for each carbon concentration of the Al _x Ga _{1 -x} N layer of the SBD 1 when the layer is composed of an Al _0.8 Ga _0.2 N layer having an Al composition ratio x of 0.8. . FIG. 5 is a graph showing the carbon concentration dependency of the planarizing layer 13 of the ratio of the device which is equal to or higher than the reference withstand voltage.

From FIG. 5, regardless of the Al composition ratio x, when the carbon concentration of the planarizing layer 13 is 1.0 × 10 ¹⁹ cm ⁻³ , ie, in the case of the same configuration as the buffer layer of the conventional configuration, The ratio of the devices is less than 30%. On the other hand, by forming the Al _x Ga _1-x N layer (0 ≦ x <1) of the planarizing layer 13 from the GaN layer and setting the carbon concentration to 1.0 × 10 ¹⁸ cm ⁻³ or less, the standard is achieved. It turns out that the ratio of the apparatus which becomes more than withstand pressure can be made into 70% or more which is a preferable ratio on manufacture. Furthermore, when the carbon concentration of the planarizing layer 13 is 7.0 × 10 ¹⁷ cm ⁻³ or less, the ratio of the device which exceeds the standard withstand voltage is 80% or more and 1.0 × 10 ¹⁶ cm ⁻³ or less. In this case, it can be seen that the proportion of the devices which is equal to or higher than the reference withstand voltage is increased to 90% or more.

Further, from FIG. 5, when the Al _x Ga ₁ -xN layer (0 ≦ x <1) of the planarization layer 13 is composed of the Al _0.4 Ga _0.6 N layer, the carbon concentration is 1.0 × 10 ¹⁸ cm ^−3. In this case, while the proportion of devices that achieve the standard withstand pressure or higher is about 50%, the proportion of devices that achieve the standard withstand pressure or higher by setting the carbon concentration to 5.0 × 10 ¹⁷ cm ^-3 or less is 70%. It can be seen that it can be made more than%. Furthermore, in the case where the Al _x Ga _{1 -x} N layer (0 ≦ x <1) of the planarizing layer 13 is formed of the Al _0.8 Ga _0.2 N layer, in the case where the carbon concentration is 1.0 × 10 ¹⁸ cm ⁻³ While the percentage of devices that achieve the standard withstand pressure or higher is about 40%, the percentage of devices that achieve the standard withstand pressure or higher can be 70% or higher by setting the carbon concentration to 1.0 × 10 ¹⁷ cm ^-3 or less. I understand. That is, when the planarizing layer 13 is formed of an Al _x Ga _{1 -x} N layer (0 x x 1 1) with an Al composition ratio x with a film thickness of 2000 nm, the ratio of devices having the withstand voltage or more is 70%. It is understood that at least 1.0 × 10 ¹⁸ cm ⁻³ or less is preferable, and 1.0 × 10 ¹⁷ cm ⁻³ or less is more preferable as the upper limit carbon concentration for making the above. From the above points, in the case where the planarizing layer 13 has a predetermined film thickness, as the Al composition ratio x of the Al _x Ga ₁ -xN layer of the planarizing layer 13 becomes larger, the design in the planarizing layer 13 By reducing the carbon concentration, it is possible to ensure the flatness of the surface of the planarization layer 13.

From the above, when the planarizing layer 13 includes the Al _x Ga _1-x N layer (0 ≦ x ≦ 1), from the viewpoint of improving the design freedom of the film thickness of the planarizing layer 13, It is understood that the smaller the Al composition ratio x, the better. Specifically, the Al composition ratio x of the Al _x Ga _1-x N layer (0 ≦ x ≦ 1) of the planarizing layer 13 is preferably 0 or more and 0.4 or less (0 ≦ x ≦ 0.4), and 0 More preferably, it is not less than 0.05 (0 ≦ x ≦ 0.05). Here, according to the knowledge obtained by the present inventor from the experiment, the film thickness of the planarizing layer 13 of the ratio of the device having the reference withstand voltage or more if the Al composition ratio x is in the range of 0 to 0.05. The tendency of dependence shows almost the same tendency as the tendency when the Al composition ratio x is 0 shown in FIG.

  Furthermore, it is understood that it is preferable to increase the lower limit of the designed film thickness as the Al composition ratio x increases in order to ensure the flatness of the surface of the planarizing layer 13. Similarly, it is preferable that the carbon concentration of the planarization layer 13 be lower, and in order to ensure the flatness of the surface of the planarization layer 13, it is preferable to reduce the carbon concentration with the increase of the Al composition ratio x. I understand. And it was confirmed that generation | occurrence | production of the defect resulting from the foreign material 20 which exists on the surface of the board | substrate 11 or the intervening layer 12 can be suppressed according to the above conditions.

As described above, according to the first embodiment of the present invention, the lower layer of the buffer layer 14 has the carbon concentration of 1.0 × 10 ¹⁸ cm ⁻³ or less, and the planarized layer 13 is planarized. By providing them, it is possible to suppress the occurrence of defects caused by the foreign matter 20 present on the surface of the substrate 11 or the intervening layer 12 or the like. As a result, the occurrence of defects in the buffer layer 14 and the electron transit layer 15 formed in the upper layer of the planarization layer 13 can be suppressed, so that the leak current in the nitride semiconductor device can be suppressed, and the reduction in breakdown voltage can be suppressed.

Second Embodiment
Next, a HEMT field effect transistor as a nitride semiconductor device according to a second embodiment of the present invention will be described. FIG. 6 is a schematic cross-sectional view showing a HEMT as a nitride semiconductor device according to the second embodiment.

  As shown in FIG. 6, the HEMT 2 according to the second embodiment is selectively separated from the field plate layer 17b on the electron supply layer 16 in addition to the structure in the semiconductor multilayer substrate 10 in the first embodiment. A source electrode 21S, a gate electrode 21G, a drain electrode 21D, and an insulating film 22 are provided. The HEMT 2 is a depletion mode (D-mode) HEMT (D-mode HEMT) operating at a negative threshold voltage.

Here, as an example of the dimensions of the HEMT 2, the width along the width direction of the nitride semiconductor device in which the plurality of HEMTs 2 are integrated is, for example, 150 mm. The width L _S of the source electrode 21S parallel to the surface of the substrate 11 and along the width direction is, for example, 20 μm. Similar width L _G of the gate electrode 21G is, for example, 5 [mu] m. Similar width L _D of the drain electrode 21D is, for example, 20 [mu] m. Then, along parallel width direction on the surface of the substrate 11, the interval l _SG of the source electrode 21S and the gate electrode 21G, for example 5 [mu] m, distance l _GD between the gate electrode 21G and the drain electrode 21D is, for example, at 15μm .

  The 2DEG concentration of 2DEG generated in the electron transit layer 15 decreases as the film thickness of the field plate layer 17 b formed of a part of the semiconductor layer 17 increases. Therefore, in the second embodiment, the film thickness of the field plate layer 17b is preferably 20 nm or more and 200 nm or less, preferably 20 nm or more and 100 nm or less, for the same reason as the reason in the first embodiment. Is 25 nm or more and 80 nm or less.

In the second embodiment, the electron transit layer 15, the electron supply layer 16, and the field plate layer 17b constitute a semiconductor laminate. Then, the 2DEG concentration inside the semiconductor laminate is reduced by the field plate layer 17b. That is, the 2DEG layer a having a low 2DEG concentration is generated in the lower region of the field plate layer 17b. Here, from the viewpoint of increasing the breakdown voltage of the HEMT ² , the 2DEG concentration of the 2DEG layer a is preferably 7 × 10 ¹² cm ⁻² or less. Further, from the viewpoint of reducing the on-resistance of the HEMT 2, the 2DEG concentration of the 2DEG layer A having a relatively high 2DEG concentration is preferably higher than 7 × 10 ¹² cm ⁻² . As described above, by adjusting the average Al composition ratio Y in the electron supply layer 16 and the number of laminated layers, the 2DEG concentration is set to, for example, less than 3 × 10 ¹³ cm ⁻² . Further, as in the first embodiment, the semiconductor laminate may be formed of the electron transit layer 15 and the electron supply layer 16, and an etching sacrificial layer may be provided between the electron supply layer 16 and the semiconductor layer 17. It is. In this case, the semiconductor laminated body is constituted by the field plate layer 17 b obtained by etching the electron transit layer 15, the electron supply layer 16, the etching sacrificial layer, and the semiconductor layer 17 into a predetermined shape.

  Further, the drain electrode 21D as the second electrode and the source electrode 21S as the third electrode are provided on the electron supply layer 16, and are formed of, for example, a laminated structure of Ti / Al. Thus, the drain electrode 21D and the source electrode 21S make ohmic contact with the 2DEG layer A via the electron supply layer 16.

  Further, the gate electrode 21G as the first electrode is disposed between the drain electrode 21D and the source electrode 21S, and provided so as to protrude on the field plate layer 17b and the insulating film 22. Gate electrode 21G is formed of, for example, a laminated structure of Ni / Au. As a result, the gate electrode 21 G comes into Schottky contact with the 2DEG layer A in the electron transit layer 15 via the electron supply layer 16. The gate electrode 21G is extended so that the field plate portion protrudes in a step-like shape toward multiple sides of the source electrode 21S and the drain electrode 21D, for example. In the second embodiment, a part of the gate electrode 21G is formed to be in contact with the electron supply layer 16, but the field plate layer 17b is interposed between the electron supply layer 16 and the gate electrode 21G. It is also possible to configure.

The insulating film 22 is made of the same material as the insulating film 19 in the first embodiment, for example, SiO ₂ . The insulating film 22 mainly protects the field plate layer 17 b, the gate electrode 21 G, the drain electrode 21 D, the source electrode 21 S, and the surface of the electron supply layer 16. Thus, the HEMT 2 according to the second embodiment is configured.

  The breakdown voltage of the HEMT 2 according to the second embodiment is measured as follows. That is, first, the substrate 11 and the source electrode 21S are grounded. Then, a voltage is applied between the source electrode 21S and the gate electrode 21G so that the gate electrode 21G has a negative potential of -10 V and the source electrode 21S has a potential of 0, thereby turning the HEMT 2 into the OFF state. In the OFF state of the HEMT 2, a voltage is applied between the source electrode 21S and the drain electrode 21D so that the drain electrode 21D has a positive potential of 600 V which is a reference withstand voltage, and the withstand voltage is measured.

  In the second embodiment, by using the semiconductor multilayer substrate 10 similar to that of the first embodiment, the same effect as that of the first embodiment can be obtained.

Third Embodiment
Next, a third embodiment of the present invention will be described. That is, in the first and second embodiments described above, a single layer or laminated structure Al _x Ga _{1 -x} N layer doped with low concentration of carbon is used as the planarization layer 13 shown in FIGS. 1 and 3. (0 ≦ X ≦ 1) is used. In the third embodiment, the planarization layer 13 is further doped with an impurity of surfactant atoms. Here, examples of surfactant atoms include magnesium (Mg), indium (In), zinc (Zn), silicon (Si), germanium (Ge), oxygen (O), and antimony (Sb).

Then, the inventor has made the doping concentration of Mg, In, Zn, Si, Ge, O, and Sb as surfactant atoms to be doped into the above-described planarizing layer 13 be 1.0 × 10 ¹⁵ cm ⁻³ or more 7 .0 × 10 ¹⁸ cm ^-3 while varying between follows, to measure the withstand voltage of the SBD 1. The flattening layer 13 is formed of a GaN layer having an Al composition ratio X of 0 and has a thickness of, for example, 2900 nm, and an AlN layer having a thickness of 20 nm is interposed whenever the thickness of the GaN layer becomes 700 nm. The carbon concentration was 5.0 × 10 ¹⁸ cm ⁻³ . FIG. 7 is a graph showing the surfactant concentration dependency in the ratio of the device which is equal to or higher than the reference withstand voltage of SBD 1, showing the measurement result.

From FIG. 7, it can be seen that, when the surfactant concentration is 1.0 × 10 ¹⁶ cm ⁻³ or more, the ratio of the device which is equal to or higher than the reference withstand voltage can be made 70% which is a preferable ratio in manufacturing. Further, it is understood that it is preferable to set the surfactant concentration to 1.0 × 10 ¹⁸ cm ⁻³ or less in order to set the ratio of the devices which are equal to or higher than the reference withstand voltage to 70% or more.

According to the third embodiment, by doping the semiconductor layer with a surfactant atom as an impurity, the nitride semiconductor layer such as the Al _x Ga ₁ -xN layer is perpendicular to the stacking direction (horizontal direction). Growth direction). Therefore, the surface of the nitride semiconductor layer doped with surfactant atoms is easily planarized, so that the formation of the planarizing layer 13 described above can be performed more efficiently. Furthermore, it is also possible to lower the upper limit of the carbon concentration of the planarization layer 13 by the doping of surfactant atoms. That is, the carbon concentration of the planarizing layer 13 is set to a low concentration of 5.0 × 10 ¹⁸ cm ⁻³ or less, and the surfactant concentration is 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less By setting the ratio to 70% or more of the nitride semiconductor device, the ratio of the device to be equal to or higher than the reference withstand voltage can be increased. This is the same as in the case where the carbon concentration of the planarizing layer 13 is set to 1.0 × 10 ¹⁸ cm ⁻³ or more and higher than the carbon concentration in the first and second embodiments. That is, in the nitride semiconductor device, the ratio of devices having the reference withstand voltage or more can be 70% or more, and the ratio of the devices having the reference withstand voltage or more can be improved.

  As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, Various deformation | transformation based on the technical idea of this invention are possible. For example, the numerical values listed in the above-described embodiment are merely examples, and different numerical values may be used as needed. Further, the present invention is not limited by the above-described embodiment. The present invention also includes those configured by appropriately combining the above-described components. Further, further effects and modifications can be easily derived by those skilled in the art.

Further, for example, in the above-described embodiment, the electron supply layer 16 is an AlGaN super lattice layer, but in addition to the AlGaN super lattice layer, a plurality of In _p Al _q Ga _{1 -p q} N layers (0 ≦ p <1 It is also possible to adopt an InAlGaN super lattice layer in which 0 <q ≦ 1, 0 <p + q <1) is stacked to form a super lattice layer.

  The anode electrode of the diode and the lower electrode layer of the gate electrode of the transistor are electrodes in Schottky contact with the electron supply layer. Therefore, other than nickel (Ni) and titanium (Ti) described above, platinum (Pt), palladium (Pd), tungsten (W), gold (Au), silver (Ag), copper (Cu), tantalum (for example) Ta), a metal film containing at least one of aluminum (Al), or a metal film consisting of an alloy containing at least one of Ti, Ni, Pt, Pd, W, Au, Ag, Cu, Ta, Al Even if it is a metal material which satisfies the above conditions, such as a metal film containing at least one or a metal film consisting of a nitride alloy containing at least one of Ti, W, and Ta good.

  In addition, the anode electrode of the diode and the upper electrode layer of the gate electrode of the transistor are made of a metal having a work function smaller than that of the lower electrode layer, and various metal materials that satisfy this condition may be used.

  In addition, the cathode electrode of the diode and the source electrode and the drain electrode of the transistor are in ohmic contact with the electron supply layer, or in contact with the electron supply layer with sufficiently small contact resistance. However, the present invention is not limited to this, and for example, a metal film containing at least one of Ti, Al, silicon (Si), lead (Pb), chromium (Cr), In, and Ta, Ti, Al, Si, A metal film made of an alloy containing at least one of Pb, Cr, In and Ta, or a metal film made of a silicide alloy containing at least one of Ti, Al, Si and Ta, or Ti, W, Ta Any metal material that satisfies the above conditions, such as a metal film containing at least one of metal films made of a nitride alloy containing at least one of the foregoing, may be used.

  Moreover, in the above-mentioned embodiment, although SBD and HEMT were mentioned as an example as a semiconductor device by the present invention, the present invention is not limited to this. That is, a MIS-HEMT (Metal Insulator Semiconductor HEMT) configured by providing a gate insulating film between the electron supply layer and the gate electrode, and a recess portion formed by etching the electron supply layer to a depth not reaching the electron transit layer And a recess MIS-HEMT (Recessed MIS-HEMT) provided with a gate electrode through a gate insulating film, and a recess formed by performing etching to a depth up to the electron travel layer is made of aluminum oxide (AlO) or the like. A MOS-HEMT (Metal Oxide Semiconductor HEMT) provided with a gate electrode through a gate oxide film, and a gate insulation made of aluminum nitride (AlN) or the like in a recess formed by etching to a depth up to the electron transit layer E-mode MIS-HEMT (Enhanced-mode MIS-HEMT), MOSFET (Metal) provided with a gate electrode through a film The present invention can be applied to various semiconductor devices such as an oxide semiconductor FET), a MISFET (metal insulator semiconductor FET), and a MESFET (metal semiconductor FET). When the present invention is applied to these transistors, it is also possible to provide an insulating film such as an oxide film between the gate electrode and the field plate layer. The present invention can also be applied to at least one of semiconductor devices including a plurality of semiconductor elements such as a transistor in which a HEMT and a MOSFET are combined to form a cascode connection.

  Moreover, in the above-mentioned embodiment, although the electrode is formed on the surface of the electron supply layer and the etching sacrificial layer, it is not necessarily limited to these, and the electron transit layer, the electron supply layer, the etching sacrificial layer, and It is possible to provide an electrode on at least one of the semiconductor stack including the semiconductor layer and the field plate layer, and optionally other layers. That is, an electrode may be provided on the other layers constituting the semiconductor laminate. Specifically, an anode electrode, a cathode electrode, a gate electrode, a drain electrode, or a source electrode is formed on the surface of the electron supply layer via a nitride-based semiconductor layer such as an insulating layer or a field plate layer, or a laminated film thereof. It is also possible to provide Further, a recess is formed by etching away a part of the electrode formation region of the electron supply layer until reaching the electron transit layer, and the anode electrode is formed on the surface of the recess or the surface of the recess through a predetermined film. It is also possible to provide a cathode electrode, a gate electrode, a drain electrode or a source electrode.

1 SBD
2 HEMT
DESCRIPTION OF SYMBOLS 10 semiconductor lamination substrate 11 substrate 12 intervening layer 13 planarization layer 14 buffer layer 15 electron traveling layer 16 electron supply layer 17 semiconductor layer 17a, 17b field plate layer 18A anode electrode 18C cathode electrode 19, 22 insulating film 20 foreign matter 21D drain electrode 21G Gate electrode 21S Source electrode

Claims (11)

A substrate,
A carbon-doped buffer layer comprising a superlattice structure provided on an upper layer of the substrate and having a plurality of semiconductor layers repeatedly stacked so as to produce a quantum size effect;
A first semiconductor layer made of a nitride semiconductor provided in the upper layer of the buffer layer, and a second semiconductor layer provided in the upper layer of the first semiconductor layer and having a wider band gap on average than the first semiconductor layer A semiconductor laminate,
A first electrode provided on at least a part of layers of the layers forming the semiconductor laminate;
And a second electrode provided apart from the first electrode on at least a part of layers of the layers forming the semiconductor laminate.
Between the substrate and the buffer layer, a third semiconductor layer containing carbon at a concentration of 1.0 × 10 ¹⁸ cm ⁻³ or less is provided.
An intervening layer is provided between the substrate and the third semiconductor layer to suppress the reaction between the material of the substrate and the material of the third semiconductor layer,
Foreign matter is present on the intervening layer, and
The thickness of the third semiconductor layer is Ri 3000nm less der than 500 nm,
It said third semiconductor layer, a nitride semiconductor device, wherein the Ru der those aluminum nitride layer and the gallium nitride layer are stacked. The nitride semiconductor device according to claim 1 , wherein a film thickness of the third semiconductor layer is 1000 nm or more and less than 3000 nm. Carbon concentration of the average of the buffer layer, a nitride semiconductor device according to claim 1 or 2, characterized in that 5.0 × 10 ¹⁸ cm ^-3 or more 5.0 × 10 ¹⁹ cm ^-3 or less. It said third semiconductor layer, claim, characterized in that the thickness is made following the gallium nitride layer and the thickness of 700nm or more 100nm are laminated a plurality of times and less aluminum nitride layer 60nm or 20 nm 1 The nitride semiconductor device of any one of -3 . An upper layer of the second semiconductor layer, according to claim 1-4, characterized in that the fourth semiconductor layer in which the average, a band gap than the second semiconductor layer is made of a narrow nitride semiconductor is selectively provided The nitride semiconductor device according to any one of the above. The third semiconductor layer contains a surfactant atom as an impurity, and the concentration of the surfactant atom is 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less. The nitride semiconductor device according to any one of items 1 to 5 . A substrate,
A carbon-doped buffer layer comprising a superlattice structure provided on an upper layer of the substrate and having a plurality of semiconductor layers repeatedly stacked so as to produce a quantum size effect;
A first semiconductor layer made of a nitride semiconductor provided in the upper layer of the buffer layer, and a second semiconductor layer provided in the upper layer of the first semiconductor layer and having a wider band gap on average than the first semiconductor layer A semiconductor laminate,
A first electrode provided on at least a part of layers of the layers forming the semiconductor laminate;
And a second electrode provided apart from the first electrode on at least a part of layers of the layers forming the semiconductor laminate.
A third semiconductor layer containing a surfactant atom as an impurity and containing carbon at a concentration of 5.0 × 10 ¹⁸ cm ⁻³ or less between the substrate and the buffer layer, and having a thickness of 500 nm or more and less than 3000 nm is Provided
An intervening layer is provided between the substrate and the third semiconductor layer to suppress the reaction between the material of the substrate and the material of the third semiconductor layer,
Foreign matter is present on the intervening layer, and
Ri 1.0 × 10 ¹⁸ cm ^-3 der less impurity concentration of 1.0 × 10 ¹⁶ cm ^-3 or more of the surfactant atoms,
It said third semiconductor layer, a nitride semiconductor device, wherein the Ru der those aluminum nitride layer and the gallium nitride layer are stacked. The semiconductor device according to claim 1, further comprising: a third electrode provided on at least a part of layers of the layers of the semiconductor stack, the third electrode being separated from the first electrode and the second electrode. the nitride semiconductor device according to any one of 1-7. A structure of the nitride semiconductor device according to claim 8 ;
A field effect transistor, wherein the first electrode is a gate electrode, the second electrode is a drain electrode, and the third electrode is a source electrode. It has the structure of a nitride semiconductor device according to any one of claims 1 to 7
A diode, wherein the first electrode is an anode electrode, and the second electrode is a cathode electrode. A substrate,
A carbon-doped buffer layer comprising a superlattice structure provided on an upper layer of the substrate and having a plurality of semiconductor layers repeatedly stacked so as to produce a quantum size effect;
A first semiconductor layer made of a nitride semiconductor provided in the upper layer of the buffer layer, and a second semiconductor layer provided in the upper layer of the first semiconductor layer and having a wider band gap on average than the first semiconductor layer A semiconductor laminate,
A first electrode provided on at least a part of layers of the layers forming the semiconductor laminate;
A second electrode provided on at least a part of layers of the layers of the semiconductor stack, the second electrode being separated from the first electrode;
In a method of manufacturing a nitride semiconductor device comprising
An intervening layer is grown on the substrate, which suppresses the reaction between the material of the substrate and the material of the third semiconductor layer composed of the nitride semiconductor in the upper layer,
The third semiconductor layer has a thickness of 500 nm or more depending on growth conditions in which foreign matter is present on the intervening layer and carbon is doped at a concentration of 1.0 × 10 ¹⁸ cm ⁻³ or less on the intervening layer. After the growth to a film thickness of less than 3000 nm, the buffer layer is grown on the upper layer of the third semiconductor layer ,
It said third semiconductor layer, the manufacturing method of the nitride semiconductor device, characterized in that the aluminum nitride layer and the gallium nitride layer is Ru der those stacked.

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