JP6225584B2 - Semiconductor device evaluation method, semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device evaluation method, a semiconductor device, and a manufacturing method thereof.

  Wide band gap semiconductors are very attractive as materials for semiconductor devices for high temperature environments, high power, or high frequency because they have high breakdown voltage, good electron transport properties, and good thermal conductivity. Typical wide band gap semiconductors include GaN, AlN, InN, BN, or a nitride semiconductor that is a mixed crystal of two or more of these. In a semiconductor device having an AlGaN / GaN heterojunction structure, two-dimensional electron gas (2DEG) is generated at the heterojunction interface due to piezoelectric polarization and spontaneous polarization. This two-dimensional electron gas has high electron mobility and carrier density. Therefore, a semiconductor device having such an AlGaN / GaN heterojunction structure has a high breakdown voltage, a low on-resistance, and a fast switching speed, and is very suitable for power switching applications.

  Further, in order to further increase the breakdown voltage of the semiconductor device, in the element having the AlGaN / GaN heterojunction structure, a stepped shape in which the Schottky electrode runs on the surface protective film made of an insulator formed on the surface of the semiconductor layer. And a field plate structure is known (see Non-Patent Document 1).

  Furthermore, the nitride semiconductor device described in Patent Document 1 is a Schottky barrier diode (SBD), and includes an anode electrode that is in Schottky contact with the semiconductor stacked portion, and a cathode electrode that is in ohmic contact with the semiconductor stacked portion. . The anode electrode is composed of a lower electrode layer and an upper electrode layer. The lower electrode layer of the anode electrode is in Schottky contact with the semiconductor laminate and a field plate layer (GaN-FP layer) made of gallium nitride (GaN) doped with a p-type dopant made of magnesium (Mg). (See Patent Document 1).

JP 2011-54845 A

N. Zhang, U.K. Mishra, “High Breakdown GaN HEMT with Overlapping Gate Structure”, IEEE Electron Device Letters, vol.21, no.9, 2000

  In the above-described high mobility transistor (HEMT) and SBD, which are semiconductor devices having an AlGaN / GaN heterojunction structure, improvement in the efficiency of actual machine operation is required. In order to improve the efficiency of the actual machine operation, first, the quality of the electron transit layer in which 2DEG is generated is reduced to reduce the on-resistance, and second, the current collapse is suppressed and conduction is performed during the actual machine operation. Two points are important to prevent the loss from increasing. However, according to the knowledge of the present inventor, if these two conditions are satisfied, there arises a problem that Schottky leak increases.

  Specifically, according to the nitride semiconductor device described in Patent Document 1, since the film thickness of the undoped GaN layer constituting the electron transit layer is about 500 nm, current collapse can be suppressed. However, there is a problem that Schottky leak increases due to the thickened electron transit layer.

  The present invention has been made in view of the above, and an object thereof is to obtain a semiconductor device in which on-resistance is reduced and current collapse is suppressed without increasing Schottky leakage. An object of the present invention is to provide a semiconductor device evaluation method, a semiconductor device, and a manufacturing method thereof.

  In order to solve the above-described problems and achieve the above object, a semiconductor device evaluation method according to the present invention includes a base, a first semiconductor layer made of a nitride-based semiconductor formed on the base, and the first semiconductor. A semiconductor stacked body including a second semiconductor layer formed of a nitride-based semiconductor having a wider band gap than the first semiconductor layer, and a semiconductor stacked body selectively provided on at least a part of the semiconductor stacked body, An insulating film having a step shape having one step, a first electrode having a step shape having at least two steps on the at least one step of the insulating film, and at least constituting a semiconductor stacked body In a method for evaluating a semiconductor device comprising: a second electrode provided apart from a first electrode on a part of a layer; a first step among steps formed on an insulating film in the first electrode Directly on the step of Depending on whether the pinch-off voltage is a predetermined voltage or less in, and evaluating the quality of the semiconductor device.

  The semiconductor device evaluation method according to the present invention is characterized in that, in the above invention, the predetermined voltage is 25 (V).

  In the semiconductor device evaluation method according to the present invention, in the above invention, the semiconductor stacked body further includes a third semiconductor layer, and the third semiconductor layer is formed of a nitride semiconductor having a narrower band gap than the second semiconductor layer. In addition, the semiconductor device is selectively provided on the second semiconductor layer.

  A semiconductor device according to the present invention includes a base, a first semiconductor layer made of a nitride-based semiconductor formed on the base, and a nitride formed on the first semiconductor layer and having a wider band gap than the first semiconductor layer. A semiconductor stacked body including a second semiconductor layer made of a base semiconductor; an insulating film that is selectively provided on at least a part of the semiconductor stacked body and has a step shape having at least one step; and at least the insulating film A first electrode that has a stepped shape and has at least two steps on the first step, and a first electrode that is spaced apart from the first electrode on at least a part of the layers constituting the semiconductor stacked body. A semiconductor device including two electrodes is characterized in that a pinch-off voltage immediately below a step portion of the first step among steps formed on the insulating film in the first electrode is not more than a predetermined voltage.

  The semiconductor device according to the present invention is characterized in that, in the above invention, the predetermined voltage is 25 (V).

  In the semiconductor device according to the present invention, in the above invention, the semiconductor stacked body further includes a third semiconductor layer, and the third semiconductor layer is formed of a nitride-based semiconductor having a narrower band gap than the second semiconductor layer. It is characterized by being selectively provided on two semiconductor layers. In this configuration, the semiconductor device according to the present invention is characterized in that the first electrode is in contact with at least part of the upper surface of the third semiconductor layer. In this configuration, the semiconductor device according to the present invention is characterized in that the third semiconductor layer and the second electrode are provided apart from each other.

  The semiconductor device according to the present invention is characterized in that, in the above invention, the first electrode is in Schottky contact with the second semiconductor layer.

  The semiconductor device according to the present invention is characterized in that, in the above invention, the second electrode is in ohmic contact with the second semiconductor layer.

  A method of manufacturing a semiconductor device according to the present invention includes a step of growing a first semiconductor layer made of a nitride-based semiconductor on a substrate, and a nitride-based having a wider band gap than the first semiconductor layer on the first semiconductor layer. Growing a second semiconductor layer made of a semiconductor, forming a semiconductor stacked body including the first semiconductor layer and the second semiconductor layer on the substrate, and at least one step on the semiconductor stacked body And forming an electrode having a step shape on at least one step on the insulating film, and forming an insulating film in the electrode. The pinch-off voltage immediately below the step portion of the first step among steps stepped on is set to be equal to or lower than a predetermined voltage.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the predetermined voltage is 25 (V).

  The method of manufacturing a semiconductor device according to the present invention includes a step of growing a third semiconductor layer made of a nitride-based semiconductor having a narrower band gap than the second semiconductor layer on the second semiconductor layer in the above invention, And a step of etching away a part of the three semiconductor layers.

  According to the semiconductor device evaluation method, the semiconductor device, and the manufacturing method thereof according to the present invention, it is possible to obtain a semiconductor device in which on-resistance is reduced and current collapse is suppressed without increasing Schottky leakage. Is possible.

FIG. 1 is a configuration diagram showing a cross section of a Schottky barrier diode for explaining a conventional problem. FIG. 2 is a graph showing the dependence of the Schottky leakage current on the pinch-off voltage immediately below the field plate layer according to the present invention. FIG. 3 is a sectional view showing a Schottky barrier diode having a field plate layer according to the first embodiment of the present invention. FIG. 4 is a graph showing the voltage dependence characteristics of capacitance when the GaN-FP layer is present and when it is not present in the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a sectional view showing a Schottky barrier diode according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view showing a HEMT transistor having a field plate layer according to the third embodiment of the present invention. FIG. 7 is a sectional view showing a HEMT transistor according to the fourth embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to the following embodiments. In the drawings, the same or corresponding elements are denoted by the same reference numerals as appropriate, and repeated descriptions are omitted as appropriate. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships between elements may differ from actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included. First, in describing embodiments of the present invention, in order to facilitate the understanding of the present invention, an intensive study conducted by the present inventor to solve the above-described problems will be described.

  That is, the inventor of the present invention has improved the quality of an electron transit layer in which 2DEG is generated in a semiconductor device by reducing the on-resistance and suppressing the current collapse to suppress an increase in conduction loss during actual operation. A method for improving the operation efficiency while preventing an increase in Schottky leak was examined.

First, in the device characteristics of a conventional silicon (Si) -based semiconductor device, the ratio (If / Ir) of the forward current If to the reverse current Ir is about 10 ⁶ . For this reason, in order to obtain device characteristics equal to or higher than those of the conventional Si-based semiconductor device, it is desirable that the following equation (1) is satisfied in the semiconductor device.
If / Ir> 10 ⁶ (1)

  However, it is difficult to achieve both the improvement of the efficiency of the actual machine operation by reducing the on-resistance and suppressing the current collapse, and the equation (1), and there is a so-called trade-off relationship. According to the study of the present inventor, these difficulties in compatibility are caused by the following four problems.

  That is, first, a means for increasing the 2DEG concentration can be considered as a means for reducing the ON resistance and suppressing the current collapse. However, when the 2DEG concentration is increased, Schottky leak increases, and there is a trade-off between improving the quality of the electron transit layer and reducing the Schottky leak. Second, as a countermeasure against current collapse, it is effective to increase the thickness of an electron transit layer made of, for example, a u-GaN layer. However, when the electron transit layer is thickened, Schottky leak increases. Third, electric field relaxation is effective as a countermeasure against further current collapse. A field plate (FP) structure or a step field plate (SFP) structure has been adopted for this electric field relaxation, and its usefulness has been confirmed by the present inventors. It will increase. Fourth, in the case where a conventionally known FP structure composed of a p-GaN layer as described in Patent Document 1 is adopted, there is a problem in that the etching damage during the manufacture of the semiconductor device and the cost increase due to the increase in the process are problems. become.

  FIG. 1 is a schematic cross-sectional view of a Schottky barrier diode as a subject for studying the above-described problems in the present invention. As shown in FIG. 1, the semiconductor device 500 includes a substrate 21, a buffer layer 22, a C-GaN layer 23, an electron transit layer 24, an electron supply layer 25, a passivation film 26, an anode electrode 27, and a cathode electrode 28. .

That is, the electron transit layer 24 is provided on the substrate 21 via the buffer layer 22 and the C-GaN layer 23. An electron supply layer 25 is provided on the electron transit layer 24. Further, a passivation film 26, an anode electrode 27, and a cathode electrode 28 are selectively provided on the surface of the electron supply layer 25. Here, a 2DEG layer is generated at the interface between the electron transit layer 24 and the electron supply layer 25. The passivation film 26 is made of, for example, silicon oxide (SiO ₂ ), but may be made of silicon nitride (SiN _x ). The passivation film 26 as an insulating film has a step shape having at least one step, and mainly protects the surface of the electron supply layer 25 where the anode electrode 27 and the cathode electrode 28 are not formed. The anode electrode 27 is in Schottky contact with the electron supply layer 25 and climbs over at least one step on the passivation film 26 to form at least two steps. The cathode electrode 28 is in ohmic contact with the electron supply layer 25.

  The present inventor conducted various experiments and studies on the semiconductor device 500 described above. As a result, it has been found that Schottky leak increases when the field plate structure in the anode electrode 27 has two or more stages as in the semiconductor device 500. Therefore, as a result of further examination and experiment by the present inventor, the inventors have paid attention to the relationship between the Schottky leak and the pinch-off voltage directly under the field plate structure, and have found a correlation between them.

  FIG. 2 is a graph showing the pinch-off voltage dependence of the Schottky leak current directly under the FP structure, derived by various experiments by the present inventor. 2 that the Schottky leakage current in the semiconductor device has a strong interphase relationship with the pinch-off voltage immediately below the FP structure. And when this inventor examined about the relationship between a pinch-off voltage and a Schottky leak current, it came to discover the following causes.

  That is, in the semiconductor device 500 configured as described above, the Schottky leak current flowing from the cathode electrode 28 to the anode electrode 27 passes through various paths. These routes are indicated by arrows A, B, C, and D in FIG. An arrow A indicates a Schottky leak current that flows from the cathode electrode 28 toward the anode electrode 27 through the interface between the electron transit layer 24 and the electron supply layer 25. An arrow B indicates a Schottky leak current that flows from the cathode electrode 28 toward the bent portion of the first step of the anode electrode 27 through the interface between the electron transit layer 24 and the electron supply layer 25. An arrow C passes from the cathode electrode 28 through the interface between the electron transit layer 24 and the electron supply layer 25 through the electron supply layer 25 immediately below the bent portion of the second step of the anode electrode 27, A Schottky leak current that flows toward the bent portion of the first step of the anode electrode 27 through the interface with the passivation film 26 is shown. An arrow D passes through the electron supply layer 25 immediately below the end of the anode electrode 27 on the passivation film 26 from the cathode electrode 28 through the interface between the electron transit layer 24 and the electron supply layer 25, and then the electron supply layer 25 and the passivation. A Schottky leak current that flows toward the bent portion of the first step of the anode electrode 27 through the interface with the film 26 is shown. In FIG. 1, Vp1, Vp2, and Vp3 indicate potential differences in the film thickness direction between the anode electrode 27 and the interface between the electron transit layer 24 and the electron supply layer in each region. These potential differences Vp1, Vp2, and Vp3 induce a Schottky current. The inventor recalled that these Schottky leak currents are dominated by the arrow (B) in FIG. As a result, the inventor of the present invention has a first step portion (a potential difference Vp2 of the potential difference Vp2) of the anode electrode 27 having a stepped shape having two steps of the SFP structure on the passivation film 26 having the one step. It has been found that the pinch-off voltage immediately below (region) affects the Schottky leakage current.

  As described above, in order to reduce the Schottky leakage current, the inventor of the FP structure having at least two steps is provided immediately below the FP structure, specifically, on the insulating film having at least one step. It has been recalled that it is extremely effective to reduce the pinch-off voltage immediately below the first step portion of the electrode.

Next, the present inventor has studied to what extent it is desirable to reduce the pinch-off voltage. First, in FIG. 2, the equation (1) corresponds to the case where the Schottky leakage current is 1.0 × 10 ⁻⁸ A or less. In the drawings, the description of αE ± β means α × 10 ^{± β} .

That is, when the device characteristics of the semiconductor device satisfy the formula (1), the range of the Schottky leakage current corresponding to this range is 1.0 × 10 ⁻⁸ A or less. For this reason, the present inventor has found that the pinch-off voltage immediately below the first step portion of the FP structure is preferably not more than a predetermined voltage corresponding to the upper limit of this Schottky leakage current, specifically 25 V or less. In other words, a semiconductor device in which the pinch-off voltage immediately below the first step portion of the anode electrode 27 of the FP structure is a predetermined voltage or lower, specifically 25 V or lower, has a Schottky leakage current of 1.0 × 10 ^−8. (A) Since the following can be achieved, the device characteristic satisfies the formula (1). As a result, in the semiconductor device, it is possible to achieve both the improvement of the efficiency of the actual machine operation and the expression (1).

  Thus, the performance of the electron transit layer in the semiconductor device can be improved, the current density can be suppressed while the on-resistance is reduced by increasing the carrier density of 2DEG, and the Schottky leak can be reduced. Further, from the above examination, the present inventor has determined whether or not the Schottky leak current is suppressed in the semiconductor device by measuring the pinch-off voltage immediately below the first step portion of the FP structure by, for example, CV characteristics. I recalled that I could evaluate. The embodiment described below has been devised based on the above-mentioned diligent study.

(Embodiment 1)
Next, the semiconductor device according to the first embodiment of the present invention based on the above earnest study will be described. FIG. 3 is a schematic cross-sectional view of a Schottky barrier diode (SBD) as a semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 3, the semiconductor device 100 according to the first embodiment includes a substrate 11, a buffer layer 12, a GaN (C-GaN) layer 13 doped with carbon (C), an electron transit layer 14, and an electron supply layer. 15, a field plate layer 16, a passivation film 17, an anode electrode 18, and a cathode electrode 19.

  That is, the buffer layer 12 and the C-GaN layer 13 are provided on the substrate 11 as a base. An electron transit layer 14 and an electron supply layer 15 are sequentially stacked on the C-GaN layer 13. Further, a field plate layer 16, a passivation film 17, an anode electrode 18, and a cathode electrode 19 are selectively provided on the electron supply layer 15, respectively.

  Substrate 11 is made of a material capable of forming a group III nitride compound semiconductor on the main surface, such as silicon (Si), silicon carbide (SiC), sapphire, or zinc oxide (ZnO).

The buffer layer 12 has a function of reducing the difference in thermal expansion coefficient and lattice constant between the substrate 11 and the nitride-based semiconductor layer to be laminated on the buffer layer 12, and the group III nitride-based on the substrate 11. This is a layer for suitably forming a compound semiconductor layer. Here, the buffer layer 12 is configured, for example, by sequentially stacking a buffer layer 12a and a buffer layer 12b having different configurations for controlling warpage. The buffer layer 12a has a C-GaN layer made of GaN doped with carbon and having a thickness of 100 nm to 700 nm, which is thick enough not to produce a quantum size effect on an AlN layer having a thickness of 20 nm to 60 nm, for example. An AlN layer having a thickness of 20 nm to 60 nm that is thick enough not to cause a size effect is repeatedly stacked a plurality of times. Note that Al and Ga may be included in the C-GaN layer and the AlN layer, respectively, but when they are not included, an effect that warpage can be increased most is produced. The buffer layer 12b is thin to the extent that produces a quantum size effect in order not to cause an electric field shielding layer by unintended carrier (2DEG) generated by the piezoelectric polarization and spontaneous polarization in the structure, the film thickness is 1 nm to 10 nm Al _u It has a superlattice structure in which Ga _1-u N and Al _v Ga _1-v N (v <u) having a film thickness of 15 nm to 25 nm are repeatedly stacked. The C-GaN layer 13 is an electric field relaxation layer that relaxes the electric field in the semiconductor device 100.

The electron transit layer 14 as the first semiconductor layer is made of, for example, undoped GaN (u-GaN). In addition, the electron supply layer 15 as the second semiconductor layer is a group III nitride compound semiconductor having a wider band gap than the electron transit layer 14 and is Al _x Ga _y In _z N (0 ≦ x, y, z ≦ 1, x + y + z = 1). The Al composition ratio x of Al _x Ga _y In _z N is preferably 0.20 or more and 0.35 or less, more preferably 0.20 or more and 0.30 or less, and specifically, for example, 0.25. The thickness d _AlGaN of the electron supply layer 15 is preferably 15 nm or more and 30 nm or less, and more preferably 20 nm or more and 25 nm or less. Here, a 2DEG layer is generated at the interface between the electron transit layer 14 and the electron supply layer 15.

The electron supply layer 15 is not limited to a single layer of Al _x Ga _y In _z N, and may have a structure in which a plurality of types of group III nitride compound semiconductors having different band gaps are stacked. In this case, it is preferable that 2DEG is not generated in the electron supply layer 15. Specifically, for example, a structure in which a GaN layer and an AlN layer are sequentially repeated a plurality of times may be employed. The band gap of the electron supply layer 15 in this case is an average band gap, specifically, a band gap value weighted (integrated) by the layer thickness ratio of each semiconductor layer constituting the stacked structure.

  The field plate layer 16 as at least a part of the third semiconductor layer has a band gap narrower than that of the electron supply layer 15. The field plate layer 16 is made of, for example, GaN. The film thickness of the field plate layer 16 is preferably 10 nm or more and 200 nm or less, for example, 30 nm. The electron transit layer 14, the electron supply layer 15, and the field plate layer 16 constitute a semiconductor stacked body.

The passivation film 17 is made of, for example, SiO ₂ or SiN _x and has a stepped shape having at least one step while covering a part of the field plate layer 16. The passivation film 17 mainly protects the field plate layer 16, the cathode electrode 19, and the surface of the electron supply layer 15 where the anode electrode 18 and the cathode electrode 19 are not formed.

  The anode electrode 18 as the first electrode is in Schottky contact with the electron supply layer 15. That is, the anode electrode 18 has, for example, a Ni / Au laminated structure. As a result, the anode electrode 18 is in Schottky contact with the 2DEG layer generated in the electron transit layer 14 via the electron supply layer 15.

  Further, the anode electrode 18 is provided so as to ride on the side surface and part of the upper surface of the field plate layer 16 and extends toward the cathode electrode 19 side. The anode 18 is provided on the field plate layer 16 so as to run on the passivation film 17 so as to form at least two steps. That is, in the first embodiment, the anode electrode 18 is provided on the field plate layer 16 and the passivation film 17 so as to have at least three steps.

  The cathode electrode 19 as the second electrode is in ohmic contact with the electron supply layer 15. That is, the cathode electrode 19 has a laminated structure in which, for example, the lower electrode layer is a Ti layer and the upper electrode layer is an Al layer (hereinafter, Ti / Al). Thus, the cathode electrode 19 is in ohmic contact with the 2DEG layer generated in the electron transit layer 14 via the electron supply layer 15.

(Method for manufacturing semiconductor device)
The semiconductor device 100 configured as described above can be manufactured as follows. First, the buffer layer 12, the C-GaN layer 13, the electron transit layer 14, and the electron supply layer 15 are sequentially grown on the substrate 11 by using a crystal growth method such as MOCVD.

Next, a third semiconductor layer to be the field plate layer 16 is grown on the electron supply layer 15. Here, the growth of the third semiconductor layer can be specifically performed as follows. That is, for example, trimethylgallium (TMGa) and ammonia (NH ₃ ) are supplied at predetermined flow rates (for example, 58 μmol / min and 12 L / min, respectively) by metal organic chemical vapor deposition (MOCVD). The semiconductor layer is epitaxially grown by introducing the semiconductor layer. Thereafter, selective etching is performed to remove the third semiconductor layer other than the desired region, thereby forming the field plate layer 16 made of a part of the third semiconductor layer.

  Thereafter, the cathode electrode 19 is formed by, for example, an electron beam evaporation method and a lift-off method. Next, the passivation film 17 having at least one step is formed using, for example, a plasma enhanced chemical vapor deposition (PECVD) method, a photolithography technique, and etching. Next, an anode electrode 18 having an FP structure is formed so as to run on the field plate layer 16 and the passivation film 17 by an electron beam evaporation method and a lift-off method. The semiconductor device 100 according to the first embodiment is manufactured through the above steps.

(Semiconductor device evaluation method)
For the semiconductor device 100 manufactured as described above, for example, using a CV measuring device, the portion directly on the passivation film 17 of the anode electrode 18 (measurement position in FIG. 3) is directly below the first step portion. Measure the CV characteristics. As a result, the semiconductor device 100 is evaluated by measuring the pinch-off voltage. Then, only the semiconductor device 100 whose pinch-off voltage is a predetermined voltage or lower, specifically, 25 V or lower is extracted and adopted as a product. As a result, a semiconductor device in which both the improvement of the efficiency of the actual machine operation and the device characteristics that satisfy the expression (1) are established can be obtained.

  The reduction of the pinch-off voltage in the semiconductor device 100 described above can be realized by setting various parameters that affect this. Specific parameters include the film thickness of the electron supply layer 15 that affects the 2DEG concentration, the average Al composition, or the film thickness of the field plate layer 16 in consideration of depletion from the anode electrode 18 side. Similarly, in the depletion from the anode electrode 18 side, the film thickness of the passivation film 17 and the film thickness of the field plate layer 16 that affect the sharing of voltage are also parameters. In consideration of depletion occurring from the buffer layer 12 side, the film thickness and carrier concentration of the electron transit layer 14 that affect the depletion of carriers remaining in the electron transit layer 14 are parameters. Similarly, when depletion occurring from the buffer layer 12 side is taken into consideration, the distance between the channel and the equipotential surface of the buffer layer 12 that affects the depletion of the channel from the buffer layer 12 is a parameter.

An example of specific numerical values of these parameters will be given. That is, the film thickness d _SiO2 of the passivation film 17 in the pinch-off voltage V _P of the measuring position, the position of the first stage of the step portion of the step in particular which rides on the passivation film 17 in the anode electrode 18, 200 nm or more 10nm It is as follows. Further, the film thickness d _FP of the field plate layer 16 is not less than 10 nm and not more than 100 nm. The 2DEG concentration immediately below the portion where the field plate layer 16 is not provided is 7.0 × 10 ¹² cm ⁻² or more and 1.0 × 10 ¹³ cm ⁻² or less. Further, in the electron transit layer 14, the film thickness _du-GaN is 500 nm to 700 nm and the carrier concentration n _u-GaN is 1 × 10 ¹⁶ cm ⁻³ or less. The thickness d _AlGaN of the electron supply layer 15 is not less than 15 nm and not more than 30 nm. By configuring the semiconductor device 100 by setting these parameters, it is possible to obtain the semiconductor device 100 whose pinch-off voltage is a predetermined voltage or lower, specifically, 25 V or lower. The film thickness of the buffer layer 12 is, for example, about 4.6 μm, but since it does not affect the lowering of the pinch-off voltage, the film thickness of the buffer layer 12 can be various.

  In addition, the structure of the field plate layer 16 affects the lowering of the pinch-off voltage. FIG. 4 is a graph showing the voltage dependence characteristics of the capacitance Cp (F) of the semiconductor device when the field plate layer 16 made of, for example, GaN is provided in the semiconductor device 100 and when it is not provided. . In the semiconductor device 100 to be compared, the conditions other than the presence or absence of the field plate layer 16 are the same. Here, the thickness of the passivation film is set to 100 nm at the position of the first stage where the anode electrode 18 rides on the passivation film 17. Yes.

  From FIG. 4, when the field plate layer 16 is not provided, the pinch-off voltage directly below the step portion of the first stage of the anode electrode 18 on the passivation film 17 may exceed 200 V, whereas In the case where the layer 16 is provided, it can be seen that the pinch-off voltage immediately below the first step portion of the anode electrode 18 on the passivation film 17 is about 19.6V. That is, when the semiconductor device 100 has the field plate layer 16, it can be seen that the Schottky leakage current falls within 25 V that is the predetermined value of the pinch-off voltage described above.

（ｅ：素電荷量、ε₀：真空の比誘電率、ε_SiO2：ＳｉＯ₂の比誘電率、ε_GaN：ＧａＮの比誘電率、ｄ_AlGaN：電子供給層の膜厚、ｄ_FP：フィールドプレート層の膜厚、ｄ_SiO2：パッシベーション膜の膜厚、ｄ_u-GaN：電子走行層の膜厚、ｎ_u-GaN：電子走行層のキャリア濃度、Ｖ_P：ピンチオフ電圧） In the semiconductor device 100, the 2DEG concentration Ns immediately below the field plate layer 16 can be specifically calculated from the following relational expression.

(E: elementary charge amount, ε ₀ : relative permittivity of vacuum, ε _SiO2 : relative permittivity of SiO ₂ , ε _GaN : relative permittivity of GaN, d _AlGaN : film thickness of electron supply layer, d _FP : field plate Layer thickness, d _SiO2 : passivation film thickness, d _u-GaN : electron transit layer thickness, n _u-GaN : electron transit layer carrier concentration, V _P : pinch-off voltage)

  According to the first embodiment of the present invention described above, by adopting a configuration in which the pinch-off voltage is likely to be lowered, an increase in leak accompanying an increase in 2DEG concentration, an increase in leak accompanying an increase in the thickness of the electron transit layer, Further, it is possible to improve the trade-off between each factor of the increase in leak when the SFP structure is employed and the Schottky leak. As a result, it is possible to obtain a semiconductor device that satisfies the expression (1) while improving the efficiency of actual machine operation.

(Embodiment 2)
Next, a Schottky barrier diode as a semiconductor device according to the second embodiment of the present invention will be described. FIG. 5 is a schematic cross-sectional view of a Schottky barrier diode according to the second embodiment.

As shown in FIG. 5, the semiconductor device 200 according to the second embodiment includes a substrate 11, a buffer layer 12 including a buffer layer 12a and a buffer layer 12b, a C-GaN layer 13, an electron transit layer 14, an electron supply layer 15, and a passivation. A membrane 17, an anode electrode 18, and a cathode electrode 19 are provided. That is, in contrast to the first embodiment, the field plate layer 16 is not provided on the surface of the electron supply layer 15, and the semiconductor stacked body includes the electron transit layer 14 and the electron supply layer 15. Further, the pinch-off voltage V _P immediately below the first step portion of the anode electrode 18 on the passivation film 17 is configured to be a predetermined voltage or less, specifically 25 V or less. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

Here, as an example of a parameter for lowering the pinch-off voltage in the semiconductor device 200 according to the second embodiment, one step of the anode electrode 18 on the step-shaped passivation film 17 for measuring the pinch-off voltage V _P is given. At the eye position (measurement position in FIG. 5), the thickness d _SiO2 of the passivation film 17 is 10 nm or more and 50 nm or less, and the 2DEG concentration immediately below this position is 7.0 × 10 ¹² cm ⁻² or more and 1.0 ×. 10 ¹³ cm ^-2 or less. It should be noted that the configuration of the semiconductor device 100 showing the characteristics without the GaN-FP layer in FIG. 4 is not included in the configuration of the semiconductor device 200. Further, in the electron transit layer 14, the film thickness _du-GaN is 500 nm to 700 nm and the carrier concentration n _u-GaN is 1 × 10 ¹⁶ cm ⁻³ or less. The thickness d _AlGaN of the electron supply layer 15 is not less than 15 nm and not more than 30 nm. By configuring the semiconductor device 200 by setting these parameters, it is possible to obtain the semiconductor device 200 having a pinch-off voltage of a predetermined voltage or lower, specifically 25V or lower. Since the buffer layer 12 does not affect the lowering of the pinch-off voltage, the film thickness can be various.

  According to the semiconductor device according to the second embodiment, the pinch-off voltage of the portion immediately below the first step in the two step portions of the anode electrode 18 on the passivation film 17 is a predetermined voltage or lower, specifically 25 V or lower. As a result, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
Next, a HEMT type transistor as a semiconductor device according to the third embodiment of the present invention will be described. FIG. 6 is a schematic cross-sectional view of a HEMT transistor according to the third embodiment.

  As shown in FIG. 6, the semiconductor device 300 according to the third embodiment includes a substrate 11, a buffer layer 12 in which buffer layers 12a and 12b having different structures are sequentially stacked, a C-GaN layer 13, an electron transit layer 14, and an electron. A supply layer 15, a field plate layer 16, a passivation film 31, a gate electrode 32, a drain electrode 33, and a source electrode 34 are provided.

  The drain electrode 33 and the source electrode 34 are formed on the electron supply layer 15 and have, for example, a laminated structure of Ti / Al. Accordingly, the drain electrode 33 as the second electrode and the source electrode 34 as the third electrode are in ohmic contact with the 2DEG layer generated in the electron transit layer 14 via the electron supply layer 15. The gate electrode 32 as the first electrode is disposed between the drain electrode 33 and the source electrode 34, and is formed on the electron supply layer 15, the field plate layer 16, and the passivation film 31. The gate electrode 32 has a laminated structure of Ni / Au, for example. As a result, the gate electrode 32 is in Schottky contact with the 2DEG layer generated in the electron transit layer 14 via the electron supply layer 15. Further, the field plate layer 16 is provided at least apart from the drain electrode 33. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  According to the third embodiment, by adopting a configuration in which the pinch-off voltage is likely to be lowered, an increase in leak accompanying an increase in 2DEG concentration, an increase in leak accompanying an increase in the thickness of the electron transit layer, and an SFP structure are adopted. In this case, the tradeoff between each factor of the increase in leak and the Schottky leak can be improved. As a result, it is possible to obtain a semiconductor device that satisfies the expression (1) while improving the efficiency of actual machine operation.

(Embodiment 4)
Next, a HEMT type transistor as a semiconductor device according to the fourth embodiment of the present invention will be described. FIG. 7 is a schematic cross-sectional view of a HEMT type transistor according to the fourth embodiment.

  As shown in FIG. 7, the semiconductor device 400 according to the fourth embodiment includes a substrate 11, a buffer layer 12 in which buffer layers 12a and 12b having different structures are sequentially stacked, a C-GaN layer 13, an electron transit layer 14, and an electron. A supply layer 15, a passivation film 31, a gate electrode 32, a drain electrode 33, and a source electrode 34 are provided. That is, the semiconductor device 400 has a configuration in which the field plate layer 16 is not provided in the semiconductor device 300 according to the third embodiment as in the second embodiment. Since other configurations are the same as those in the second and third embodiments, the description thereof is omitted.

  According to the fourth embodiment, the same effect as in the third embodiment can be obtained by having the same configuration as in the third embodiment.

  Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible. For example, the numerical values given in the above-described embodiment are merely examples, and different numerical values may be used as necessary.

  The parameters for setting the pinch-off voltage to 25 V or less as mentioned in the above embodiment are not necessarily limited to the parameters described above, and various parameters can be adopted.

Further, in the above-described embodiment, the electron supply layer 15 is made of Al _x Ga _y In _z N (0 ≦ x, y, z ≦ 1, x + y + z = 1), and the electron transit layer 14 and the field plate layer 16 are formed. Is made of GaN. However, the constituent materials of these layers are not limited to those described above. That is, the electron supply layer 15 may be made of a group III nitride compound semiconductor having a wider band gap than the electron transit layer 14. The field plate layer 16 only needs to be made of a group III nitride compound semiconductor having a narrower band gap than the electron supply layer 15. Here, III nitride compound semiconductor has the formula _{Al x In y Ga 1-x} -y As u P v N 1-u-v ( however, 0 ≦ x ≦ 1,0 ≦ y ≦ 1, x + y ≦ 1, 0 ≦ u <1, 0 ≦ v <1, 0 ≦ u + v <1).

  The lower electrode layers of the anode electrode 18 of the diode and the gate electrode 32 of the transistor are electrodes that are in Schottky contact with the electron supply layer 15. Therefore, in addition to the above-described titanium (Ti), for example, nickel (Ni), platinum (Pt), palladium (Pd), tungsten (W), gold (Au), silver (Ag), copper (Cu), tantalum ( Ta), a metal film containing at least one of aluminum (Al), or a metal film made of an alloy containing at least one of Ti, Ni, Pt, Pd, W, Au, Ag, Cu, Ta, and Al Of these, various materials may be used as long as they satisfy the above conditions, such as a metal film including at least one of them.

  The upper electrode layer of the anode electrode 18 of the diode and the gate electrode 32 of the transistor is made of a metal having a work function smaller than that of the lower electrode layer, and various materials may be used as long as the metal material satisfies this condition.

  Further, the cathode electrode 19 of the diode and the source electrode 34 and the drain electrode 33 of the transistor are electrodes that are in ohmic contact with the electron supply layer 15 or in contact with a sufficiently small contact resistance. However, the present invention is not limited to this. For example, a metal film containing at least one of Ti, Al, silicon (Si), lead (Pb), chromium (Cr), indium (In), and Ta, Ti, At least one of a metal film made of an alloy containing at least one of Al, Si, Pb, Cr, In, and Ta, or a metal film made of a silicide alloy containing at least one of Ti, Al, Si, and Ta. Any metal material that satisfies the above conditions, such as a metal film including one, may be used.

  In the above-described embodiment, SBD and HEMT are given as examples of the semiconductor device according to the present invention, but the present invention is not limited to this. In other words, the present invention can be applied to various semiconductor devices such as MESFET (Metal Semiconductor FET), MOSFET (Metal Oxide Semiconductor FET), and MISFET (Metal Insulator Semiconductor FET). When the present invention is applied to these FETs, an insulating film such as an oxide film can be provided between the gate electrode 32 and the field plate layer 16.

  In the above-described embodiment, the electrode is formed on the surface of the electron supply layer 15, but is not necessarily limited thereto, and the electron transit layer 14, the electron supply layer 15, and the field plate layer 16 are not necessarily limited thereto. It is possible to provide an electrode on at least one layer of the semiconductor stacked body including other layers as necessary. That is, an electrode may be provided on another layer constituting the semiconductor stacked body. Specifically, an anode electrode 18, a cathode electrode 19, a gate electrode 32, a drain are formed on the surface of the electron supply layer 15 via a nitride semiconductor layer such as an insulating layer, a field plate layer 16, or a laminated film thereof. It is also possible to provide the electrode 33 or the source electrode 34. Further, a part of the electrode formation region of the electron supply layer 15 is removed by etching until reaching the electron transit layer 14 to form a recessed portion, and the surface of the recessed portion or the surface of the recessed portion through a predetermined film, It is also possible to provide the anode electrode 18, the cathode electrode 19, the gate electrode 32, the drain electrode 33, or the source electrode 34.

11, 21 Substrate 12, 12a, 12b, 22 Buffer layer 13, 23 C-GaN layer 14, 24 Electron traveling layer 15, 25 Electron supply layer 16 Field plate layer 17, 26, 31 Passivation film 18, 27 Anode electrode 19, 28 Cathode electrode 32 Gate electrode 33 Drain electrode 34 Source electrode 100, 200, 300, 400, 500 Semiconductor device

Claims (12)

A substrate;
A first semiconductor layer made of a nitride semiconductor formed on the substrate, and a second semiconductor layer made of a nitride semiconductor formed on the first semiconductor layer and having a wider band gap than the first semiconductor layer. A semiconductor laminate including:
An insulating film which is selectively provided on at least a part of the semiconductor stacked body and has a stepped shape having at least one step;
The rides over the step of at least the first stage of the insulating film to forming a stepped shape having a step of at least two stages, a first electrode contacting the second semiconductor layer and the Schottky,
A second electrode provided apart from the first electrode on at least a part of the layers constituting the semiconductor laminate;
In a method for evaluating a semiconductor device comprising:
The quality of the semiconductor device is evaluated based on whether or not the pinch-off voltage immediately below the step portion of the first step among the steps on the insulating film in the first electrode is equal to or lower than a predetermined voltage. A method for evaluating a semiconductor device.   The semiconductor device evaluation method according to claim 1, wherein the predetermined voltage is 25 (V).   The semiconductor stacked body further includes a third semiconductor layer, and the third semiconductor layer is made of a nitride-based semiconductor having a narrower band gap than the second semiconductor layer, and is selectively formed on the second semiconductor layer. The semiconductor device evaluation method according to claim 1, wherein the semiconductor device evaluation method is provided. A substrate;
A first semiconductor layer made of a nitride semiconductor formed on the substrate, and a second semiconductor layer made of a nitride semiconductor formed on the first semiconductor layer and having a wider band gap than the first semiconductor layer. A semiconductor laminate including:
An insulating film which is selectively provided on at least a part of the semiconductor stacked body and has a stepped shape having at least one step;
The rides over the step of at least the first stage of the insulating film to forming a stepped shape having a step of at least two stages, a first electrode contacting the second semiconductor layer and the Schottky,
A second electrode provided apart from the first electrode on at least a part of the layers constituting the semiconductor laminate;
In a semiconductor device comprising:
The pinch-off voltage immediately below the step portion of the first step among the steps on the insulating film in the first electrode is equal to or lower than a predetermined voltage corresponding to the upper limit of the Schottky leak current. .   The semiconductor device according to claim 4, wherein the predetermined voltage is 25 (V).   The semiconductor stacked body further includes a third semiconductor layer, and the third semiconductor layer is made of a nitride-based semiconductor having a narrower band gap than the second semiconductor layer, and is selectively formed on the second semiconductor layer. 6. The semiconductor device according to claim 4, wherein the semiconductor device is provided.   The semiconductor device according to claim 6, wherein the first electrode is in contact with at least a part of an upper surface of the third semiconductor layer.   The semiconductor device according to claim 6, wherein the third semiconductor layer and the second electrode are provided apart from each other. Wherein the second electrode, the semiconductor device according to any one of claims 4-8, characterized in that contacts the second semiconductor layer and the ohmic. Growing a first semiconductor layer made of a nitride-based semiconductor on a substrate; and growing a second semiconductor layer made of a nitride-based semiconductor having a wider band gap than the first semiconductor layer on the first semiconductor layer. Forming a semiconductor laminate including the first semiconductor layer and the second semiconductor layer on a substrate; and
Selectively forming an insulating film having at least one step on the semiconductor laminate;
The rides on the step of the at least one stage of the insulating film to forming a stepped shape having a step of at least two stages, and forming the second semiconductor layer and the Schottky contact electrode,
Including
A semiconductor device characterized in that a pinch-off voltage immediately below a step portion of the first step among steps stepped on the insulating film in the electrode is equal to or lower than a predetermined voltage corresponding to an upper limit of a Schottky leak current. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 10 , wherein the predetermined voltage is 25 (V). Growing a third semiconductor layer made of a nitride-based semiconductor having a narrower band gap than the second semiconductor layer on the second semiconductor layer; etching away a part of the third semiconductor layer; the method of manufacturing a semiconductor device according to claim 10 or 11, further comprising a.

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