JP4592938B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4592938B2
JP4592938B2 JP2000373612A JP2000373612A JP4592938B2 JP 4592938 B2 JP4592938 B2 JP 4592938B2 JP 2000373612 A JP2000373612 A JP 2000373612A JP 2000373612 A JP2000373612 A JP 2000373612A JP 4592938 B2 JP4592938 B2 JP 4592938B2
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layer
formed
cap layer
electron supply
semiconductor device
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JP2001230407A (en
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薫 井上
宏幸 正戸
勝則 西井
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パナソニック株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and in particular, generally relates to In.XAlYGa1-XYThe present invention relates to a field effect transistor using a heterostructure of a gallium nitride semiconductor represented by N (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1).
[0002]
[Prior art]
Gallium nitride semiconductors such as GaN, AlGaN, InGaN, and InAlGaN have high dielectric breakdown field strength, high thermal conductivity, and high electron saturation speed, and are promising as high-frequency power device materials. In particular, in a semiconductor device having an AlGaN / GaN heterojunction structure, electrons accumulate at a high concentration near the heterojunction interface between AlGaN and GaN, and so-called two-dimensional electron gas is formed. Since this two-dimensional electron gas exists spatially separated from donor impurities added to AlGaN, it exhibits high electron mobility. When a field effect transistor is fabricated using this heterostructure, the source resistance component is reduced. Can be reduced. Further, since the distance d from the gate electrode to the two-dimensional electron gas is usually as short as several tens of nm, even if the gate length Lg is as short as about 100 nm, the ratio of the gate length Lg to the distance d (that is, the aspect ratio) Lg / d can be increased to about 5 to 10. Therefore, a semiconductor device using a heterostructure has an excellent feature that a short-channel effect is small and a field-effect transistor having good saturation characteristics can be easily manufactured. Furthermore, the two-dimensional electron in the AlGaN / GaN heterostructure is 1 × 10FiveIn the high electric field region of about V / cm, it has an electron velocity more than twice that of the AlGaAs / InGaAs system currently popular as a high frequency transistor, and is expected to be applied to a high frequency power device.
[0003]
FIG. 9 shows a conventional semiconductor device 900. The semiconductor device 900 has a structure in which a buffer layer 902 containing GaN, a channel layer 903 made of GaN or InGaN, and an electron supply layer 904 containing AlGaN are sequentially stacked on a sapphire substrate or SiC substrate 901. . A source electrode 906, a gate electrode 907, and a drain electrode 908 are provided over the electron supply layer 904.
[0004]
This AlGaN / GaN heterostructure is usually formed by crystal growth on a [0001] plane (c-plane) sapphire substrate or SiC substrate 901 using metal organic vapor phase epitaxy or molecular beam epitaxy. . When the buffer layer 902 containing GaN is formed over the sapphire substrate or the SiC substrate 901, the lattice constants of the substrate 901 and the buffer layer 902 are greatly different, so that the buffer layer 902 needs to be formed thick. This is because by forming the buffer layer 902 thick, distortion based on lattice mismatch between the buffer layer 902 and the substrate 901 is sufficiently relieved. When an electron supply layer 904 containing AlGaN doped with an n-type impurity such as Si is formed on the thick buffer layer 902 with a thickness of several tens of nanometers, electrons are generated at the heterointerface between AlGaN and GaN due to the effect of selective doping. A two-dimensional electron gas (that is, a channel layer 903) is formed on the buffer layer 902 having a higher affinity. In the heterostructure formed by the MOCVD (metal organic chemical vapor deposition) method, the crystal surface is usually a group III atom Ga plane, and the concentration of the two-dimensional electron gas is (included in the electron supply layer 904). The effect of piezoelectric polarization in the c-axis direction due to the tensile stress applied to AlGaN is added to the difference in spontaneous polarization between AlGaN and GaN (included in the buffer layer 902), which is predicted from the concentration of the n-type impurity added to the electron supply layer 904. Accumulate electrons at a higher concentration than the expected value. When the Al composition of AlGaN in the electron supply layer 904 is 0.2 to 0.3, the electron concentration in the channel layer 903 is 1 × 1013/ Cm2This is about three times that of GaAs-based devices. Since such a high-concentration two-dimensional electron gas is accumulated, the semiconductor device 900 used as a GaN-based heterostructure field effect transistor (FET) is very promising as a power device.
[0005]
[Problems to be solved by the invention]
However, the conventional semiconductor device 900 has several problems. The problems are that (1) the crystal growth technique and the process related to the crystal growth technique are not perfect, so that a high-quality crystal is not obtained, and (2) the etching process when the etching process is performed. The device characteristics deteriorate due to the damage introduced by the above, and the predicted power characteristics are not sufficiently realized.
[0006]
One of the problems related to crystal growth is that non-doped GaN contained in the buffer layer 902 is usually n-type and has a carrier concentration of 1016/ CmThreeThis is due to the high degree or higher. This is presumably because nitrogen (N), which is a constituent element, escapes during crystal growth, and nitrogen vacancies are easily formed. Such residual carriers increase the leakage current component through the GaN buffer layer 902 of the device, leading to deterioration of device characteristics such as poor pinch-off characteristics when operated at high temperatures. In addition, when a plurality of GaN-based heterostructure FETs are formed on the same substrate, the FETs interfere with each other, and there is a problem related to element isolation that prevents normal operation. Further, when the gate electrode 907 is provided above the GaN buffer layer 902, problems such as an increase in gate leakage current and a decrease in device breakdown voltage occur.
[0007]
A problem in the etching process technique is that damage is formed on the surface of GaN (included in the buffer layer 902) or AlGaN (included in the electron supply layer 904). Since GaN or AlGaN is difficult to remove or scrape using wet etching, etching is usually performed using dry etching. However, the buffer layer 902 or the electron supply layer is damaged due to damage to the surface formed during dry etching. Leakage current easily flows on the surface of 904. In particular, it is believed that the lack of nitrogen on the surface increases the conductivity of the surface of the buffer layer 902 exposed by etching and increases the leakage current.
[0008]
The present invention has been made in view of the problems of the above-described GaN-based heterostructure FET, and the first object thereof is a residual carrier accompanying defects or scratches that are unintentionally introduced into the GaN layer or the surface of the GaN layer. The present invention provides a semiconductor device (GaN-based heterostructure FET) in which the surface leakage current due to the above is significantly reduced. The second object of the present invention is to provide a semiconductor device (GaN heterostructure FET) capable of improving the withstand voltage (breakdown voltage) of the element while reducing the surface leakage current.
[0009]
[Means for Solving the Problems]
  A semiconductor device of the present invention includes a substrate and GaN formed on the substrate.Consist ofA buffer layer, the surface of the buffer layer being a c-plane of Ga atoms, and GaN or InGaN formed on the buffer layerConsist ofA channel layer, the surface of the channel layer being a c-plane of Ga or In atoms, and AlGaN formed on the channel layerConsist ofAn electron supply layer, wherein the surface of the electron supply layer is a c-plane of Al or Ga atoms, a source electrode and a drain electrode formed on the electron supply layer, and the source electrode GaN formed between the drain electrodeConsist ofA cap layer, wherein the surface of the cap layer is a c-plane of Ga or In atoms, at least part of the cap layer is in contact with the electron supply layer, and at least part of the cap layer is in contact with the cap layer And a gate device formed as described aboveThe gate electrode is formed so as to be in contact with the electron supply layer.The
The gate electrode may be formed on the cap layer.
The composition of the cap layer is substantially lattice-matched with the buffer layer in the c-plane, and the absolute value of the polarization generated in the cap layer is the absolute value of the polarization generated in the electron supply layer. The electron supply layer may be formed to be smaller than that.
The gate electrode may be located closer to the source electrode than the drain electrode.
The surface area of the gate electrode may be larger than the surface area of the cap layer.
[0010]
  The semiconductor device of the present invention includes a substrate and a buffer layer made of GaN formed on the substrate, wherein the buffer layer has a c-plane of Ga atoms, and a buffer layer on the buffer layer. A channel layer made of GaN or InGaN formed on the channel layer, the surface of the channel layer being a c-plane of Ga or In atoms, and an electron supply layer made of AlGaN formed on the channel layer The surface of the electron supply layer is a c-plane of Al or Ga atoms, the source electrode and the drain electrode formed on the electron supply layer, the source electrode and the drain electrode A cap layer made of InGaAlN formed between and a c-plane of Ga or In atoms, and at least a part of the cap layer is in contact with the electron supply layer A semiconductor device comprising a cap layer and a gate electrode formed so that at least a part thereof is in contact with the cap layer, the composition of the cap layer being substantially lattice constant with the buffer layer in the c-plane. The electron supply layer is formed so as to be matched and the absolute value of the magnitude of the polarization generated in the cap layer is smaller than the absolute value of the polarization generated in the electron supply layer.
  The gate electrode may be formed so as to be in contact with the electron supply layer.
  The gate electrode may be formed on the cap layer.
  The gate electrode may be located closer to the source electrode than the drain electrode.
  The surface area of the gate electrode may be larger than the surface area of the cap layer.
[0011]
  The semiconductor device of the present invention includes a substrate and a buffer layer made of GaN formed on the substrate, wherein the buffer layer has a c-plane of Ga atoms, and a buffer layer on the buffer layer. A channel layer made of GaN or InGaN formed on the channel layer, the surface of the channel layer being a c-plane of Ga or In atoms, and an electron supply layer made of AlGaN formed on the channel layer The surface of the electron supply layer is a c-plane of Al or Ga atoms, the source electrode and the drain electrode formed on the electron supply layer, the source electrode and the drain electrode A cap layer made of GaN formed between and a surface of the cap layer is a c-plane of Ga or In atoms, and at least a part of the cap layer is in contact with the electron supply layer. And up layer, a semiconductor device and a gate electrode formed so as to at least partly in contact with the cap layer, n-type impurity is added to partially or entirely on the cap layer.
  The gate electrode may be formed so as to be in contact with the electron supply layer.
  The gate electrode may be formed on the cap layer.
  The gate electrode may be located closer to the source electrode than the drain electrode.
  The surface area of the gate electrode may be larger than the surface area of the cap layer.
[0028]
With the above configuration, by increasing the barrier height of the Schottky junction, it is possible to reduce leakage current while preventing increase in source resistance, or to improve breakdown voltage while preventing increase in source resistance. A semiconductor device capable of achieving the above can be provided. Furthermore, the breakdown voltage of the semiconductor device can be further improved by providing a structure in which the cap layer is left in a wider range between the gate and the drain.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
A semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. 1A is a cross-sectional view of a field effect transistor (FET) 100 according to a first embodiment of the present invention, and FIG. 1B is a top view thereof. The field-effect transistor 100 has a composition ratio of about GaN buffer layer 102 having a thickness of about 2 to 3 μm, channel layer 103 made of GaN or InGaN, and AlN on a substrate 101 made of sapphire or SiC. 0.15 to 0.5, and an n-type impurity such as Si is about 2 × 1018cm-3In this structure, an n-type AlGaN electron supply layer 104 added at a concentration of ˜10 and a GaN cap layer 105 with a thickness of about 10 to 20 nm are sequentially stacked. The GaN cap layer 105 is selectively etched away leaving only the central portion, and a gate electrode 107 is formed on the GaN cap layer 105. The source electrode 106 and the drain electrode 108 are formed adjacent to the gate electrode 107 on the surface of the AlGaN electron supply layer 104 after the GaN cap layer 105 is removed and exposed. Here, the surface of each nitride layer is formed of a c-plane of group III atoms.
[0030]
As shown in FIG. 1B, an isolation region 110 surrounding the element formation region 109 is formed around the element formation region 109 by a method that does not involve etching such as ion implantation. The GaN cap layer 105 is formed in a wider range than the gate electrode 107. The GaN cap layer 105 is formed so as not to contact the source electrode 106 and the drain electrode 108. The GaN cap layer 105 acts to increase the effective barrier height (peak potential) of the Schottky electrode, which is explained by the difference in the magnitude of polarization generated in the GaN cap layer 105 and the AlGaN electron supply layer 104. The
[0031]
Next, the influence of polarization generated when stress is applied to the field effect transistor 100 having such a configuration will be described.
[0032]
Since the GaN buffer layer 102 is sufficiently thick to relieve the compressive strain associated with lattice mismatch, piezo polarization due to the effect of strain does not occur, and only spontaneous polarization occurs. On the other hand, the AlGaN electron supply layer 104 receives tensile strain, and large piezo polarization is generated inside in addition to spontaneous polarization. The direction of this polarization is the c-axis direction of the substrate 101, that is, the direction perpendicular to the surface of the substrate 101. Considering the effect of such polarization, the potential in the depth direction was theoretically calculated with respect to the interface between the GaN cap layer 105 and the gate electrode 107 (distance 0) for the semiconductor device 100 shown in FIG. 1A. The results are shown in FIG.
[0033]
In FIG. 2, the thickness of the GaN cap layer 105 is set to 10 nm and the gate voltage is set to 0V. Due to the influence of polarization, a potential difference is generated in the GaN cap layer 105, and thereby the potential (peak potential shown in FIG. 2) at the heterointerface with the AlGaN electron supply layer 104 is raised. This increases the effective Schottky barrier.
[0034]
FIG. 3 shows the change in effective barrier height (peak potential) when the thickness of the GaN cap layer 105 is changed from 0 to 20 nm (indicated by x in FIG. 3), the GaN cap layer 105 and the AlGaN. The result of theoretical calculation of the change in the concentration of electrons accumulated at the hetero interface with the electron supply layer 104 (indicated by ◯ in FIG. 3) is shown.
[0035]
As shown in FIG. 3, as the thickness of the GaN cap layer 105 increases, the effective Schottky electrode barrier height (peak potential) gradually increases, while the GaN cap layer 105 and the AlGaN electron supply layer 104 It can be seen that the concentration of electrons accumulated at the heterointerface of the lowers. The reason why the peak potential increases is that the barrier height of the Schottky electrode with respect to the GaN cap layer 105 is constant, whereas the potential difference generated in the GaN cap layer 105 increases as the film thickness of the GaN cap layer 105 increases. Because. Therefore, inserting the GaN cap layer 105 effectively increases the peak potential. Further, as the thickness of the GaN cap layer 105 increases, the electron concentration decreases. This is because a reverse bias is applied to the gate electrode by a potential difference generated in the GaN cap layer 105.
[0036]
As described above, the provision of the GaN cap layer 105 increases the peak potential and decreases the concentration of electrons accumulated at the heterointerface. All of these contribute to the high breakdown voltage of the field effect transistor. However, there is a component that flows along the surface of the buffer layer 102 in the leakage current, and this leakage is particularly caused in a material that generates a donor due to a lack of surface nitrogen atoms such as GaN contained in the buffer layer 102. It is important to reduce the current component. In addition, a decrease in the concentration of electrons accumulated at the heterointerface leads to an increase in the resistance of the region where the GaN cap layer 105 is present, increases the source resistance of the field effect transistor, and leads to a decrease in transistor performance.
[0037]
In the field effect transistor 100 of the present invention, since the GaN cap layer 105 in the region between the gate and the source is removed (that is, the source electrode 106 and the cap layer 105 are not in direct contact), the source resistance is further increased. Reduced. Furthermore, the leakage current between the source and gate and between the gate and drain is also removed from the GaN cap layer 105 (that is, the source electrode 106 and the cap layer 105 are not in direct contact, and the drain electrode 108 and the cap layer 105 are directly in contact with each other). It can be reduced by not contacting. As already described, due to the potential difference generated in the GaN cap layer 105, the potential becomes discontinuous in the in-plane direction indicated by arrow a in FIG. 1B, and electrons contributing to the leakage current must acquire energy exceeding this discontinuous value. Because it will not be. Since the energy at room temperature is about 26 meV, if the discontinuity value of potential is 260 meV, the leakage current will be reduced by about four orders of magnitude, which is a very significant effect. When the change of the peak potential in FIG. 3 is actually observed, the potential discontinuity value of about 1 eV can be obtained by inserting the GaN cap layer 105 having a thickness of 10 nm as compared with the case where the GaN cap layer 105 is not inserted. Further, it is expected that the leakage current value can be further reduced.
[0038]
FIG. 4 shows a field effect transistor (FET) 400 which is a first modification of the first embodiment of the present invention. The field effect transistor 400 is different from the field effect transistor 100 described with reference to FIG. 1A in that the portion of the GaN cap layer 405 on which the gate electrode 407 is stacked is thinned or removed by etching. It is different. FIG. 4 shows an example in which the gate electrode 407 is in contact with the current supply layer 404. In this way, the GaN cap layer 405 is thinned or removed, and the gate electrode 407 is laminated in that region, thereby preventing deterioration of mutual conductance due to the GaN cap layer 405. In this case, although the height of the Schottky barrier is not improved, it contributes to the reduction of the leakage current by utilizing the potential discontinuity in the horizontal direction on the surfaces of the GaN cap layer and the AlGaN electron supply layer.
[0039]
In the semiconductor device 100 shown in FIG. 1A, the example in which the surface area of the cap layer 105 is larger than the surface area of the gate electrode 107 is shown, but the present invention is not limited to this. FIG. 5 shows a field effect transistor (FET) 500 which is a second modification of the first embodiment of the present invention. The field effect transistor 500 is different from the field effect transistor 100 described with reference to FIG. 1A in that the width of the GaN cap layer 505 is smaller than the width of the gate electrode 507. Therefore, in the field effect transistor 500, the gate electrode 507 is stacked in a state of spreading on both sides of the GaN cap layer 505. Even with this configuration, it is possible to obtain the effects of reducing leakage current and improving breakdown voltage.
(Embodiment 2)
6A to 6E are cross-sectional views of a field effect transistor (FET) according to the second embodiment of the present invention. The field effect transistor shown in FIGS. 6A to 6E is provided with a GaN cap layer 605 for the purpose of improving the breakdown voltage.
[0040]
The field effect transistor (FET) 600 shown in FIG. 6A is different from the field effect transistor (FET) 100 shown in FIG. 1 in that the gate electrode 607 provided on the GaN cap layer 605 is disposed closer to the source electrode 606. Different in that it is. As a result, the depletion layer extending in the channel layer 603 directly below the gate electrode 607 can be further expanded to the drain electrode 608 side, and the breakdown voltage of the field effect transistor 600 can be improved.
[0041]
The field effect transistor 610 shown in FIG. 6B is different from the field effect transistor 600 shown in FIG. 6A in that the portion of the GaN cap layer 605 where the gate electrode 607 is formed is thinned or removed by etching. It is different in point. In the field effect transistor 610 of FIG. 6B, the GaN cap layer is etched so that the gate electrode 607 is in contact with the current supply layer 604. In the field effect transistor 610 shown in FIG. 6B, the transconductance deteriorated by introducing the GaN cap layer 605 can be improved.
[0042]
In the field effect transistor 620 shown in FIG. 6C, the gate electrode 607 is provided on the side edge on the source electrode 606 side on the GaN cap layer 605 and on the electron supply layer 604 along the side edge. Accordingly, the GaN cap layer 605 is located between the gate electrode 607 and the drain electrode 608. In the configuration of the field effect transistor 620 shown in FIG. 6C, the gate-source leakage current is not improved, but the gate-drain breakdown voltage is improved. In particular, since the gate electrode 607 is formed over the side edge of the cap layer 605 on the source electrode 606 side, electric field concentration in the region on the drain electrode side where the gate electrode 607 is in contact with the electron supply layer 604 can be reduced. Therefore, the breakdown voltage between the gate and the drain is further improved. Further, similarly to the field effect transistor 610 shown in FIG. 6B, an increase in the source resistance can be prevented and the mutual conductance of the FET can be improved.
[0043]
In the above embodiment, an example in which GaN is used as the cap layer 605 has been described. However, when GaN is used as the cap layer 605, the thickness cannot be increased too much. This is because, as shown in FIG. 3, the sheet electron concentration becomes too low by increasing the thickness of GaN, and / or the peak potential becomes too high, so that holes are formed between the cap layer 605 and the electron supply layer 604. This is because there will be a situation in which it will accumulate. The demand to increase the thickness of the cap layer 605 without significantly affecting the sheet electron density occurs particularly in the field effect transistor 620 shown in FIG. 6C. This is because if the cap layer 605 is thickened in the field effect transistor 620, the electric field concentration near the drain side of the gate electrode 607 is relaxed, and the breakdown voltage of the field effect transistor 620 is improved. Further, when the cap layer 605 is thickened in the field effect transistor 620, the parasitic gate capacitance of the portion where the gate electrode 607 overlaps the cap layer 605 can be reduced, which leads to improvement of the high frequency characteristics of the field effect transistor 620.
[0044]
There are the following two methods for increasing the thickness of the cap layer 605 while keeping the sheet electron concentration moderately lowered. The first is to use an InGaAlN cap layer instead of the GaN cap layer 605. Second, an n-type impurity is added to the cap layer to reduce a potential difference generated in the cap layer.
[0045]
In the first method, one of the requirements for the composition of InGaAlN is to make the c-plane lattice constant substantially match the lattice constant of the GaN buffer layer in order to increase the film thickness. To do this, In0.18Al0.72Since lattice matching can be achieved with N and GaN, In0.18Al0.72A mixed crystal of N and GaN may be used. Ie (In0.18Al0.72)xGa1-xThe composition may be N. In practice, some compositional deviation is allowed. Another requirement is to keep the magnitude of polarization inside the InGaAlN cap layer smaller than the magnitude of polarization generated in the AlGaN electron supply layer 604. This means (In0.18Al0.72)xGa1-xThe value of x of N is limited, but the upper limit of the value of x depends on the composition of AlN in the AlGaN electron supply layer 604. When the upper limit of x is calculated by calculation for the AlN composition of the AlGaN electron supply layer 604 that is often used, the upper limit of x is about 0.16 when the AlN composition of the AlGaN electron supply layer 604 is 10%. When the AlN composition is 30%, the upper limit of x is about 0.47. The upper limit of x may be considered to be about 1.5 times the AlN composition ratio of the AlGaN electron supply layer 604.
[0046]
In the second method, an appropriate thickness of the cap layer 605 is determined by the concentration of the impurity to be added. The material of the cap layer may be GaN or InGaAlN, but it is assumed that GaN is used. Considering increasing the thickness of the cap layer while maintaining the same potential as that in FIG. 2 in the region below the AlGaN electron supply layer 104 (that is, the region having a distance of 10 nm or more in FIG. 2).
[0047]
In FIG. 2, the surface potential of the cap layer 105 is fixed at a Schottky barrier height of 0.76V. At this point, if the doping is performed so that the electric field becomes zero and the electric potential (about 1.6 V) at the boundary between the cap layer 105 and the AlGaN electron supply layer 104 is equalized, an undoped GaN layer can be formed on the cap layer as much as possible. It can be formed. When such conditions are estimated, the thickness of the cap layer is 16.7 nm, and the doping concentration of n-type impurities is 3 × 10.18/ CmThreeIs obtained. An undoped GaN cap layer having a desired thickness may be formed on the n-type GaN cap layer.
[0048]
The above-described configuration of the cap layer is an example to show the feasibility of the embodiment, and actually a cap layer in which various concentrations and thicknesses are combined can be designed. In the case where charge control by the gate electrode is mainly performed at the portion where the gate electrode 607 and the electric field supply layer 604 are in contact like the field effect transistors 610 and 620 shown in FIGS. 6B and 6C, FIGS. 6D and 6E. As shown in the field effect transistors 630 and 640, the cap layer 605 may be a combination of a semiconductor layer 605b such as an n-type GaN layer and an insulating film 605a formed thereon. Insulating film is SiO2Although a film or a silicon nitride film can be used, it is preferable to use a silicon nitride film which is said to have a low interface state density. Note that a field effect transistor 630 illustrated in FIG. 6D includes a semiconductor layer 605b and an insulating film 605a provided thereon instead of the cap layer 605 of the field effect transistor 610 illustrated in FIG. 6B. A field-effect transistor 640 shown is obtained by providing a semiconductor layer 605b and an insulating film 605a thereon instead of the cap layer 605 of the field-effect transistor 620 shown in FIG. 6C. In the field effect transistor 630, the gate electrode 607 is formed so as to be in contact with not only the AlGaN electron supply layer 604 but also the upper surface of the cap layer 605. However, also in the field effect transistor 610, the gate electrode 607 includes only the AlGaN electron supply layer 604. Needless to say, the cap layer 605 may be formed so as to be in contact with the upper surface. In particular, as described above, it is expected that the breakdown voltage is improved by extending the gate electrode 607 on the cap layer 605 to the drain side.
(Embodiment 3)
The structure of the field effect transistor (FET) described in the first and second embodiments is the case where the surface of the heterostructure is a group III atom, but when the nitrogen of the group V atom forms the surface, another structure is employed. It is necessary to. An example in which the surface of the heterostructure is a group V atom nitrogen will be described below.
[0049]
FIG. 7 shows a field effect transistor 700 as the above specific example. The field effect transistor 700 includes an AlGaN buffer layer 702 having a film thickness of about 2 to 3 μm and an AlN composition ratio of about 0.15 to 0.5 on a substrate 701 formed of sapphire or SiC, Si and the like. About 2 × 10 n-type impurities18cm-3In this structure, an n-type AlGaN electron supply layer 703 added at a concentration, a channel layer 704 made of GaN or InGaN having a thickness of about 15 to 20 nm, and an AlGaN cap layer 705 having a thickness of about 10 nm are sequentially stacked. In this field effect transistor 700, the AlN composition ratio in each AlGaN layer may be the same, but the AlN composition of the AlGaN cap layer 705 on the surface can be made larger than the AlN composition of the AlGaN buffer layer 702 in consideration of the polarization effect. . Similar to the field effect transistor 100 shown in FIG. 1A, the AlGaN cap layer 705 is selectively removed leaving only the central portion, and a gate electrode 707 is formed on the AlGaN cap layer 705. A source electrode 706 and a drain electrode 708 are formed adjacent to the gate electrode 707 and on the channel layer 704 after the AlGaN cap layer 705 has been removed. As described above, the surface of each nitride layer is formed of the c-plane of group V atoms (nitrogen).
[0050]
In the heterostructure field effect transistor 700 mainly composed of GaN, the growth conditions in the molecular beam epitaxy method in which the surface is a group V atom have already been reported. When the film is formed so that the surface is a group V atom, the direction of polarization generated in each layer is opposite to the case where the surface is a group III atom. Therefore, the buffer of the field effect transistor 100 shown in FIG. AlGaN is used as the buffer layer 702 instead of GaN as a material for forming the layer 102. An electron supply layer 703 containing AlGaN doped with an n-type impurity such as Si and a channel layer 704 are sequentially formed thereon. Electrons are supplied to the channel layer 704 from the AlGaN electron supply layer 703 below the channel layer 704 and positive charges induced by the polarization difference between the channel layer 704 and the electron supply layer 703. Therefore, normally, the gate electrode is directly formed on the channel layer 704. Here, the AlGaN buffer layer 702 is formed to be sufficiently thick so that the lattice strain is relaxed, and the channel layer 704 containing GaN or InGaN is formed to be relatively thin as several tens of nm because it receives compressive strain. As the cap layer 705, AlGaN is used instead of GaN.
[0051]
By adopting such a configuration, an increase in source resistance and a reduction in leakage current can be achieved for the same reason as described in the first embodiment.
[0052]
Furthermore, many modifications can be considered in this embodiment, and these modifications are shown as field effect transistors (FETs) in FIGS. 8A to 8E. However, in the field effect transistor shown in FIGS. 8A to 8E, the surface of each nitride layer is formed of a c-plane of group V atoms (nitrogen).
[0053]
The field effect transistor 800 shown in FIG. 8A has a configuration in which a portion of the AlGaN cap layer 805 that forms the gate electrode 807 is thinned or removed by etching in the same manner as the field effect transistor 400 shown in FIG. Is. By adopting such a configuration, it is possible to improve the mutual conductance that is deteriorated by introducing the AlGaN cap layer 805.
[0054]
A field effect transistor 810 shown in FIG. 8B corresponds to the field effect transistor 500 shown in FIG. In the field effect transistor (FET) 810, the gate electrode 807 is formed on the AlGaN cap layer 805, but the surface area of the AlGaN cap layer 805 is smaller than the surface area of the gate electrode 807. Accordingly, the AlGaN cap layer 805 is formed inside the bottom surface of the gate electrode 807. With the structure of the field-effect transistor 810, leakage current can be reduced and breakdown voltage can be improved.
[0055]
The field effect transistor 820 shown in FIG. 8C corresponds to the field effect transistor 600 shown in FIG. 6A. The field effect transistor 820 is different from the field effect transistor (FET) 800 shown in FIG. 8A in the position of the gate electrode 807 provided on the AlGaN cap layer 805. By disposing the gate electrode 807 on the source electrode 806 side, the area occupied by the AlGaN cap layer 805 between the gate and the drain becomes wider. With such a structure, a depletion layer extending to the channel layer 804 immediately below the gate electrode 807 can be further extended to the drain electrode 808 side, and the withstand voltage of the field-effect transistor 820 can be improved.
[0056]
The field effect transistor 830 shown in FIG. 8D corresponds to the field effect transistor 610 shown in FIG. 6B. The field effect transistor 830 is different from the field effect transistor 820 shown in FIG. 8C in that the portion of the AlGaN cap layer 805 where the gate electrode 807 is formed is thinned or removed by etching. By introducing the AlGaN cap layer 805 as in the structure of the field effect transistor 830, the deteriorated transconductance can be improved.
[0057]
The field effect transistor 840 shown in FIG. 8E corresponds to the field effect transistor 620 shown in FIG. 6C. The field effect transistor 840 has a structure in which an AlGaN cap layer 805 is provided between the gate electrode 807 and the drain electrode 808. With the structure of the field effect transistor 840, the leakage current between the gate and the source is not improved, but the breakdown voltage between the gate and the drain is improved.
[0058]
Increasing the thickness of the cap layer 805 is effective in improving the breakdown voltage between the gate and the drain of the FET in the structure of the field effect transistor 840. However, when the surface is a group V atom, it is not easy to increase the thickness of the cap layer 805 using a material other than AlGaN. Unlike the case where the surface of the heterostructure is a group III, GaN constituting the channel layer 804 receives compressive stress in the plane, so that the direction of spontaneous polarization and the direction of polarization due to the piezo effect are opposite to each other. This is because the absolute value of the polarization generated inside the channel layer 804 of GaN becomes considerably small. For materials that lattice-match with the AlGaN buffer layer 802, a material that can make the polarization value smaller than that of AlGaN cannot be found. Therefore, doping the cap layer 805 as described in Embodiment 2 is simpler and more effective than using a material other than AlGaN to thicken the cap layer.
[0059]
As described in Embodiment Mode 2, it is also effective for the field effect transistors 830 and 840 to use a combination of an AlGaN layer and an insulating film formed thereon as the cap layer 805. Insulating film is SiO2Although a film or a silicon nitride film can be used, it is preferable to use a silicon nitride film which is said to have a low interface state density.
[0060]
Note that the GaN buffer layers 102, 402, 502, and 602 and the AlGaN buffer layers 702 and 802 shown in the present invention are relatively thin AlN having a thickness of about 100 nm on the substrates 101, 401, 501, 601 and 701, 801, respectively. Although it has been reported so far to be formed through layers, it goes without saying that the present invention can be applied to such a case without any substantial change.
[0061]
【The invention's effect】
The semiconductor device of the present invention can reduce leakage current while preventing an increase in source resistance of a gallium nitride heterostructure, or can improve breakdown voltage while preventing an increase in source resistance (electric field effect). Type transistor).
As a result, the power characteristics of the semiconductor device having a gallium nitride heterostructure can be improved.
[Brief description of the drawings]
FIG. 1A is a cross-sectional view illustrating a field effect transistor according to a first embodiment of the present invention.
FIG. 1B is a top view illustrating the field effect transistor according to the first embodiment of the invention.
FIG. 2 is a potential diagram according to the first embodiment of the present invention.
FIG. 3 is a graph showing the dependence of sheet electron concentration and peak potential on the GaN cap layer thickness according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a field effect transistor according to a modification of the first embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating a field effect transistor according to another modification of the first embodiment of the present invention.
FIG. 6A is a cross-sectional view illustrating a field effect transistor according to a second embodiment of the present invention.
FIG. 6B is a cross-sectional view illustrating a field effect transistor according to the second embodiment of the present invention.
FIG. 6C is a cross-sectional view illustrating a field effect transistor according to the second embodiment of the present invention.
FIG. 6D is a cross-sectional view illustrating a field effect transistor according to the second embodiment of the present invention.
FIG. 6E is a cross-sectional view illustrating a field effect transistor according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view illustrating a field effect transistor according to a third embodiment of the present invention.
FIG. 8A is a cross-sectional view illustrating a field effect transistor according to a modification of the third embodiment of the present invention.
FIG. 8B is a cross-sectional view illustrating a field effect transistor according to a modification of the third embodiment of the present invention.
FIG. 8C is a cross-sectional view illustrating a field effect transistor according to a modification of the third embodiment of the present invention.
FIG. 8D is a cross-sectional view illustrating a field effect transistor according to a modification of the third embodiment of the present invention.
FIG. 8E is a cross-sectional view illustrating a field effect transistor according to a modification of the third embodiment of the present invention.
FIG. 9 is a cross-sectional view illustrating a conventional field effect transistor.
[Explanation of symbols]
101 substrate
102 Buffer layer
103 channel layer
104 Electron supply layer
105 Cap layer
106 Source electrode
107 Gate electrode
108 Drain electrode

Claims (15)

  1. A substrate,
    A buffer layer made of GaN is formed over the substrate, the surface of the buffer layer is a c-plane of the Ga atoms, a buffer layer,
    A channel layer made of GaN or InGaN is formed on the buffer layer, the surface of the channel layer is a c-plane of the Ga or In atoms, and the channel layer,
    An electronic supply layer composed of AlGaN formed on the channel layer, the surface of the electron supply layer is a c-plane Al or Ga atoms, and the electron supply layer,
    A source electrode and a drain electrode formed on the electron supply layer;
    A cap layer made of GaN is formed between said source electrode and said drain electrode, the surface of the cap layer is a c-plane of the Ga or In atoms, at least a portion of the cap layer electronic supplies A cap layer in contact with the layer;
    A gate electrode formed so as to be at least partially in contact with the cap layer;
    A semiconductor device comprising :
    A semiconductor device formed so that at least a part of the gate electrode is in contact with the electron supply layer .
  2.   The semiconductor device according to claim 1, wherein the gate electrode is formed on the cap layer.
  3. Before the composition of Kiki cap layer take nearly lattice constant matching between the buffer layer in the c-plane, and the absolute value of the magnitude of the polarization that occurs in the cap layer of the polarization generated in the electron supply layer The semiconductor device according to claim 1, wherein the electron supply layer is formed to be smaller than an absolute value.
  4.   The semiconductor device according to claim 1, wherein the gate electrode is located closer to the source electrode than the drain electrode.
  5. The semiconductor device according to claim 2 , wherein a surface area of the gate electrode is larger than a surface area of the cap layer.
  6. A substrate,
      A buffer layer made of GaN formed on the substrate, wherein the buffer layer surface is a c-plane of Ga atoms;
      A channel layer made of GaN or InGaN formed on the buffer layer, the surface of the channel layer being a c-plane of Ga or In atoms;
      An electron supply layer made of AlGaN formed on the channel layer, the surface of the electron supply layer being a c-plane of Al or Ga atoms;
      A source electrode and a drain electrode formed on the electron supply layer;
      A cap layer made of InGaAlN formed between the source electrode and the drain electrode, the surface of the cap layer being a c-plane of Ga or In atoms, and at least a part of the cap layer being the electron supply A cap layer in contact with the layer;
      A gate electrode formed so as to be at least partially in contact with the cap layer;
    A semiconductor device comprising:
      The composition of the cap layer is substantially lattice-matched with the buffer layer in the c-plane, and the absolute value of the magnitude of the polarization generated in the cap layer is the absolute value of the polarization generated in the electron supply layer. A semiconductor device in which the electron supply layer is formed to be smaller than that.
  7. The semiconductor device according to claim 6, wherein at least a part of the gate electrode is formed in contact with the electron supply layer.
  8. The semiconductor device according to claim 6, wherein the gate electrode is formed on the cap layer.
  9. The semiconductor device according to claim 6, wherein the gate electrode is located closer to the source electrode than the drain electrode.
  10. The semiconductor device according to claim 8, wherein a surface area of the gate electrode is larger than a surface area of the cap layer.
  11. A substrate,
      A buffer layer made of GaN formed on the substrate, wherein the buffer layer surface is a c-plane of Ga atoms;
      A channel layer made of GaN or InGaN formed on the buffer layer, the surface of the channel layer being a c-plane of Ga or In atoms;
      An electron supply layer made of AlGaN formed on the channel layer, the surface of the electron supply layer being a c-plane of Al or Ga atoms;
      A source electrode and a drain electrode formed on the electron supply layer;
      A cap layer made of GaN formed between the source electrode and the drain electrode, the surface of the cap layer being a c-plane of Ga or In atoms, and at least a part of the cap layer being the electron supply A cap layer in contact with the layer;
      A gate electrode formed so as to be at least partially in contact with the cap layer;
    A semiconductor device comprising:
      A semiconductor device in which an n-type impurity is partially or wholly added to the cap layer.
  12. The semiconductor device according to claim 11, wherein at least a part of the gate electrode is formed in contact with the electron supply layer.
  13. The semiconductor device according to claim 11, wherein the gate electrode is formed on the cap layer.
  14. The semiconductor device according to claim 1, wherein the gate electrode is located closer to the source electrode than the drain electrode.
  15. The semiconductor device according to claim 13, wherein a surface area of the gate electrode is larger than a surface area of the cap layer.
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Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6548333B2 (en) * 2000-12-01 2003-04-15 Cree, Inc. Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment
US7030428B2 (en) 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors
US6982204B2 (en) 2002-07-16 2006-01-03 Cree, Inc. Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
JP4077731B2 (en) 2003-01-27 2008-04-23 富士通株式会社 Compound semiconductor device and manufacturing method thereof
JP3940699B2 (en) 2003-05-16 2007-07-04 株式会社東芝 Power semiconductor device
US7501669B2 (en) * 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
TWI560783B (en) 2003-09-09 2016-12-01 Univ California Fabrication of single or multiple gate field plates
US7901994B2 (en) 2004-01-16 2011-03-08 Cree, Inc. Methods of manufacturing group III nitride semiconductor devices with silicon nitride layers
US7045404B2 (en) 2004-01-16 2006-05-16 Cree, Inc. Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
US7612390B2 (en) 2004-02-05 2009-11-03 Cree, Inc. Heterojunction transistors including energy barriers
US7170111B2 (en) 2004-02-05 2007-01-30 Cree, Inc. Nitride heterojunction transistors having charge-transfer induced energy barriers and methods of fabricating the same
JP4759923B2 (en) * 2004-03-11 2011-08-31 住友電気工業株式会社 Semiconductor device
US7084441B2 (en) 2004-05-20 2006-08-01 Cree, Inc. Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
US7238560B2 (en) 2004-07-23 2007-07-03 Cree, Inc. Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
US20060017064A1 (en) 2004-07-26 2006-01-26 Saxler Adam W Nitride-based transistors having laterally grown active region and methods of fabricating same
US7456443B2 (en) 2004-11-23 2008-11-25 Cree, Inc. Transistors having buried n-type and p-type regions beneath the source region
US7709859B2 (en) 2004-11-23 2010-05-04 Cree, Inc. Cap layers including aluminum nitride for nitride-based transistors
US7161194B2 (en) 2004-12-06 2007-01-09 Cree, Inc. High power density and/or linearity transistors
US7355215B2 (en) 2004-12-06 2008-04-08 Cree, Inc. Field effect transistors (FETs) having multi-watt output power at millimeter-wave frequencies
US9640649B2 (en) 2004-12-30 2017-05-02 Infineon Technologies Americas Corp. III-nitride power semiconductor with a field relaxation feature
US7465967B2 (en) 2005-03-15 2008-12-16 Cree, Inc. Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions
US8575651B2 (en) 2005-04-11 2013-11-05 Cree, Inc. Devices having thick semi-insulating epitaxial gallium nitride layer
US7626217B2 (en) 2005-04-11 2009-12-01 Cree, Inc. Composite substrates of conductive and insulating or semi-insulating group III-nitrides for group III-nitride devices
US7544963B2 (en) 2005-04-29 2009-06-09 Cree, Inc. Binary group III-nitride based high electron mobility transistors
US7615774B2 (en) 2005-04-29 2009-11-10 Cree.Inc. Aluminum free group III-nitride based high electron mobility transistors
US9331192B2 (en) 2005-06-29 2016-05-03 Cree, Inc. Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same
JP2009522812A (en) * 2006-01-09 2009-06-11 インターナショナル レクティファイアー コーポレイション Group III nitride power semiconductor with electric field relaxation function
US7709269B2 (en) 2006-01-17 2010-05-04 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
JP4818844B2 (en) * 2006-08-03 2011-11-16 トヨタ自動車株式会社 Contact hole forming method and semiconductor device manufacturing method
US8823057B2 (en) 2006-11-06 2014-09-02 Cree, Inc. Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
JP5105160B2 (en) 2006-11-13 2012-12-19 クリー インコーポレイテッドCree Inc. Transistor
JP2008211172A (en) * 2007-01-31 2008-09-11 Matsushita Electric Ind Co Ltd Semiconductor device and method for fabricating the same
JP2009004504A (en) * 2007-06-20 2009-01-08 Fujitsu Ltd Compound semiconductor device and method of manufacturing the same
JP2009054632A (en) * 2007-08-23 2009-03-12 Fujitsu Ltd Field-effect transistor
JP2009231396A (en) * 2008-03-19 2009-10-08 Sumitomo Chemical Co Ltd Semiconductor device and method for manufacturing semiconductor device
JP2011044457A (en) * 2009-08-19 2011-03-03 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device, and method of manufacturing semiconductor device
JP5638225B2 (en) * 2009-11-11 2014-12-10 三菱電機株式会社 Heterojunction field effect transistor and manufacturing method thereof
JP5221577B2 (en) * 2010-03-08 2013-06-26 トヨタ自動車株式会社 Semiconductor device and manufacturing method thereof
EP2562799A1 (en) * 2010-04-22 2013-02-27 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing same
WO2012063329A1 (en) * 2010-11-10 2012-05-18 三菱電機株式会社 Semiconductor device, and method for producing semiconductor device
JP5418482B2 (en) * 2010-12-08 2014-02-19 富士通株式会社 Compound semiconductor multilayer structure
JP5179611B2 (en) * 2011-03-04 2013-04-10 シャープ株式会社 Normally-off heterojunction field effect transistor
US9373688B2 (en) * 2011-05-04 2016-06-21 Infineon Technologies Austria Ag Normally-off high electron mobility transistors
JP5991000B2 (en) * 2012-04-23 2016-09-14 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP6419418B2 (en) 2013-05-29 2018-11-07 三菱電機株式会社 Semiconductor device
JP6225584B2 (en) * 2013-09-13 2017-11-08 富士電機株式会社 Semiconductor device evaluation method, semiconductor device and manufacturing method thereof
JP6215786B2 (en) * 2014-07-18 2017-10-18 日本電信電話株式会社 Semiconductor device
JP6332021B2 (en) * 2014-12-26 2018-05-30 株式会社デンソー Semiconductor device
JP2018056299A (en) 2016-09-28 2018-04-05 富士通株式会社 Compound semiconductor substrate and manufacturing method of the same, compound semiconductor device and manufacturing method of the same, power supply unit, and high-power amplifier

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223901A (en) * 1996-12-04 1998-08-21 Sony Corp Field effect transistor and manufacture of the same
JPH10294452A (en) * 1997-04-22 1998-11-04 Sony Corp Heterojunction field effect transistor
JPH10335637A (en) * 1997-05-30 1998-12-18 Sony Corp Hetero-junction field effect transistor
JPH11261052A (en) * 1998-03-09 1999-09-24 Furukawa Electric Co Ltd:The High electron mobility transistor
JPH11297713A (en) * 1998-04-14 1999-10-29 Furukawa Electric Co Ltd:The Field effect transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223901A (en) * 1996-12-04 1998-08-21 Sony Corp Field effect transistor and manufacture of the same
JPH10294452A (en) * 1997-04-22 1998-11-04 Sony Corp Heterojunction field effect transistor
JPH10335637A (en) * 1997-05-30 1998-12-18 Sony Corp Hetero-junction field effect transistor
JPH11261052A (en) * 1998-03-09 1999-09-24 Furukawa Electric Co Ltd:The High electron mobility transistor
JPH11297713A (en) * 1998-04-14 1999-10-29 Furukawa Electric Co Ltd:The Field effect transistor

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