JPH10294452A - Heterojunction field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a heterojunction field effect transistor in which the intrinsic performance of an element using a GaN semiconductor is displayed by optimizing a structure, to realize high performance. SOLUTION: An Alx Ga1-x N (1>=x>=0) layer 1 acting as a base layer, an Aly Ga1-y N (1>=y>0) layer 2 acting as a barrier layer, an n-type Alz Ga1-z N (1>=z>=0) layer 3 acting as an electron supply layer, an undoped Ga1-u Inu N (1>=u>=0) layer 5 acting as an electron transit layer and an Alv Ga1-v N (1>=v>0) layer 8 acting as a gate insulation film are laminated in this order. A gate electrode 9 is provided on the Alv Ga1-v N layer 8, and further a source electrode 10 and a drain electrode 11 are provided on the undoped Ga1-u Inu N layer 5. In this way a GaN FET(field effect transistor) containing both of a MIS(metal insulator semiconductor) structure and a HEMT(high electron mobility transistor) structure is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a heterojunction field effect transistor, and more particularly to a heterojunction field effect transistor using a GaN-based semiconductor.

[0002]

2. Description of the Related Art The saturation electron velocity of GaN is about 2.0 × 10
⁷ cm / s larger than Si, GaAs and SiC,
The breakdown electric field is about 5 × 10 ⁶ V / cm, which is the second largest after diamond. For these reasons, GaN-based semiconductors have been expected to have great potential as materials for high-frequency, high-temperature, high-power semiconductor devices. In recent years, a prototype example of a GaN-based field effect transistor (FET) has been described as a so-called high electron mobility transistor (High E
lectron Mobility Transistor, HEMT) (for example, Appl. Phys. Lett. 62 (1
5), 1786 (1993), Appl. Phys. Lett. 65 (9), 1121 (1994)
Phys. Lett. 69 (6), 794 (1996) and Appl. Phy.
s. Lett. 68 (20), 2849 (1996)).

FIG. 9 shows a conventional GaN-based HEMT (Appl. Phys. Lett. 68 (20), 2849 (1996)). As shown in FIG. 9, in this GaN-based HEMT, an AlN buffer layer 102 and an undoped G
aN layer 103, Al _0.16 Ga _0.84 N layer 104, undoped GaN layer 105 as an electron transit layer (channel layer),
Al _0.16 Ga _0.84 N layer 106 as a spacer layer, n-type Al _0.16 Ga _0.84 N layer 107 as an electron supply layer, Al _0.16 Ga _0.84 N layer 108 as a barrier layer, and n-type Al _0.06 Ga _0.94 N as a cap layer The layers 109 are sequentially stacked. On the n-type Al _0.06 Ga _0.94 N layer 109,
A gate electrode 110, a source electrode 111, and a drain electrode 112 are provided. Here, the gate electrode 110
Is in Schottky contact with the n-type Al _0.06 Ga _0.94 N layer 109, and the source electrode 111 and the drain electrode 112 are in ohmic contact with the n-type Al _0.06 Ga _0.94 N layer 109.

[0004]

However, according to the inventor's knowledge, the above-mentioned conventional GaN-based HEMT has the following problems.
The optimization of the structure was insufficient, and the original performance of the device using the GaN-based semiconductor could not be sufficiently exhibited.

Accordingly, an object of the present invention is to provide a heterojunction field-effect transistor that can exhibit the original performance of a device using a GaN-based semiconductor by optimizing the structure and can achieve high performance. It is in.

[0006]

Means for Solving the Problems The present inventor has made intensive studies in order to solve the above-mentioned problems of the prior art. The outline is as follows.

The present inventors have conducted various studies to optimize the structure of a GaN-based FET. As a result, as shown in FIG. 1, the MIS (Metal-Insulator-Semiconducto)
r) A GaN-based FET having both a structure and a HEMT structure was devised. Here, FIG. 1 shows an energy band diagram under a flat band condition, particularly a conduction band.

As shown in FIG. 1, in this GaN-based FET, an Al _x Ga ₁ -xN layer 1 (where 1 ≧ x ≧ 0) as a base layer and an Al _y Ga _1-y N layer as a barrier layer
Layer 2 (where 1 ≧ y> 0), n-type Al _z Ga _{1 -zN} layer 3 as an electron supply layer (where 1 ≧ z ≧ 0), undoped Al _z Ga ₁ -zN as a spacer layer Layer 4 (1 ≧ z ≧ 0), undoped Ga as electron transit layer
_{1-u InuN} layer 5 (where 1 ≧ u ≧ 0), undoped Al _z Ga _1-z N layer 6 (where 1
≧ z ≧ 0), n-type Al _z Ga ₁ -zN as electron supply layer
A layer 7 (1 ≧ z ≧ 0) and an Al _v Ga _1-v N layer 8 (1 ≧ v> 0) as a gate insulating film are sequentially stacked. Here, n-type Al as an electron supply layer
From _z Ga _1-z N layer 3 and 7, electrons are supplied to the undoped Ga _1-u In u N layer 5 as an electron transit layer, two-dimensional electron gas (2DEG) is formed. The conduction bands of these layers have discontinuities at the heterojunction interface as shown in FIG.

The inventor of the present invention performed a simulation of charge control of a one-dimensional vertical structure in a GaN-based FET having a structure as shown in FIG.
_m (mutual conductance) -V _gs (gate voltage) characteristics and f _T (cut-off frequency) -V _gs characteristics were determined. However,
Temperature T is 300K, the Schottky barrier height V _Scttky is 1.1 eV, saturation electron velocity v _s is 2.0 × 10 ⁷ cm /
s. The composition of each layer is represented by the following formula: x = Al _x Ga ₁ -xN layer 1
0, y = 0.4 of Al _y Ga _1-y N layer 2, n-type Al _z G
a _{1 -z} N layer 3, undoped Al _z Ga _{1 -z} N layer 4, undoped Al _z Ga _{1 -z} N layer 6 and n-type Al _z Ga _{1 -z}
Z = 0.15 in the N layer 7, u = 0.28 of undoped Ga _1-u In u N layer 5 was set to v = 1 of Al _v Ga _1-v N layer 8. At this time, the energy discontinuity existing at the heterojunction interface of these layers is ΔE _c1 = 0.639 eV, ΔE _c2 =
0.413 eV, ΔE _c3 = 0.625 eV, ΔE _c4 =
1.554 eV. The thickness of each layer is Al _x Ga _1-x
The N layer 1 is 50 nm, the Al _y Ga _1-y N layer 2 is 30 nm,
The n-type Al _z Ga _{1 -z} N layer 3 has a thickness of 2 nm and an undoped Al _z
Ga _1-z N layer 4 is 1 nm, an undoped Ga _1-u In u N
The layer 5 is 5 nm, and the undoped Al _z Ga _{1 -z} N layer 6 is 1 n
The m, n-type Al _z Ga _{1 -z} N layer 7 is 2 nm, and the Al _v Ga
_{The 1-v} N layer 8 is 3 nm. Also, n-type Al _z Ga _1-z
Doping concentration dp1 of N layer 7 = 1.0 × 10 ¹⁹ c
m ⁻³ , doping concentration dp of n-type Al _z Ga ₁ -zN layer 3
2 = 5.0 × 10 ¹⁶ cm ⁻³ . _Lg (gate length) =
G _m -V _gs characteristics and f _T for the case of 0.25 μm
The results of determining the -V _gs characteristic are shown by dotted lines in FIGS. 2 and 3, respectively. Fig. 4 shows the conduction band at that time.
Shown in At this time, the undoped G directly under the gate electrode (not shown) provided on the Al _v Ga _1-v N layer 8 is used.
a _1-u In u electronic surface of the N layer 5 density C _s is 5.0 × 1
0 ¹² cm ^-2 .

As can be seen from the curves shown by the dotted lines in FIGS. 2 and 3, when V _gs ≧ −0.3 V, both G _m and f _T sharply decrease. As a result of the examination, as shown in FIG. 4, the cause is that when V _gs increases, Al _v
The electron supply layer on the Ga _1-v N layer 8 side (front side), ie, n
As the conduction band of the type Al _z Ga _{1 -zN} layer 7 decreases, the charge transfer to and from the n-type Al _z Ga _{1 -z} N layer 7 increases, and the undoped Ga _{1 -u} I
It was found that the change in the electric charge of the n _u N layer 5 was small.

The inventor of the present invention has improved the above-mentioned point and has studied to further optimize the structure. As a result, the present inventors have devised the present invention.

That is, in order to achieve the above object, a heterojunction field effect transistor according to the present invention comprises
a base layer composed of _x Ga _1-x N (where 1 ≧ x ≧ 0);
A barrier layer made of Al _y Ga _1-y N (where 1 ≧ y> 0) on the base layer, and an electron supply layer made of Al _z Ga _1-z N (where 1 ≧ z ≧ 0) on the barrier layer And an electron transit layer made of Ga _1-u In _u N (1 ≧ u ≧ 0) on the electron supply layer, and Al _v Ga _1-v N (1 ≧ v> 0) on the electron transit layer ), And a gate insulating film comprising:

In the present invention, the product of the impurity concentration and the thickness of the electron supply layer (hereinafter referred to as “impurity concentration × thickness product”)
Is generally not less than 5 × 10 ¹⁸ [cm ⁻³ ] [nm] and 1
× 10 ²¹ [cm ⁻³ ] [nm] or less, preferably 5
× 10 ¹⁹ [cm ^-3 ] [nm] or more and 5 × 10 ²⁰ [cm ^-3 ]
[Nm] or less. The thickness of the electron transit layer is generally 1 nm or more and 15 nm or less, and preferably 2 nm or less.
nm or more and 10 nm or less.

According to the present invention configured as described above, by optimizing the structure, that is, the electron supply layer is not provided between the gate insulating film and the electron transit layer, By providing the electron supply layer only between the barrier layer, when the gate voltage is increased,
It is possible to prevent the change in the charge of the electron transit layer is reduced, it is possible to G _m, is f _T to prevent the drops sharply.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

In one embodiment of the present invention, the GaN-based FET shown in FIG.
The electron supply layer immediately below the l _v Ga _1-v N layer 8, ie, n
The type Al _z Ga _{1 -zN} layer 7 is removed together with the undoped Al _z Ga _{1 -zN} layer 6 as a spacer layer. Thus, the gate electrode (not shown) provided on the Al _v Ga _1-v N layer 8 and the electron transit layer, that is, the undoped Ga
The distance between _1-u In _u N layer 5 is close, it is possible to perform electronic control of the undoped Ga _1-u In _u N layer 5 by the gate electrode efficiently, it possible to increase the G _m it can. FIG. 5 shows the GaN-based FET at this time.

That is, as shown in FIG. 5, in the GaN-based FET according to this embodiment, A
l _x Ga _1-x N layer 1 (where 1 ≧ x ≧ 0), and Al _y Ga _1-y N layer 2 as a barrier layer (where 1 ≧ y>
0), n-type Al _z Ga _{1 -z} N layer 3 as electron supply layer
(Where 1 ≧ z ≧ 0), undoped Al _z Ga _{1 -zN} layer 4 as a spacer layer (where 1 ≧ z ≧ 0), and undoped Ga _{1-u InuN} layer 5 as an electron transit layer ( (1 ≧ u ≧ 0) and Al _v G as a gate insulating film
a _1-v N layers 8 (where 1 ≧ v> 0) are sequentially stacked.

FIG. 6 shows a specific example of the structure of the GaN-based FET. In FIG. 6, a gate electrode 9 is provided on an Al _v Ga _1-v N layer 8 and an undoped Ga
_A source electrode 10 and a drain electrode 11 are provided on the _{1-u InuN} layer 5. Al _x Ga _1-x N layer 1, Al
_y Ga _1-y N layer 2, n-type Al _z Ga _1-z N layer 3, undoped Al _z Ga _1-z N layer 4, undoped Ga _1-u In _u
The N layer 5 and the Al _v Ga _1-v N layer 8 are usually formed on a substrate such as a sapphire substrate (not shown) by Ga
They are stacked via a buffer layer made of N or AlN.

Now, as shown in FIG. 5, Al _v Ga _1-v
The electron supply layer on the N layer 8 side, that is, n-type Al _z Ga _{1 -z} N
Except for layer 7, instead the electron supply layer at the back, ie n
Type Al _z Ga _{1 -zN} layer 3 (however, doping concentration dp
2 is 1.0 × 10 ¹⁹ cm ⁻³ ) from 2 nm to 4 nm.
And thick, and the other conditions are the same (however, the thickness of the undoped Ga _1-u In _u N layer 5 as the electron transit layer 5n
m), a simulation similar to the above is performed, and G
It was determined _m -V _gs characteristics and f _T -V _gs characteristics. The areal density C _s of electrons in the undoped Ga _{1-u InuN} layer 5 immediately below the gate electrode 9 is 2.0 × 10 ¹³ cm ⁻² . An undoped Ga _1-u In u N layer 5 and the Al _v Ga _1-v N layer 8
The energy discontinuity existing at the heterojunction interface between and is ΔE _c5 = 2.18 eV. G _m obtained at this time
Shown -V _gs characteristics and f _T -V _gs characteristics by a solid line in FIGS. 2 and 3, respectively. FIG. 7 shows the state of the conduction band at that time.

2 and 3, Ga shown in FIG.
As can be seen in comparison with the characteristics of N type FET (shown by a dotted line), G _m is larger throughout, V _gs ≧ -0.3V
It has become extremely less deterioration of f _T in.

Next, undoped Ga as an electron transit layer
The condition of the thickness W of the _{1-u InuN} layer 5 will be discussed.

[0022] The thickness W of the undoped Ga _1-u In u N layer 5 is too small, increasing the gate voltage V _gs,
When the undoped Ga _1-u In _u N layer increases the electron density of 5, increase in the Fermi level (E _f) is vigorously against the undoped Ga _1-u In _u N layer number of electrons 5 N _- type Al _z Ga _{1 -z} N layer 3 as electron supply layer
Relatively increases, and G _m and f _T decrease. Further, the n-type Al _z Ga ₁ -zN layer 3 is
To approach, the n-type Al _z Ga _1-z N layer 3 is more susceptible to relatively gate electrode 9, also narrowed region of Do V _gs magnitude of G _m. This example is shown in FIG. 2 and FIG. Further, considering the easiness of making ohmic contact between the source electrode 10 and the drain electrode 11 and the increase in spreading resistance, W is desirably 2 nm or more. Conversely, if too large W, as shown in FIG. 2, reduction of G _m in low gate voltage V _gs region becomes significant.

Furthermore, as can be seen from FIG. 6, since the undoped Ga _1-u In u n-type as the electron supply layer under the N layer 5 Al _z Ga _1-z N layer 3 as an electron transit layer is,
Between the gate electrode 9 and the source electrode 10 and between the gate electrode 9 and the drain electrode 11, electrons are undoped.
a _1-u In u inner side of the N layer 5 (n-type Al _z Ga _1-z N layer 3
Side). In this case, when the number of electrons in the undoped Ga _{1-u InuN} layer 5 is increased by _{applying the} gate voltage V _gs to the gate electrode 9, the region where electrons are present moves to the gate electrode 9 side, as shown in FIG. (In FIG. 6, a region where electrons exist in the undoped Ga _{1-u InuN} layer 5 is stippled). Was calculated when W = a 10 nm, an undoped Ga _1-u In u N layer 5 and the Al _v Ga _1-v N layer 8
Average position of two-dimensional electron (2D
The center of the EG) is shown in FIG. In FIG. 8, z _av is the average position of all two-dimensional electrons (two-dimensional electrons are undoped Ga
_1-u In _u N layer 5 and is present throughout both the n-type Al _z Ga _1-z N layer 3, 2 when considering its both
Average position of two-dimensional electrons), z _chav is undoped Ga _1-u I
This is the average position of the two-dimensional electrons obtained by considering only the electrons existing in the n _u N layer 5. In this example, the average position of the electron in the region of A, B in FIG. 6, an undoped Al _z G
is approximately the distance d1 = 4 nm of at the interface between a _1-z N layer 3 and the undoped Ga _1-u In u N layer 5. When a gate voltage V _gs is applied to the gate electrode 9, the average position of the electrons is determined by the Al _v Ga ₁ -vN layer 8 and the undoped Ga _{1 -u} In
_It can be seen that the depth changes from the interface with the uN layer 5 to a depth of d2 = 3 nm. Therefore, considering that the electrons immediately below the gate electrode 9 and the regions A and B need to overlap (the parasitic resistance increases if the overlap is not sufficient), W
It is understood that it is desirable that the thickness be 10 nm or less.

Next, an n-type Al _z Ga as an electron supply layer
_The conditions that the _1-z N layer 3 should satisfy will be discussed.

The gate electrode 9 and the source electrode 1 in FIG.
0, or between the gate electrode 9 and the drain electrode 11, that is, in order to reduce the parasitic resistance generated in the regions A and B,
N-type Al _z Ga _1-z N layer 3 as an electron supply layer must be able to supply sufficient electrons to the undoped Ga _1-u In _u N layer 5 as an electron transit layer. However, if too much doped n-type Al _z Ga _1-z N layer 3, reduces the bottom of the conduction band (E _c), the Fermi level E _F is or close to the conduction band, so as to overlap or Become. Then, since both G _m and f _T decrease, n
There is an upper limit on the impurity concentration of the type Al _z Ga _{1 -zN} layer 3.

Specifically, the gate electrode 9 and the source electrode 1
0 and the parasitic resistance generated between the gate electrode 9 and the drain electrode 11 is 500Ω (W = 50 μm,
(L _sg = 0.5 μm) or less, the n-type Al _z G
The product of the impurity concentration × thickness of the a _{1 -z} N layer 3 is 5 × 10 ¹⁸ [cm
^-3 ] [nm] or more. On the other hand, n-type Al _z
The potential drop of the Ga ₁ -zN layer 3 is reduced by 0.9 V (however, n-type A
In order to make the thickness W of the l _z Ga _{1 -z} N layer 3 1 nm or less), the product of the impurity concentration × thickness of the n-type Al _z Ga _{1 -z} N layer 3 is 1 × 10 ²¹ [ cm ⁻³ ] [nm] or less.

The parasitic resistance generated between the gate electrode 9 and the source electrode 10 and between the gate electrode 9 and the drain electrode 11 is 50Ω (W = 50 μm, L _sg =
0.5 μm) or less, the n-type Al _z Ga _1-z
The product of the impurity concentration × the thickness of the N layer 3 is 5 × 10 ¹⁹ [cm ⁻³ ]
[Nm] or more. On the other hand, n-type Al _z Ga
0.5-V potential drop of the _1-z N layer 3 (however, n-type Al _z
In order to reduce the thickness W of the Ga _{1 -zN} layer 3 to 1 nm or less, the impurity concentration of the n-type Al _z Ga _{1 -zN} layer 3
The thickness product needs to be 5 × 10 ²⁰ [cm ⁻³ ] [nm] or less.

As described above, according to this embodiment,
Optimized structures, i.e., Al as an undoped Ga _1-u In _u N layer 5 and the barrier layer as the electron transit layer
_y by n-type Al _z Ga _1-z N layer 3 is provided as an electron supply layer between the Ga _1-y N layer 2, and Al _v Ga _1-v N layer 8 serving as a gate insulating film electronic by supplying layer is not provided, Al _v Ga _1-v N layer 8 and the undoped Ga _1-u in _u N layer between the undoped Ga _1-u in _u N layer 5 as the electron transit layer as in the case of the electron supply layer is provided also between the 5, out of the charge for the electron supply layer when the gate voltage V _gs becomes larger increases, an undoped Ga _1-u in _u N layer 5 can be prevented from decreasing, and G
Deterioration of _m and f _T can be prevented. Further, by the electron supply layer of the gate electrode 9 side is not provided, the distance between the gate electrode 9 and the undoped Ga _1-u In _u N layer 5 is close, the overall high G _m Obtainable. And undoped Ga _1-u In _u N
The thickness W of the layer 5 is 1 nm or more and 15 nm or less, preferably 2 n
m to 10 nm, the gate voltage V _gs
, The decrease in G _m can be greatly reduced, and the parasitic resistance (channel resistance) can be kept low. Also, n-type Al _z Ga as an electron supply layer
_The product of the impurity concentration × thickness of the _1-z N layer 3 is 5 × 10 ¹⁸ [c
m ⁻³ ] [nm] to 1 × 10 ²¹ [cm ⁻³ ] [nm], preferably 5 × 10 ¹⁹ [cm ⁻³ ] [nm] to 5 ×
By setting it to 10 ²⁰ [cm ⁻³ ] [nm] or less, G _m
And f _T can be increased. From the above, high G
_m, it is possible to realize a high performance GaN-based FET of the high-frequency high-power high f _T.

As described above, one embodiment of the present invention has been specifically described. However, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the numerical values and structures described in the above embodiment are merely examples, and different numerical values and structures may be used as needed.

In one embodiment, the electronic
Undoped Ga which is a layer containing In as a running layer_1-uI
n_uSince the N layer 5 is used, the undoped Ga_1-u
In _uIn in the N layer 5 is Al as a gate insulating film._vG
a_1-vThese Al are diffused into the N layer 8 and these Al_vGa_1-vN layer 8
And undoped Ga_1-uIn_uDeterioration of both of the N layers 5
To prevent this from happening.
And Al_vGa_1-vN layer 8 and undoped Ga_1-uIn_u
A thin layer made of, for example, undoped GaN
A buffer layer may be provided.

Furthermore, in some cases, as an electron transit layer may be used Ga _1-u In u N layer doped instead of the undoped Ga _1-u In u N layer 5.

[0033]

As described above, according to the heterojunction field effect transistor of the present invention, the original performance of a device using a GaN-based semiconductor can be exhibited by optimizing the structure, and higher performance can be achieved. Can be planned.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a GaN-based FET studied by the present inventors.

FIG. 2 G obtained by computer simulation
It is a schematic diagram showing a G _m -V _gs characteristics of aN based FET.

FIG. 3 G obtained by computer simulation
It is a schematic diagram showing an f _T -V _gs characteristics of aN based FET.

FIG. 4 is a schematic diagram showing a conduction band in the GaN-based FET shown in FIG.

FIG. 5 is a schematic diagram showing a GaN-based FET according to an embodiment of the present invention.

FIG. 6 is a sectional view showing a GaN-based FET according to an embodiment of the present invention.

FIG. 7 is a schematic diagram showing a conduction band in the GaN-based FET shown in FIG.

FIG. 8 is a schematic diagram illustrating V _gs dependence of the center of a two-dimensional electron gas in a GaN-based FET according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a conventional GaN-based HEMT.

[Explanation of symbols]

_{1 ··· Al x Ga 1-x} N _{layer, 2 ··· Al y Ga 1-} y
N layer, 3, 7,... N-type Al _z Ga _{1 -z} N layer, 4, 6,.
· Undoped Al _z Ga _1-z N layer, 5 ... undoped Ga _1-u In u N _{layer, 8 ··· Al v Ga 1-} v N layer,
9 ... gate electrode, 10 ... source electrode, 11 ...
・ Drain electrode

Claims (5)

[Claims] An Al _x Ga ₁ -xN (where 1 ≧ x ≧ 1)
0) and the base layer consisting of, on the base layer Al _y Ga _1-y N (provided that, 1 ≧ y> 0)
And Al _z Ga _1-z N on the barrier layer (where 1 ≧ z ≧
0), and Ga _{1 -uInuN} (where 1 ≧ u) on the electron supply layer.
≧ 0) and an Al _v Ga _1-v N (1 ≧ v) on the electron transit layer
A hetero-junction field-effect transistor comprising: 2. The product of the impurity concentration and the thickness of the electron supply layer is 5 × 10 ¹⁸ [cm ⁻³ ] [nm] or more and 1 × 10 ²¹ [c].
2. The heterojunction field-effect transistor according to claim 1, wherein the value is not more than m ^-3 ] [nm]. 3. The product of the impurity concentration and the thickness of the electron supply layer is 5 × 10 ¹⁹ [cm ⁻³ ] [nm] or more and 5 × 10 ²⁰ [c].
2. The heterojunction field-effect transistor according to claim 1, wherein the value is not more than m ^-3 ] [nm]. 4. The thickness of the electron transit layer is 1 nm or more and 15 nm or more.
2. The heterojunction field effect transistor according to claim 1, wherein the thickness is not more than nm. 5. The method according to claim 1, wherein the thickness of the electron transit layer is from 2 nm to 10 nm.
2. The heterojunction field effect transistor according to claim 1, wherein the thickness is not more than nm.