KR100985470B1 - High-electron-mobility transistor and manufacturing method for the same - Google Patents

Abstract

The present invention discloses a high electron mobility transistor and a method of manufacturing the same. The present invention forms a gate electrode layer of an AlGaN / GaN high electron mobility transistor in a stepped structure that is not in contact with each other, thereby suppressing concentration of an electric field generated between the gate electrode and the drain electrode, thereby reducing the peak value of the electric field, and performing local avalanche. By suppressing the breakdown, the increase in the drain current is reduced, thereby exhibiting a linear drain current characteristic. In addition, by controlling the input voltage applied to the stepped gate electrode, the linearity, high output, and high frequency characteristics of the device can be improved to realize low power consumption and low cost, and also AlGaN / GaN high mobility suitable for application to an RF device. There is an effect to provide a transistor.

Description

High-electron-mobility transistor and manufacturing method for the same

The present invention relates to a transistor and a method of manufacturing the same, and more particularly to a high electron mobility transistor and a method of manufacturing the same.

In general, when doping a material with a large bandgap when contacting two materials with different bandgaps in a semiconductor material, a small bandgap material has a relatively high electron affinity, so the doped bandgap is not doped from a large material. Free electrons move to a material with a small band gap, and a high electron mobility two-dimensional electron gas layer is formed below about 100Å at the interface, and a high electron mobility transistor is fabricated using the electron gas layer. It is a well known fact.

In general, a high electron mobility transistor (HEMT) is a conduction band generated by hetero-junction of two kinds of materials having a large difference in bandgap energy among III-V compound semiconductors. It is an electronic device using a 2-dimensional electron gas (2-DEG) as a channel due to discontinuity of.

High power, high frequency, and high temperature are required for the implementation of HEMT, but existing III-V compound semiconductors are limited in the aforementioned characteristics due to problems such as discontinuity of small conduction band and low breakdown voltage. Have

In order to solve this problem, a nitride (GaN) based HEMT based on excellent material properties such as large bandgap energy, high thermal conductivity and high breakdown voltage has recently been introduced. It is attracting attention as an electronic device of (radio frequency, RF).

However, when implementing AlGaN / GaN HEMT, a single gate electrode is mainly used as a gate electrode structure that controls the characteristics of the device, and this electrode structure concentrates an electric field between the gate electrode and the drain electrode, so that the electric field is concentrated at the edge of the gate electrode. This results in avalanche breakdown, which results in a decrease in breakdown voltage and an increase in nonlinear drain current.

In addition, the breakdown phenomenon in the gate electrode region increases leakage current to the gate electrode and decreases the gain of the device, thereby increasing power consumption and capacitance between the gate electrode and the drain electrode. Increasingly, there is a problem of limiting the high power and high frequency characteristics of the high electron mobility transistor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high electron mobility transistor having high output and high frequency characteristics by preventing avalanche breakdown due to concentration of an electric field at the edge of a gate electrode.

The high electron mobility transistor of the present invention for achieving the above technical problem, a semiconductor substrate; A high resistance layer formed on the semiconductor substrate; A barrier layer formed on the high resistance layer; And a plurality of gate electrode layers formed on the barrier layer.

In addition, the plurality of gate electrode layers described above may be spaced apart from each other so as not to contact each other.

In addition, the plurality of gate electrode layers described above may be formed to be stepped with each other.

In addition, the plurality of gate electrode layers described above may be formed to have a progressively upward or downward stepped structure without being in contact with each other.

In addition, the high electron mobility transistor described above may further include a source electrode layer and a drain electrode layer formed on the high resistance layer while being in contact with the barrier layer.

In addition, the plurality of electrode layers described above may be located directly above the barrier layer.

In addition, the high resistance layer described above may be formed of GaN.

In addition, the barrier layer described above may be formed of AlGaN.

In addition, the above-mentioned high electron mobility transistor may further include a buffer layer formed between the semiconductor substrate and the high resistance layer.

On the other hand, the high electron mobility transistor manufacturing method of the present invention for achieving the above technical problem, (a) forming a high resistance layer on a semiconductor substrate; (b) forming a barrier layer over the high resistance layer; And (c) forming a plurality of gate electrode layers over the barrier layer.

In addition, in step (c) described above, the plurality of gate electrode layers may be spaced apart from each other so as to be in contact with each other.

In addition, in the above-described step (c), the plurality of gate electrode layers may be formed to be stepped with each other.

In addition, in the above-described step (c), the plurality of gate electrode layers may be formed to have a gradually upward or downward stepped structure without being in contact with each other.

In addition, the step (b) described above, (b1) forming a barrier layer; And (b2) a portion of the barrier layer may be etched to expose the high resistance layer to form a source electrode layer and a drain electrode layer.

In addition, in the above-described step (c), the plurality of electrode layers may be formed to be located directly above the barrier layer.

In addition, in step (b) described above, the high resistance layer may be formed of GaN.

In addition, in step (c) described above, the barrier layer may be formed of AlGaN.

In addition, in the above-described step (a), the buffer layer may be formed on the semiconductor substrate and the high resistance layer may be formed on the buffer layer.

As described above, the present invention forms the gate electrode layer of the AlGaN / GaN high electron mobility transistor into a stepped structure that is not in contact with each other, thereby suppressing concentration of an electric field generated between the gate electrode and the drain electrode to reduce the peak value of the electric field. Therefore, it is possible to reduce the increase of the drain current by suppressing local avalanche breakdown, thereby exhibiting a linear drain current characteristic.

In addition, by controlling the input voltage applied to the stepped gate electrode, the linearity, high output, and high frequency characteristics of the device can be improved to realize low power consumption and low cost, and also AlGaN / GaN high mobility suitable for application to an RF device. There is an effect to provide a transistor.

Hereinafter, a high electron mobility transistor and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a view showing the structure of a high electron mobility transistor according to a preferred embodiment of the present invention. Referring to FIG. 1, a high electron mobility transistor (hereinafter, abbreviated as “HEMT”) of the present invention is a semiconductor substrate implemented as a silicon substrate, a sapphire (Al ₂ O ₃ ) substrate, or a silicon carbide (SiC) substrate ( A metal-nitride based buffer layer 200, such as AlN, ZrN, TiN, or HfN, is formed on 100, and a high resistance layer 300, which is a GaN layer doped at a concentration of 1 × 10 ¹⁵ / cm, is formed on the buffer layer 200. .

On the other hand, a barrier layer 400 having a wider band gap than the high resistance layer 300 is formed on the high resistance layer 300, and source and drain electrode layers 510 and drain electrode layers are formed on both sides of the barrier layer 400. 520 are formed, respectively. Barrier layer 400 is preferably implemented with an undoped AlGaN layer containing about 30% Al.

On the other hand, a plurality of gate electrode layers on the barrier layer 400 is formed stepwise so as not to overlap each other.

In detail, the first gate electrode layer 650 is formed on the barrier layer 400, and the source electrode layer 510 and the drain electrode layer 520 are formed on the barrier layer 400 on which the first gate electrode layer 650 is not formed. The first insulating layer 600 is formed thereon.

In addition, a second gate electrode layer 750 is formed on the first insulating layer 600 formed on the barrier layer 400 so as not to overlap the first gate electrode layer 650, and the second gate electrode layer 750 is formed around the second gate electrode layer 750. The insulating layer 700 is formed.

In addition, a third gate electrode layer 850 is formed on the first insulating layer 600 formed on the barrier layer 400 and the second insulating layer 700 formed on the first insulating layer 600 as an upper region of the barrier layer 400. The third insulating layer 800 is formed to not overlap the second gate electrode layer 750, and the fourth insulating layer 900 is formed on the third gate electrode layer 850 and the third insulating layer 800. Is formed.

The gate electrode structure formed in the above-described high electron mobility transistor of the present invention is characterized in that the plurality of gate electrode layers are positioned directly above the barrier layer without being in contact with each other, and in particular, the plurality of gate electrode layers are gradually upward or downward. It is characterized by being formed in a downward stepped structure. Hereinafter, the structure of the gate electrode layers will be abbreviated as a stepped gate electrode structure.

In addition, when a gate voltage is applied to the plurality of gate electrode layers of the present invention, a two-dimensional electron gas layer (2-DEG layer) 310 is formed at a depth of about 10 nm from the boundary between the barrier layer and the high resistance layer into the high resistance layer. do.

2A to 2S illustrate a method of manufacturing a high electron mobility transistor according to an exemplary embodiment of the present invention. A method of manufacturing a high electron mobility transistor according to a preferred embodiment of the present invention will be described with reference to FIGS. 2A to 2S.

First, referring to FIG. 2A, a metal-nitride-based buffer layer 200 such as AlN, ZrN, TiN, or HfN may be formed on a semiconductor substrate formed of a silicon substrate, a sapphire (Al ₂ O ₃ ) substrate, or a silicon carbide (SiC) substrate. Is formed to a thickness of about 25 nm using a sputtering method, atomic layer deposition (ALD) method, or chemical-vapor deposition (CVD) method.

Thereafter, as shown in FIG. 2B, GaN doped on the buffer layer 200 at a concentration of 1 × 10 ¹⁵ / cm using a metal-organic chemical vapor deposition (MOCVD) method or a molecular-beam epitaxy (MBE) method. The high resistance layer 300 as a layer is formed to a thickness of 1.5 μm to 2 μm.

After the high resistance layer 300 is formed, an Al _0.3 Ga _0.7 N layer, which is an undoped barrier layer 400 containing 30% of aluminum (Al), as shown in FIG. 2C, is about 25 nm to 30 nm thick. The furnace is formed on the high resistance layer 300 by using a metal-organic chemical vapor deposition (MOCVD) method or a molecular-beam epitaxy (MBE) method. At this time, the doping concentration of the Al _0.3 Ga _0.7 N layer is preferably about 1 × 10 ¹² / cm or less.

Thereafter, as shown in FIG. 2D, a portion of the barrier layer 400 is etched and removed to form the source electrode layer 510 and the drain electrode layer 520. According to a preferred embodiment of the present invention, after ICP / RIE dry etching of the barrier layer 400 using BCl ₃ / Cl ₂ mixed gas (37.5: 7.5 ratio), rinsing is performed using HCl (hydrochloric acid) solution. . At this time, the etching thickness is preferably about 30 nm.

After the etching is completed, as shown in FIG. 2E, the e-beam evaporation is performed on the etched region in the order of Ti (300Å) / Al (1000Å) / Ni (300Å) / Au (1000Å). The source and drain electrode layers 520 are formed. After performing the deposition process, it is preferable to perform a rapid thermal annealing (RTA) process at about 900 ° C. for 30 seconds in a nitrogen atmosphere (N ₂ ) to obtain excellent ohmic characteristics.

Thereafter, as shown in FIG. 2F, the first insulating layer is disposed on the barrier layer 400, the source electrode layer 510, and the drain electrode layer 520 for surface leakage current and surface protection of the HEMT element on which the source and drain electrodes are formed. In order to form 600 to 200 nm thickness using an ALD (atomic layer deposition) method, and to form the first gate electrode layer 650 on the barrier layer 400, as shown in FIG. 2G, the first insulating layer After etching a portion of the 600, as shown in FIG. 2H, the first gate electrode layer 650 is formed in the etching region.

According to a preferred embodiment of the present invention, in order to form the first gate electrode layer 650, the first insulating layer 600 formed of Si ₃ N ₄ is mixed with an O ₂ / SF ₆ mixed gas at a ratio of 5:45 to ICP. / RIE dry etching and then rinsed with BOE (buffered oxide etchant, 5: 1 dilute hydrofluoric acid) solution for 1 minute, Ni (500Å) / Au (1500Å) using the electron beam evaporation method of the first gate electrode layer 650 To form.

The position of the first gate electrode layer 650 of the preferred embodiment of the present invention is preferably spaced about 1 μm from the source electrode layer 510, and the width of the first gate electrode layer 650 is preferably 500 nm.

Meanwhile, after the first insulating layer 600 and the first gate electrode layer 650 are formed, the second insulating layer 700 is formed thereon with a thickness of 200 nm in the same manner as that of the first insulating layer 600. 2I) and after etching a portion of the second insulating layer 700 in the same manner as described above with reference to FIG. 2G to form the second gate electrode layer 750 (see FIG. 2J), The second gate electrode layer 750 is formed in the same manner as described above with reference to FIG. 2H (see FIG. 2K).

The second gate electrode layer 750 formed in the above-described process is positioned in an upper region of the barrier layer 400 and is formed so as not to overlap the first gate electrode layer 650. In a preferred embodiment of the present invention, the second gate electrode layer 750 is preferably formed with a width of 500 nm at a position spaced about 100 nm from the first gate electrode layer 650.

Meanwhile, after the second insulating layer 700 and the second gate electrode layer 750 are formed, the third insulating layer 800 and the first insulating layer 600 and the second insulating layer 700 have a thickness of 200 nm thereon. In order to form the third gate electrode layer 850, and to form the third gate electrode layer 850 in the same manner as described above with reference to FIGS. 2G and 2J. After etching a portion (see FIG. 2M), the third gate electrode layer 850 is formed in the same manner as described above with reference to FIGS. 2H and 2K (see FIG. 2N).

The third gate electrode layer 850 formed in the above process is positioned in an upper region of the barrier layer 400 and is formed so as not to overlap the first gate electrode layer 650 and the second gate electrode layer 750. In a preferred embodiment of the present invention, the third gate electrode layer 850 is preferably formed with a width of 500 nm at a position spaced about 100 nm from the second gate electrode layer 750.

After the third gate electrode layer 850 and the third insulating layer 800 are formed, as shown in FIG. 2O, the fourth insulating layer (top) of the third gate electrode layer 850 and the third insulating layer 800 is formed. 900 is formed using ALD (atomic layer deposition) method. In this case, the fourth insulating layer 900 to be deposited is preferably formed with the same material as the first insulating layer 600 to the third insulating layer 800 to a thickness of about 1 μm.

After the fourth insulating layer 900 is formed, as described below, a via hole is formed through the insulating layer to expose the respective gate electrode layers, and a gate electrode for applying a voltage to the gate electrode layers therein. Form the controls.

Referring to FIGS. 2P through 2S, first, the first gate electrode controller 1000 and the first gate electrode layer 650 are disposed in a region of the fourth insulating layer 900 corresponding to the first gate electrode layer 650. In order to form the via-holes 920, the metal mask 910 is patterned for etching of titanium (Ti) using an e-beam evaporation method (see FIG. 2P).

Thereafter, as shown in FIG. 2Q, the O ₂ / SF ₆ mixed gas is mixed at a ratio of 5:45 from the fourth insulating layer 900 to the second insulating layer 700 at a ratio of 5:45 to form via-holes. After performing RIE dry etching, rinse for 1 minute using BOE (buffered oxide etchant, 5: 1 dilute hydrofluoric acid) solution. Thereafter, Au 930 is seeded using a sputtering method to improve metal adhesion of the resulting via-hole, and the Ti metal mask is etched and removed using a 5: 1 BOE solution. At this time, the thickness of the seeded Au is about 100 kPa.

Thereafter, as shown in FIG. 2R, the via-holes are patterned with photoresist (PR, not shown), followed by a first gate control electrode using an Au-plating method. Form a portion 1010. At this time, the thickness of the Au electrode controller to be formed is preferably about 1 μm.

In addition, as shown in FIG. 2S, the second gate control electrode unit 1020 and the third gate electrode layer with respect to the second gate electrode layer 750 in the same manner as the first gate control electrode unit 1010 is formed. A third gate control electrode portion 1030 to 850 is sequentially formed to complete the high electron mobility transistor.

So far, a high electron mobility transistor and a method of manufacturing the same have been described. In the above-described embodiment, various modifications may be derived within the scope of the technical idea of the present invention. For example, in the above-described preferred embodiment of the present invention, the first insulating layer 600 to the fourth insulating layer 900 are described as being formed of the same material, but may be formed of different materials. In addition, different methods may be applied to the method of etching the insulating layers or the method of forming the via holes.

3 to 6 are diagrams comparing the performance of the high electron mobility transistor according to the present invention with the performance of the high electron mobility transistor having a conventional single electrode structure.

First, FIG. 3 is a diagram comparing electric field distribution and current-flow ratio of the high electron mobility transistor of the conventional single gate electrode structure and the high electron mobility transistor of the present invention. .

As shown in FIG. 3, the electric field at the edge of the gate electrode generated in the single gate electrode structure has a relatively high electric field dispersion degree of about 7 × 10 ⁵ V / cm, whereas in the stepped gate electrode structure of the present invention. By showing a low electric field dispersion degree of about 2.5 × 10 ⁵ V / cm, the edge breakdown of the gate electrode can be effectively suppressed. In addition, considering the current flow rate, the single gate electrode structure shows a sharp increase in current flow due to additional carriers caused by the breakdown phenomenon in the vicinity of the gate electrode, whereas in the stepped gate electrode structure, the electric field is effectively dispersed. As a result, the sudden increase in current flow is also suppressed due to the suppression of yield.

Figure 4 is a (a) I _D- V _D characteristics comparison, (b) I _D- V _G characteristics comparison of the high electron mobility transistor of the conventional single gate electrode structure and the high electron mobility transistor of the present invention, (c) Figures show a comparison of substrate leakage current and (d) comparison of temperature characteristics in 2-DEG.

As in the drain current-drain voltage characteristic (I _D -V _D ) shown in FIG. 4A, the DC characteristic in the conventional structure is pinched by the gate voltage due to the additional carriers generated by the above-described breakdown phenomenon. While the drain current increases abruptly after the pinch-off point, in the case of the present invention, the DC current shows a slight decrease in the drain current due to the enlarged gate area, but the abrupt drain current occurring after the pinch-off point. The increase of shows controlled stable drain current characteristic.

The drain current-gate voltage (ID-VG) characteristics of FIG. 4 (b) show a gain (Gm) characteristic of about 10% increased in spite of the current characteristic of about 15% lower than that of the conventional structure. It can be seen that.

In addition, as shown in (c) and (d) of FIG. 4, in the case of leakage current to the substrate generated by the gate voltage and temperature change in the 2-DEG, the stairs proposed by the present invention compared to the conventional single gate structure. It can be seen that the substrate leakage current of the type stacked gate structure has improved characteristics reduced by about 50% when considering the gate voltage of 0 V and also relatively less thermal characteristics generated in the 2-DEG channel.

FIG. 5 is a diagram illustrating (a) C _gd characteristics comparison and (b) C _gs characteristics comparison of the high electron mobility transistor of the conventional single gate electrode structure and the high electron mobility transistor of the present invention, respectively.

As shown in FIG. 5, due to the structural characteristics of the stepped gate electrode, the capacitance value between the gate and drain electrodes and the capacitance value between the gate and source electrodes are increased by about two times or more, compared to the conventional structure. As a result, a stable DC characteristic is secured, and thus the overall G _m value increases.

FIG. 6 is a diagram comparing transducer power gain (G _T ) characteristics of the high electron mobility transistor of the conventional single gate electrode structure and the high electron mobility transistor of the present invention.

In the stepped gate electrode structure of the present invention, the cut-off frequency of the conventional single electrode structure tends to decrease by about 0.3 GHz while the transducer power gain, which is a power gain that can be secured through a single element, is about 3 dB. Shows increased high frequency characteristics with increasing degree.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

1 is a diagram showing the structure of a high electron mobility transistor according to a preferred embodiment of the present invention.

2A to 2S illustrate a method of manufacturing a high electron mobility transistor according to a preferred embodiment of the present invention.

3 is a diagram comparing electric field mobility and current flow of the high electron mobility transistor of the conventional single gate electrode structure and the high electron mobility transistor of the present invention.

4 is (a) I _D -V _D characteristics comparison, (b) I _D -V _G characteristics comparison of the high electron mobility transistor of the conventional single gate electrode structure and the high electron mobility transistor of the present invention, (c) Figures show a comparison of substrate leakage current and (d) comparison of temperature characteristics in 2-DEG.

Fig. 5 shows a high electron mobility transistor of a conventional single gate electrode structure and (a) C _gd of the high electron mobility transistor of the present invention. It is a figure which shows a characteristic comparison and (b) C _gs characteristic comparison, respectively.

FIG. 6 is a diagram comparing transducer power gain (G _T ) characteristics of the high electron mobility transistor of the conventional single gate electrode structure and the high electron mobility transistor of the present invention.

Claims (18)

delete delete delete Semiconductor substrates; A high resistance layer formed on the semiconductor substrate; A barrier layer formed on the high resistance layer; And A plurality of gate electrode layers formed on the barrier layer, And the plurality of gate electrode layers are formed to have a gradually upward or downward stepped structure without being in contact with each other. The method of claim 4, wherein And a source electrode layer and a drain electrode layer formed on the high resistance layer while being in contact with the barrier layer. The method according to claim 4 or 5, And said plurality of electrode layers are located directly above said barrier layer. The method according to claim 4 or 5, The high resistance layer is formed of GaN. The method according to claim 4 or 5, The barrier layer is formed of AlGaN. The method according to claim 4 or 5, And a buffer layer formed between the semiconductor substrate and the high resistance layer. delete delete delete (a) forming a high resistance layer on the semiconductor substrate; (b) forming a barrier layer on the high resistance layer; And (c) forming a plurality of gate electrode layers on the barrier layer, In the step (c) And the plurality of gate electrode layers are formed to have a gradually upward or downward stepped structure without being in contact with each other. The method of claim 13, wherein step (b) (b1) forming the barrier layer; And (b2) forming a source electrode layer and a drain electrode layer by etching a portion of the barrier layer to expose the high resistance layer. 15. The process according to claim 13 or 14, wherein in step (c) And the plurality of electrode layers are formed to be located directly above the barrier layer. 15. The process according to claim 13 or 14, wherein in step (b) The high resistance layer is GaN manufacturing method, characterized in that formed of GaN. 15. The process according to claim 13 or 14, wherein in step (c) And wherein said barrier layer is formed of AlGaN. The method according to claim 13 or 14, wherein in step (a) Forming a buffer layer on the semiconductor substrate and forming the high resistance layer on the buffer layer.

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