JP5740643B2 - Field effect transistor - Google Patents

Field effect transistor Download PDF

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JP5740643B2
JP5740643B2 JP2010212189A JP2010212189A JP5740643B2 JP 5740643 B2 JP5740643 B2 JP 5740643B2 JP 2010212189 A JP2010212189 A JP 2010212189A JP 2010212189 A JP2010212189 A JP 2010212189A JP 5740643 B2 JP5740643 B2 JP 5740643B2
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source electrode
barrier
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JP2012069662A (en
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清水 三聡
三聡 清水
祐一 坂村
祐一 坂村
紘志 長南
紘志 長南
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国立研究開発法人産業技術総合研究所
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Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor that has a small operating current and operates with low power consumption.

  In a silicon LSI, power consumption increases as miniaturization progresses and the degree of integration increases. One of the major factors is an increase in leakage current. There are two increasing leakage currents. The first leakage current is a diffusion current from the drain to the source when the MOSFET is off. In the npn structure formed by the source, gate, and drain of a silicon MOSFET, the p region becomes shorter when miniaturized, and the diffusion current from the drain to the source at the time of off increases.

Another leakage current is called GIDL (Gate-Induced-Drain-Leakage Current). In order to shorten the gate length, it is necessary to simultaneously shorten the length of the depletion layer of the pn junction between the gate and the drain. However, if the depletion layer is short, the electric field strength in the depletion layer increases when a voltage is applied to the drain. Therefore, leakage occurs from the drain to the gate. In order to reduce any leakage current, there is a limit due to the use of a silicon material having a small band gap and the use of a pn junction.
In addition, when the gate length is shortened, a short channel effect or the like occurs as well as a leakage current. Further, when the doping concentration is increased according to the scaling law, there are problems such as a decrease in mobility at the MOS interface and a variation in threshold voltage.

Therefore, there is a method of suppressing leakage current by controlling the threshold voltage using the substrate side as a back gate, but the control becomes complicated. In addition, leakage current and a short channel effect can be suppressed by a method such as using a FIN gate structure or using an SOI substrate. Further, in the FIN type gate structure, since the doping concentration can be lowered, GIDL can be reduced. However, there is a limit even if a FIN type gate structure or an SOI substrate is used.
As another method for reducing power consumption, there is a method of operating at a subthreshold. In this method, since the operation is performed below the threshold voltage, the amount of current during operation can be reduced, and the power consumption can be reduced. However, as long as silicon with a small band gap is used, there is a limit to reducing the amount of current.

As another method, a structure called TBJ (tunneling barrier junction) MOSFET has been proposed. This is a structure having a thin dielectric film such as an oxide film at both ends of the channel. Thin barrier layers are formed between the source and gate and between the gate and drain. This has been proposed to prevent deterioration of characteristics due to the short channel effect. (See Non-Patent Document 1)
In this method, a barrier is formed using a thin silicon oxide film, and the current tunneling through the barrier is controlled by the gate. However, in reality, since the tunnel current depends on the film thickness and film quality of the silicon oxide film, it is difficult to control the tunnel current.

  There has also been proposed an element that uses a Schottky barrier in the source electrode portion to control the tunnel current of the barrier. However, in order to control the tunnel current from the source electrode to the conduction band of the semiconductor, a current starts to flow when the drain voltage is applied and the barrier becomes thin. Therefore, no current flows when the drain voltage is near zero, and a rising voltage like a diode is required. (See Non-Patent Document 2)

In addition, a method has been proposed in which a tunnel current from a valence band to a conduction band, which is also seen in the operation of a Zener diode, is controlled by a gate electrode to operate a transistor. Further, a method has been proposed in which a barrier is formed using a SiGe film at the pn junction and the device is operated at a lower current. (See Non-Patent Documents 3 and 4)
However, this has physical properties and process problems. Since silicon has a narrow band gap, there is a leakage current due to thermal electrons. In addition, the band structure is determined by doping. However, if the structure is miniaturized, a variation in doping becomes a problem, and the drain voltage may vary.

On the other hand, in recent years, research and development of power switching elements using wide gap semiconductors such as GaN, SiC, and diamond have been performed. Compared to a silicon power switching element, the resistance can be reduced while having the same breakdown voltage. Further, since it is chemically stable and stable at a high temperature, it can be used for manufacturing an element operating at a high temperature.
However, a technique for reducing the power consumption of the logic circuit has not been so much. Hereinafter, GaN, SiC, diamond and the like will be described.

Nitride semiconductors such as GaN, AlGaN, and InAlN are wurtzite crystals belonging to the hexagonal system, and are characterized by a high dielectric breakdown electric field and a high saturation drift velocity. In addition, the band gap can be changed by changing the composition of aluminum, gallium, indium, or the like, and a heterojunction can be formed.
A two-dimensional electron gas is formed at the AlGaN / GaN heterojunction. A positive charge is induced in the heterojunction by the piezo effect, and a quantum well for confining electrons is formed. An n-channel AlGaN / GaN heterojunction field effect transistor using this two-dimensional electron gas has been developed. In addition, FETs using a MOS structure for the gate are also being developed.
However, little development has been made on logic circuits using nitride semiconductor materials. This is because, even if a p-type layer is formed by doping, the activation rate of Mg, Zn, etc. is low, and the mobility of holes is low. Therefore, it is difficult to produce a p-type layer that can be used for an electronic device.

There is an example in which a p-type layer is formed in a heterojunction using the piezo effect to increase the breakdown voltage of an n-channel FET. (See Patent Document 1)
However, since a nitride semiconductor is likely to be n-type due to nitrogen depletion and the like, and a defect generated due to a difference in lattice constant exists at the heterojunction interface and supplies electrons, it is difficult to form a p-type layer.
In this method, the p-type layer is a layer for managing an electric field, and is not used as a channel.
For this reason, there is a proposal of an integrated circuit using Si transistors together. In this example, an AlGaN / GaN heterojunction field effect transistor and a Si pnp transistor are used. (See Non-Patent Document 5)

  As described above, in the nitride semiconductor material, there are few reports on the case where a proper hole channel is formed and the transistor operation is obtained. Therefore, there is no example of a transistor that can operate with low power consumption.

SiC has a crystal structure such as hexagonal 4H or 6H or cubic 3C, and has characteristics such as a high dielectric breakdown electric field and a high saturation drift velocity. Used in the manufacture of power transistors. Currently, n-type and p-type MOSFETs are being developed.
CMOS has been developed for logic circuits using SiC materials. This uses an npn transistor and an inverter composed of a pnp transistor. Except for the difference in material, the technique is almost the same as that used in conventional silicon. (See Non-Patent Document 6)

Diamond also has a large band gap and a high dielectric breakdown electric field. Diodes and FETs are being developed. There are reports of p-channel and n-channel FETs.
However, there is no example of an element for low power consumption operation using SiC or diamond.

JP 2007-134608 A

J. Appl. Phys., Vol. 42, pp. 1206-1211, 2003. Jpn.J.Appl.Phys., Vol.33, pp.612-618,1994. Jpn.J.Appl.Phys., Vol.31, pp.L455-L457,1992. IEEE Transactions on Electron Devices, VOL.56, NO.11, pp.2752-2761, 2009. Phys. Status Solidi C 6, No. 6, pp. 1361-1364, 2009. IEEE Transactions on Electron Devices, vol. 45, No. 1, pp. 45-53, 1998.

  An object of the present invention is to provide a field effect transistor that can be applied to a logic circuit that operates with low power consumption in consideration of the above-described problems of the prior art.

The above problem is solved by the following field effect transistor.
(1) has a barrier between the semiconductor conduction band source electrode and a source electrode is in contact, have a configuration in which the electrons flow through the barrier from the source electrode can be adjusted by the gate voltage,
In source part, it possesses a source electrode, between the channels responsible for electronic conduction, the contact area to adjust the height of the Schottky barrier,
An n- channel field effect transistor , wherein the Schottky barrier is adjusted to be low so that a drain current amount per 50 μm gate width is controlled to 30 μA or less when a gate voltage of 5 V is applied .
( 2 )
The n-channel field effect transistor according to ( 1 ), wherein the contact region in contact with the source electrode and the channel responsible for electron conduction are compound semiconductors having different band gaps.
( 3 )
The n-channel field effect transistor according to ( 1 ), wherein the contact region in contact with the source electrode is an InAlGaN layer, and the channel responsible for electron conduction is a GaN layer.
( 4 )
It characterized in that it has a barrier layer between the channel responsible for the semiconductor surface and electron conduction Gate unit (1) field effect transistors of the n-channel description.
( 5 )
The n-channel field effect transistor according to ( 4 ), wherein the barrier layer of the gate portion is a compound semiconductor having a band gap different from that of the channel responsible for electron conduction.
( 6 )
The n-channel field effect transistor according to ( 4 ), wherein the barrier layer of the gate portion is an InAlGaN layer, and the two-dimensional electron gas formed at the heterojunction interface between the barrier layer and the GaN layer is a channel.
( 7 )
It has a barrier between the source electrode and the valence band of the semiconductor with which the source electrode is in contact, and has a configuration in which holes flowing from the source electrode through the barrier can be adjusted by the gate voltage,
In source part, between a channel carrying a source electrode, a hole conducting, it has a contact area for adjusting the height of the Schottky barrier,
A p- channel field effect transistor characterized in that the Schottky barrier is adjusted to be low so that the drain current amount per 50 μm gate width is controlled to 30 μA or less when a gate voltage of 5 V is applied .
( 8 )
The p-channel field effect transistor according to ( 7 ), wherein the contact region in contact with the source electrode and the channel responsible for hole conduction are compound semiconductors having different band gaps.
( 9 )
The p-channel field effect transistor according to ( 7 ), wherein a barrier layer is provided between the semiconductor surface of the gate portion and the channel responsible for hole conduction.
(1 0 )
( 9 ) The p-channel field effect transistor according to ( 9 ), wherein the barrier layer of the gate portion is a compound semiconductor having a band gap different from that of the channel responsible for hole conduction.
(1 1 )
The p-channel field effect transistor according to ( 7 ), wherein the p-channel is formed of a nitride semiconductor, and the p-channel is formed by a negative charge generated in the heterojunction due to the piezoelectric effect.
(1 2 )
The p-channel field effect transistor according to ( 7 ), wherein the p-channel includes a GaN layer of an AlGaN / GaN / AlGaN double heterojunction.

  According to the present invention, there is provided a field effect transistor capable of operating with lower power consumption by using a source electrode with a barrier and controlling the operating current flowing by thermionic emission by the gate voltage, thereby reducing the operating current of the transistor. can get.

Field effect transistor having a Schottky barrier at the source electrode Field effect transistor having contact layer between source electrode and channel Field effect transistor having a barrier layer in the gate portion AlGaN / GaN heterojunction field effect transistor having Schottky barrier at source electrode Relationship between drain voltage and drain current obtained by numerical analysis Electron distribution in a channel obtained by numerical analysis. Fabricated field effect transistor structure Drain voltage vs. current characteristics of normally-off device Drain voltage-current characteristics of normally-on device Drain voltage-current characteristics measured by switching source and drain in normally-on device Characteristics of mutual conductance Characteristics of gate current Structure of p-channel field effect transistor Drain voltage-current characteristics of p-channel field effect transistors

(Example 1)
FIG. 1 shows an n-channel transistor having a Schottky barrier between the source electrode 1 and the channel layer 7. An insulating film 4 is provided between the gate electrode 2 and the channel layer 7 and has a MIS (Metal Insulator Semiconductor) structure. A MOS (Metal Oxide Semiconductor) structure may be used. The drain electrode 3 is a normal ohmic electrode.

  The transistor is constructed on the substrate 5, but a layer structure required by a transistor integration method, a manufacturing method, or the like is used between the channel layer 7 and the substrate 5. If necessary, the buffer layer 6 is inserted to improve crystallinity, or a p-type layer or a high resistance layer is inserted as the buffer layer 6 to electrically isolate the elements.

  When current flows in the forward direction in the Schottky diode, electrons flow through the Schottky barrier from the semiconductor side to the electrode side. On the other hand, in the Schottky barrier portion of the source electrode 1 in FIG. 1, electrons flow from the electrode side to the semiconductor side. This amount of current is controlled by the gate voltage.

  The supply of electrons from the source electrode 1 side is mainly due to thermionic emission. If the barrier is thin, there is also a tunnel current. When the barrier between the source electrode 1 and the channel layer 7 is high, the amount of current is small. When the channel layer 7 is doped n-type, a triangular barrier is formed in the Schottky barrier portion of the source electrode 1. By applying a gate voltage, the triangular barrier becomes thinner and current flows. When the gate voltage is high, a component due to the tunnel current is also generated. Thus, since the Schottky barrier exists, the amount of current from the source electrode 1 side is suppressed, and low power operation is possible.

  Further, since the supply of electrons from the source electrode 1 side is due to thermionic emission, the operating current rises from zero drain voltage. Therefore, it is possible to have the same operating characteristics as a normal transistor showing a linear region and a saturation region.

In a normal field effect transistor, the saturation current is controlled by the gate voltage. However, in the device of the present invention, the Schottky barrier of the source electrode portion is also a factor that determines the saturation current of the device.
The height of the Schottky barrier in the source electrode 1 is determined by the physical property value of the electrode material, that is, the work function. Therefore, it is a feature that variation in the amount of current for each element can be suppressed.

  Further, since a Schottky barrier is present at the source, even if the portion of the channel layer 7 immediately below the gate is an n-type semiconductor layer, the enhancement operation can be performed. The height of the Schottky barrier in the source electrode 1 is adjusted so that electrons can be supplied from the source side when the gate voltage is positive, and electrons supplied from the source side are reduced when the gate voltage is zero. That's fine.

  This is also an important feature and is not affected by doping distribution or non-uniformity when miniaturized. However, as a matter of course, the doping distribution of the channel layer 7 may be an npn structure like a normal transistor.

(Example 2)
On the other hand, since the height of the Schottky barrier of the source electrode 1 part is determined by the work function and electron affinity of the metal or semiconductor material, the selection range is narrowed depending on the usable material. In that case, as shown in FIG. 2, a contact region 8 is provided between the source electrode 1 and the channel 7 responsible for electron conduction. In the case of FIG. 1, the contact region 8 is formed in a layer shape. The height of the Schottky barrier can be adjusted by adjusting the doping concentration of the contact layer 8.

  When the Schottky barrier of the source electrode part is high and the amount of current is too small, the contact layer 8 may be a layer doped with n-type at a high concentration. Conversely, when the amount of current is too large, an n-type layer doped at a low concentration or a non-doped layer is used. In some cases, a thin p-type layer may be used as the contact layer.

  In the case of a compound semiconductor such as AlGaAs or AlGaN, the band gap can be changed by changing the composition. Therefore, a transistor having a desired current amount can be formed by changing the composition to change the height of the Schottky barrier in accordance with the work function of the source electrode metal.

  For example, InGaAs can be used as the channel layer 7 and InAlAs can be used as the contact layer 8 in the source portion. In this case, if the heterojunction of the channel layer 7 and the contact layer 8 is formed and two-dimensional electron gas is formed at the heterojunction interface, the mobility of the channel can be increased.

  In the case of a nitride semiconductor, the GaN layer may be used as the channel layer 7 and the contact layer 8 may be an InAlGaN layer. When the band gap of the contact layer 8 is increased, an AlGaN layer or the like is used as the contact layer 8. An InAlN layer may be used as the contact layer 8 in order to increase the band gap while keeping the lattice constant matched to the GaN layer channel layer 7. In this case, a heterojunction is also formed, and the mobility can be increased by using a two-dimensional electron gas formed at the heterojunction interface.

  Conversely, when it is desired to make the band gap of the contact layer 8 smaller than that of the GaN channel layer 7, an InGaN layer may be used as the contact layer 8. A method of continuously changing the band gap between the contact layer 8 and the channel layer 7 is also possible.

  The contact region 8 may be formed from two layers. For example, the height of the barrier with the source electrode 1 is adjusted using a layer having a small band gap such as an InGaN layer on the source electrode 1 side, and the AlGaN layer and the channel layer 7 are joined using an AlGaN layer on the channel side. Alternatively, a heterojunction may be formed, and a two-dimensional electron gas may be formed at the heterojunction interface and used as a channel.

An element having such a structure has four important characteristics.
The first characteristic is that in the element of the present invention, the source electrode portion has a low Schottky barrier and the amount of current is reduced. Therefore, the factor that determines the drain saturation current in the saturation region is different from that of a normal transistor.

  In a normal transistor, the channel of the gate portion is close to the gate electrode, and thus is not directly affected by the drain voltage. Now, when the gate voltage is equal to or higher than the threshold voltage, the drain current increases in the linear region as the drain voltage is increased. At that time, in the channel of the gate part, corresponding to the increase of the drain current, a difference occurs in the carrier density of the channel at the source end of the gate part and the carrier density of the channel at the drain end of the gate part, and diffusion current is generated. Thus, a current flows in the gate portion. When the drain voltage is further increased, the carrier density of the channel at the drain end of the gate portion decreases, which corresponds to an increase in drain current.

  However, when the drain voltage is increased and the carrier density of the channel at the drain end of the gate portion becomes almost zero, the carrier density of the channel at the source end of the gate portion and the carrier density of the channel at the drain end of the gate portion The limit that cannot be increased any more is reached. As a result, even if the drain voltage is increased beyond the voltage at this time, a depletion layer is generated in the drain direction from the drain end of the gate portion, and the drain current does not increase. This is the operation in the saturation region of a normal transistor. The value of the drain current in the saturation region depends only on the gate voltage.

  On the other hand, in the transistor of the present invention, there is a barrier in the source electrode portion, which is also a major factor determining the drain current. For this reason, when a drain voltage is applied, a voltage drop also occurs in the barrier portion of the source electrode portion.

  Therefore, the operation of the transistor of the present invention is considered when the gate voltage is equal to or higher than the threshold value. When the drain voltage is increased, a voltage drop occurs due to the barrier of the source electrode portion. That is, a voltage drop occurs near the source electrode of the channel between the gate and the source.

  As a result, the electron density in the channel of the gate portion is not determined by the voltage between the gate electrode and the source electrode. The electron density of the gate portion is determined by the potential difference between the potential of the channel that is on the gate side of the channel where the voltage drop in the vicinity of the source electrode is flat and the potential is flat.

  The potential of the channel in which this potential is flat is equal to the voltage drop due to the barrier of the source portion, and depends on the drain voltage, and increases as the drain voltage is increased. Therefore, when the drain voltage is increased, the electron density of the channel of the gate portion is decreased.

  Therefore, when the drain voltage increases, the electron density in the channel of the gate portion decreases and acts to suppress the drain current. As a result, drain current saturation is likely to occur. Therefore, there is a Schottky barrier in the source electrode portion, and therefore a transistor having a drain voltage / current characteristic having saturation characteristics can be manufactured as in a normal transistor even when the amount of current is small.

  The second characteristic is that the electron density in the channel of the gate portion may be small. Since the amount of current is small due to the barrier of the source electrode part, the diffusion current is also small in the gate part. That is, the carrier distribution in the channel of the gate portion is flatter than that in the case where the source electrode portion has no barrier. That is, since the difference in carrier density can be small, the electron density of the channel of the gate portion can be relatively lowered.

  The third characteristic is that the short channel effect is less likely to occur. This is because a voltage drop also occurs in the source electrode portion, so that the potential difference between the source side and the drain side of the gate portion is substantially reduced. Therefore, the short channel effect is less likely to occur in the gate portion. Therefore, the gate length can be further shortened.

The fourth characteristic is that it is not necessary to form a channel at the MOS interface of the gate portion. This is apparent from the fact that it is not necessary to increase the carrier density of the channel of the gate part, which is the second characteristic, and the short channel effect which is the third characteristic is difficult to occur. Therefore, a barrier layer having a doping concentration different from that of the channel layer is disposed between the semiconductor surface of the gate portion and the channel, so that an element that operates even when electrons do not flow through the MOS interface can be manufactured.
Therefore, when applied to a SiC material having a low mobility of carriers at the MOS interface, it is not affected by the low mobility of carriers at the MOS interface.

(Example 3)
FIG. 3 shows a transistor in which the channel of the gate portion is separated from the interface. In this structure, an i-layer or p-type layer is used as a barrier layer 9 between the gate electrode 2 and the channel layer 7 so that electrons do not flow on the semiconductor surface of the gate portion even when the transistor is on. . This eliminates the need to use a low mobility MOS interface as a channel. In addition, high-speed operation is possible while being normally off.

In particular, in the case of a material such as SiC, it is difficult in principle to form a high mobility MOS interface, and this is an effective method. As the wide gap semiconductor material, GaN, SiC, diamond, GaAs, or the like can be used.
In the case of III / V group compound semiconductor materials such as AlGaAs, InAlGaN, and InGaAs, it is possible to use a material having a different channel and band gap as a barrier in the gate portion.

For example, a GaN layer can be used as the channel layer 7 and an AlGaN layer can be used as the barrier layer 9. Alternatively, an InGaAs layer may be used as the channel layer 7 and an InAlAs layer may be used as the barrier layer 9.
Also in this case, the channel layer 7 and the barrier layer 9 can form a heterojunction to form a two-dimensional electron gas channel, thereby increasing the carrier mobility.

Example 4
Next, operational characteristics of an AlGaN / GaN heterojunction field effect transistor having a barrier in the source electrode portion, calculated using semiconductor device simulation, are shown.
FIG. 4 shows the structure. A non-doped GaN layer 16, a p-type GaN layer 17, a GaN channel layer 18, and an AlGaN barrier layer 19 are formed on the insulating substrate 15. The AlGaN barrier layer 19 functions both as a contact layer for the source electrode and as a barrier between the channel of the gate portion and the semiconductor surface layer.

  In this structure, an AlGaN / GaN heterojunction field effect transistor using a source electrode having a Schottky barrier was simulated. A synopsys T-CAD Sentaurus Device was used. In this calculation, the lengths in the channel direction of the source electrode 11, the gate electrode 12, and the drain electrode 13 were each 1 μm. The surface was covered with silicon nitride. The distance between the source electrode and the gate electrode and the distance between the gate electrode and the drain electrode were also set to 1 μm.

  The semiconductor semiconductor layer structure used in the calculation was such that the non-doped GaN layer 16 had a thickness of 0.7 μm, the p-type GaN layer 17 had a thickness of 0.3 μm, and the GaN channel layer 18 had a thickness of 10 nm. The thickness of the AlGaN barrier layer 19 was 30 nm.

A positive space charge is formed at the actual AlGaN / GaN heterojunction interface by the piezoelectric effect, and electrons are attracted to form a quantum well. As a result, a two-dimensional electron gas channel is formed on the GaN layer side of the heterointerface. However, it is difficult to include a quantum well in the simulation due to a problem of calculation time. Therefore, in the simulation, a channel layer having a thickness of 10 nm was assumed. The electron mobility in this channel layer was 1500 cm 2 / Vs. As positive space charges formed by the piezo effect, a charge amount of 3.5 × 10 12 cm −2 was set at the interface between the GaN channel layer 18 and the AlGaN barrier layer 19 in terms of the number of electrons.

Further, the AlGaN barrier layer 19 has a three-layer structure of a channel layer 18, a p-type layer 17, and a non-doped layer 16 toward the insulating substrate. This is because a leakage current is generated when the GaN layer adjacent to the channel layer 18 is non-doped. The p-type having a thickness of 0.3 μm is formed below the 10 nm thick channel layer 18 (insulating substrate side). There was a layer 17. The doping concentration of the p-type layer 17 was 3.75 × 10 14 cm −3 . Further, it is assumed that there is a non-doped layer 16 therebelow. The substrate 15 was a sapphire substrate having a thickness of 1 μm.
The drain electrode 13 is in ohmic contact with the AlGaN layer 19. The gap between the source electrode 11 and the conduction band of the AlGaN layer 19 was about 0.25 eV. The gap between the gate electrode 12 and the conduction band of the AlGaN layer 19 was about 1.95 eV.

FIG. 5 shows the calculation result of drain current versus drain-source voltage. The horizontal axis is the drain voltage, and the vertical axis is the drain current per 1 mm of gate width. The gate voltage is 0V to -4V. The threshold voltage is about -2V. The drain current starts to flow from the drain voltage of 0V. It can be seen that the transistor operates in this way. The amount of current is about 400 μA / mm when the gate voltage is 0V.
In a normal device, since it is 300-500 mA / mm or more, it turns out that the electric current amount is restrict | limited to about 1/1000.

  Further, as shown in FIG. 5, it can be seen that the drain current is saturated in the drain current versus the drain-source voltage. Therefore, FIG. 6 shows the results of examining the distribution of electrons in the channel from the source portion toward the drain portion.

  This shows the carrier density at the interface between the GaN channel layer and the AlGaN barrier layer when the drain-source voltage is changed to 0V, 2V, and 4V when the gate voltage is 0V. The carrier density is indicated by a value per volume. The abscissa represents the distance along the channel, where −1 μm to 0 μm is the part with the source electrode, 1 μm to 2 μm is the part with the gate electrode, and 3 μm to 4 μm is the part with the drain electrode. .

  From this figure, it can be seen that also in the source electrode portion, the carrier density decreases when the drain voltage is increased. When the drain voltage is 4V with respect to the drain voltage being 0V, the carrier density of the source electrode portion is reduced to about 25%. Therefore, it can be seen that when the drain voltage is increased, the electric field strength also increases at the source portion, causing a voltage drop.

  Also from this figure, it can be seen that the carrier density in the source electrode portion is uniformly reduced. From this, it can be seen that when the drain voltage is increased, an electric field is uniformly applied to the barrier of the source portion. In this way, if a channel is formed using a heterojunction in the source part, the distance between the channel and the source electrode is made uniform, and an electric field is uniformly applied to the barrier between the channel and the source electrode, current can be applied in device design. This makes it easy to control the amount, which is a practically important feature.

  Further, as can be seen from FIG. 6, it can be seen that also in the gate electrode portion, when the drain voltage is increased, the carrier density decreases. It decreases almost uniformly along the gate electrode. This is largely different from the decrease in carrier density only at the drain end of the gate in a normal transistor. It can also be seen that the short channel effect hardly occurs because the carrier density is almost uniform along the gate electrode. This point is also different from a normal transistor.

  In the region between the source and the gate, the carrier density does not change. Therefore, the voltage is flat in this region. The voltage at this portion is a value corresponding to the voltage drop at the source electrode portion. The electric field applied to the channel of the gate portion is determined by the difference between the voltage of the gate electrode and the potential of the region where the voltage between the source and the gate is flat.

  From this, it is considered that when the drain voltage increases, the carrier density of the entire channel in the gate portion decreases and the resistance increases. Therefore, even if it considers from this calculation result, in the transistor of this invention, when a drain voltage increases, it turns out that the gate is functioning so that a drain current may be suppressed. That is, it functions so as to have operating characteristics having a saturation region.

(Example 5)
FIG. 7 shows an element structure of a transistor using a two-dimensional electron gas formed in an actually produced AlGaN / GaN heterojunction as a channel. It grows on the Si substrate 25 by using a metal organic chemical vapor deposition method (MOCVD method). There is a great difference in the thermal expansion coefficient between the Si substrate and the GaN layer. The thermal expansion coefficient of the GaN layer is larger. Therefore, a large strain is generated when the GaN crystal is grown at a high temperature by the MOCVD method and then cooled to room temperature. Therefore, after first growing on the Si substrate 25 a buffer layer 26 for relieving strain generated due to a difference in thermal expansion coefficient, such as an AlN layer and a GaN layer superlattice buffer, a GaN layer 27 and an AlGaN barrier layer 28, A GaN cap layer 29 is formed.

The growth conditions for GaN and AlGaN may be those normally used in the MOCVD method. As sources of Ga, Al, and nitrogen, trimethylgallium (TMG), trimethylaluminum (TMA), ammonia (NH 3 ), or the like is used. Usually, vacuum growth is used. The growth pressure is about 30 kPa. The growth temperature may be about 1100 ° C. As the substrate 10, a (111) silicon substrate is used. Immediately before the growth, the oxide film is removed using hydrofluoric acid, and the substrate surface is etched using sulfuric acid + hydrogen peroxide solution. Thereafter, a superlattice buffer layer and a desired AlGaN / GaN heterojunction structure are formed on the silicon substrate.

As for the gate portion, the GaN cap layer 29 and a part of the AlGaN barrier layer 28 are removed by etching so that the gate voltage acts on the channel efficiently. It is a recess gate.
Since the gate electrode 22 needs to be turned on by applying a positive voltage, an SiO 2 film 24 having a thickness of several nm to 20 nm is disposed between the gate electrode 22 and the AlGaN barrier layer 28. To do. This may be a MIS (Metal Insulator Semiconductor) structure.

  The GaN cap layer 29 functions as a contact layer for the source electrode 21. The height of the Schottky barrier is basically determined by the metal properties of the GaN cap layer 29 and the source electrode 21. In addition, a barrier corresponding to the difference in band gap also exists between the GaN layer cap layer 29 and the AlGaN barrier layer 28. Therefore, it is necessary to design in consideration of both the Schottky barrier between the source electrode 21 and the GaN cap layer 29 and the barrier between the GaN layer cap layer 29 and the AlGaN barrier layer 28.

  As a metal of the source electrode 21, a Schottky metal used for a gate or the like has a too high barrier height. Therefore, Ti / Al / Ni / Au or the like is used from the semiconductor side. This metal is usually used for ohmic electrodes, but forms a low Schottky barrier because the barrier layer is thick.

Further, defects such as threading transition exist in the AlGaN barrier layer 28 and the GaN cap layer 29, and the metal of the source electrode may come into contact with the heterojunction where the two-dimensional electron gas exists through the defect. Therefore, the thickness of the AlGaN layer 28 is preferably as thick as about 30 to 50 nm. Since the GaN cap layer 29 is for surface protection, it may be about 2 nm.
Further, since the lattice constants of the AlGaN layer 28 and the GaN layer 27 are different, when the AlGaN barrier layer 28 is thus thickened, the Al composition is preferably lowered to about 20%.

For comparison, a method for forming an ohmic contact in a normal transistor will be described. In order to obtain a proper ohmic contact with Ti / Al / Ni / Au in a normal transistor, the AlGaN barrier layer is removed to directly contact the AlGaN / GaN heterojunction interface. Alternatively, as another method, the metal of the source electrode is diffused through the threading transition existing in the AlGaN layer so that an ohmic can be obtained.
Therefore, even if an electrode having a Ti / Al / Ni / Au structure is formed on the surface side of the thick AlGaN layer 28 and the GaN cap layer 29 from the semiconductor side, ohmics cannot be obtained, and a Schottky barrier with a low barrier is formed.

  The drain electrode 23 may be a normal ohmic electrode. However, this time, it was fabricated in the same manner as the source electrode 21. In this case, a Schottky barrier also exists on the drain side, but there is no problem in operation because a current flows in the forward direction and the height of the barrier is low.

FIG. 8 shows the drain current-voltage characteristics of the actually produced device. The gate width is 50 μm and the gate length is 2 μm. The distance between the gate and the source is about 2 μm, and the distance between the gate and the drain is about 5 μm. The operating characteristics having a linear region and a saturation region are shown.
When the threshold voltage is 0 V, it can be seen that the drain current does not flow and the enhancement operation is performed. This is because in this element, the gate portion has a recess structure, and the carrier density in the channel immediately below the gate is depleted.

  It can be seen that the amount of current is about 1/1000 compared to a normal element. When an AlGaN / GaN heterojunction structure is formed, the sheet resistance is usually about 300 to 500Ω, and an element having a gate width of about 50 μm flows about 10 to 20 mA. However, as shown in FIG. 8, only about 8 μA flows in this element.

  Further, it can be seen that the amount of current in the saturation region is controlled by the gate voltage and is almost the same as that of a normal transistor except that the amount of current is small. It has a saturated region and a linear region, and operates in the same way as a normal transistor. The reason why the drain current is controlled according to the gate voltage in the saturation region is that when the drain voltage increases, the carrier density of the gate portion decreases and the gate portion functions to suppress the drain current. Thus, it can be seen that if the source electrode has a low Schottky barrier, the amount of current can be significantly reduced.

  9 and 10 show the results of measuring the same element with the source and gate interchanged. A normally-on operation is performed. This element is an element having substantially the same distance between the source and the gate and the distance between the gate and the drain. The important point is that this element exhibits almost the same characteristics even if the source electrode and the drain electrode are interchanged.

  This is because the electrodes used for the drain electrode and the source electrode both function properly as Schottky barriers, and when used as a high voltage side electrode, that is, when used as a drain electrode, This is because the current does not become a resistance component that reduces the current of the element.

  FIG. 11 shows the mutual conductance characteristics of this element. It turns out that the characteristic similar to a normal element is shown.

  FIG. 12 shows the characteristics of gate leakage current. Gate leakage is 50 pA or less, and gate leakage current can be reduced by using the MIS structure. Therefore, it can be seen that the drain current-voltage characteristics of FIGS.

  The current amount of this element is also characterized by being easily variable by changing the composition of the AlGaN barrier layer. Since the number of electrode materials that can form a small Schottky barrier at the source electrode is limited, there are limited options in the first place. However, when the barrier layer is a compound semiconductor such as AlGaN or AlGaAs, the height of the Schottky barrier can be controlled by changing the composition.

  In addition, since a heterojunction channel is used, high mobility and high speed operation can be expected. A HEMT having a normal structure using a two-dimensional electron gas formed in a heterojunction is always in an on state, and thus has a problem of high power consumption. However, in the element structure of the present invention, since the source electrode portion has a barrier, the enhancement operation is possible while the gate portion always has a two-dimensional electron gas. Therefore, a logic circuit capable of high speed operation with low power can be formed.

As described above, the case where the source electrode portion has the contact layer and the gate electrode portion has the barrier layer has been described. However, when there is a source electrode material capable of forming a low barrier between the channel layer and the semiconductor, the channel layer is directly formed. A source electrode may be formed.
Also in this case, even if the drain and source have the same electrode structure, the drain side is in the forward direction of the Schottky operation.

(Example 6)
In the case of the p-type channel, element design is possible as in the case of the n-type channel. In the source electrode portion, if there is a barrier between the valence band of the semiconductor layer in contact with the source electrode and the work function of the source electrode, the operation is similar to that of the n-channel.

  Similarly to the n-channel transistor, the amount of current can be adjusted by providing a contact region for adjusting the height of the barrier at the portion where the source electrode contacts. In the case of a compound semiconductor, the height of the barrier of the source electrode portion can be adjusted by adjusting the doping concentration or adjusting the composition and adjusting the band gap.

  Similarly to the n-channel transistor, the channel can be separated from the semiconductor surface by using a barrier layer in the gate portion. As a result, the mobility of holes as carriers can be increased. In addition, the influence of the surface state of the semiconductor can be suppressed.

(Example 7)
Next, a p-channel transistor using an AlGaN / GaN / AlGaN double heterostructure will be described.
GaN or AlGaN becomes a group III surface when grown on a c-plane sapphire substrate, a (111) silicon substrate, or the like. In other words, the Ga surface where the group III atom of the periodic table comes to the surface becomes the table. When growing in such a direction, when an AlGaN layer is grown on the GaN layer, a positive space charge is generated at the heterojunction interface due to the piezoelectric effect, and a two-dimensional electron gas is formed. This is used for a commonly found AlGaN / GaN heterojunction field effect transistor.

  On the other hand, when a GaN layer is grown on the AlGaN layer, a negative space charge is generated at the hetero interface due to the piezoelectric effect. Therefore, if this is used, a p-type channel can be formed. However, even if the GaN layer is grown on the AlGaN layer, the barrier layer does not exist in the gate portion. As a barrier layer, an AlGaN layer may be further disposed on the surface.

Therefore, when a double heterostructure is formed by laminating an Al x Ga 1-x N layer having an Al composition x, a GaN layer, and an Al y Ga 1-y N layer having an Al composition y from the substrate side, a GaN layer Negative charges and positive charges are generated at the lower interface and the upper interface. That is, a negative space charge is generated at the Al x Ga 1-x N / GaN hetero interface, and a positive space charge is generated at the GaN / Al y Ga 1-y N hetero interface. Therefore, the space charge in the GaN layer is the sum of these negative charges and positive charges.

  Since the amount of negative space charge and the amount of positive space charge depend on the composition x and y, it can be made n-type, p-type or insulator by adjusting x and y. If x <y, it becomes an n-type layer, and if x> y, it becomes a p-type layer. If x = y, it becomes an insulator in principle. However, since GaN tends to be n-type due to elimination of nitrogen atoms, it is necessary to consider the amount of compensation.

Therefore, in order to obtain a p -type , the composition of Al x Ga 1-x N as the lower barrier is set to about 27 to 30% (x = 0.27 to 0.3), and Al y Ga as the upper barrier is formed. The double heterostructure was formed by setting the composition of the 1-yN layer to 25% (y = 0.25).

  FIG. 13 shows the structure. A GaN layer 36 is first grown on the substrate 35 to improve crystallinity, and then an element structure is formed. From the substrate side, an AlGaN layer 38 with an Al composition of 27%, a GaN layer 39, and an AlGaN layer 40 with an Al composition of 25% were stacked to form a double heterostructure. Since the two-dimensional electron gas is formed when the AlGaN layer 38 having an Al composition of 27% is directly grown on the GaN layer 36, the composition change layer 37 is used. The composition change layer 37 is gradually changed in composition from GaN to AlGaN. When the composition is changed in this way, the n-type is formed. Therefore, Mg or the like used for growing a p-type semiconductor is doped to form an insulator. Thus, the resistance under the AlGaN layer 38 becomes electrically high.

  Using this double heterostructure, a p-channel device was prepared. A recess electrode structure was formed so that the source electrode 31 and the drain electrode 33 were in direct contact with the double heterostructure GaN, and an electrode was formed there. The electrode material was Ni / Au from the semiconductor side. In fact, under this condition, the source and drain electrodes do not form a proper ohmic electrode but have a barrier. The reason is that the GaN layer is a p-type layer having a low hole concentration, and in the case of a nitride semiconductor, it is difficult to form an ohmic electrode in the first place.

  In this structure, the source electrode is in contact with the channel at almost a point. Therefore, since an electric field is not applied non-uniformly to the barrier between the channel and the source electrode, there is a design advantage in controlling the amount of operating current.

As the gate metal 32, Ni / Au was also used. However, 100 nm of HfO 2 was used as an insulator as the insulating film 34 between the gate metal and the Al y Ga 1-y N layer on the surface.

  FIG. 14 shows the drain current versus the source / drain voltage of the actually fabricated device. When the gate voltage was lowered to the minus side, the drain current increased to the minus side, and the characteristics of the p-type channel were obtained.

Although the embodiments of the n-type channel and the p-type channel have been described above, when a wide gap semiconductor material is used, the Schottky barrier of the source electrode portion can be increased, so that an element with a very small amount of current becomes possible. In addition, since the wide gap semiconductor material has a high dielectric breakdown electric field, problems such as GIDL as seen in Si devices are less likely to occur, and miniaturization is possible than in Si devices.
In addition, if a wide gap semiconductor material is used, a logic circuit that operates at a high temperature can be formed.
In addition, since n-type channel and p-type channel elements can be formed in this way, logic circuits such as inverters can be formed by arranging them in a complementary manner.

  Since a logic circuit with a small amount of operating current can be formed, power consumption of an integrated circuit of a small electronic device can be reduced. When a wide gap semiconductor material is used, a logic circuit with low power consumption that can operate at high temperature can be formed.

1: source electrode 2: gate electrode 3: drain electrode 4: insulator 5: substrate 6: buffer layer 7: channel 8: contact layer 9: barrier layer 11: source electrode 12: gate electrode 13: drain electrode 15: substrate 16 : I-GaN layer 17: p-GaN layer 18: GaN channel layer 19: AlGaN barrier layer 21: source electrode 22: gate electrode 23: drain electrode 24: insulator 25: substrate 26: buffer layer 27: GaN channel layer 28 : AlGaN barrier layer 29: GaN layer cap layer 31: source electrode 32: gate electrode 33: drain electrode 34: insulator 35: substrate 36: GaN layer 37: composition change layer 38: AlGaN layer 39: GaN channel layer 40: AlGaN layer


Claims (12)

  1. Having a barrier between the source electrode and the conduction band of the semiconductor with which the source electrode is in contact, having a configuration in which electrons flowing from the source electrode through the barrier can be adjusted by the gate voltage;
    In the source portion, a contact region for adjusting the height of the Schottky barrier is provided between the source electrode and the channel responsible for electron conduction,
    Upon application of an Gate voltage 5V to the drain current per gate width 50μm is controlled below 30 .mu.A, the field effect transistor of n-channel in which the Schottky barrier is characterized in that the adjusted low .
  2. Channels responsible for contact areas and electronic conduction in contact with the source electrode, the field-effect transistor of the n-channel according to claim 1, characterized in that it is a different compound semiconductor bandgap.
  3. Contact region in contact with the source electrode is the InAlGaN layer, the field-effect transistor of the n-channel according to claim 1, wherein the channel responsible for the electronic conduction is GaN layer.
  4. Field effect transistor of n-channel according to claim 1, wherein a barrier layer between the channel responsible for the semiconductor surface and electron conduction Gate section.
  5. 5. The n-channel field effect transistor according to claim 4 , wherein the barrier layer of the gate portion is a compound semiconductor having a band gap different from that of the channel responsible for electron conduction.
  6. 5. The n-channel field effect transistor according to claim 4 , wherein the barrier layer of the gate portion is an InAlGaN layer, and the two-dimensional electron gas formed at the heterojunction interface between the barrier layer and the GaN layer is a channel.
  7. It has a barrier between the source electrode and the valence band of the semiconductor with which the source electrode is in contact, and has a configuration in which holes flowing from the source electrode through the barrier can be adjusted by the gate voltage,
    In the source portion, a contact region for adjusting the height of the Schottky barrier is provided between the source electrode and the channel responsible for hole conduction,
    Upon application of an Gate voltage -5V to drain current per gate width 50μm is controlled below 30 .mu.A, the field effect of the p-channel in which the Schottky barrier is characterized in that the adjusted low Transistor.
  8. 8. The p-channel field effect transistor according to claim 7 , wherein the contact region in contact with the source electrode and the channel responsible for hole conduction are compound semiconductors having different band gaps.
  9. 8. The p-channel field effect transistor according to claim 7 , further comprising a barrier layer between the semiconductor surface of the gate portion and the channel responsible for hole conduction.
  10. 10. The p-channel field effect transistor according to claim 9 , wherein the barrier layer of the gate portion is a compound semiconductor having a band gap different from that of the channel responsible for hole conduction.
  11. 8. The p-channel field effect transistor according to claim 7 , wherein the p-channel field effect transistor is formed of a nitride semiconductor, and a p-channel is formed by a negative charge generated in a heterojunction due to a piezo effect.
  12. 8. The p-channel field effect transistor according to claim 7 , comprising a GaN layer of an AlGaN / GaN / AlGaN double heterojunction as a p-channel.
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