JP2010212596A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor capable of preventing a current from leaking from a drain electrode. <P>SOLUTION: The field effect transistor has a WN/Al drain electrode Schottky-joined to a GaN channel layer 104 via an n<SP>+</SP>region (diffusion region) 112 below the drain electrode 109. Consequently, intrusion of metal into the lower part of the drain electrode 109 can be avoided differently from a case wherein ohmic contact is formed at the drain electrode 109 by the conventional heat treatment. Consequently, the leakage current caused by the intrusion of the metal is reduced to improve the breakdown voltage of the field effect transistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a lateral field effect transistor (FET) using a semiconductor.

  Conventionally, a lateral FET using a semiconductor has been widely used as a switching element. For example, an FET using a nitride semiconductor is very promising as a switching element for a high-frequency power device because it has high breakdown field strength and high thermal conductivity.

  FIG. 7 shows a schematic cross section of a typical lateral n-channel FET using a heterojunction. In the field effect transistor shown in FIG. 7, a channel layer 902 is formed on a substrate 901, and a barrier layer 903 having a larger band gap than the channel layer 902 is formed on the channel layer 902. A heterojunction is formed at the interface between the channel layer 902 and the barrier layer 903 having different band gaps. In the vicinity of the heterojunction interface, electrons are accumulated at a high concentration, and a two-dimensional electron gas 907 is present. In the barrier layer 903, a source electrode 904, a drain electrode 906, and a gate electrode 905 are formed.

  Conventionally, when forming an electrode, in order to lower the forward voltage during operation, the FET is generally laminated with an appropriate metal material as an electrode material and alloyed by subjecting it to high-temperature heat treatment. (See, for example, Patent Document 1 (Japanese Patent Laid-Open No. 9-69623) and Patent Document 2 (Japanese Patent Laid-Open No. 2001-196574)).

  However, in the lateral FET having the structure shown in FIG. 7, when high-temperature heat treatment is performed at the time of electrode formation, the source electrode 904 and the substrate 901 are connected to increase the applied voltage to the drain electrode 906. A rapid increase in leakage current was observed. This rapid increase was more remarkable in FETs using nitride semiconductors.

  This will be described in more detail with reference to FIGS.

  FIG. 8 is an energy band diagram along a dashed line B-B ′ of the lower side of the drain electrode 906 when a voltage is applied to the drain electrode 906 in the FET shown in FIG. 7. FIG. 9 is a photograph of a cross section of the lower portion of the drain electrode 935 observed with a transmission electron microscope (TEM) when an ohmic contact is formed by heat treatment in an FET using a nitride semiconductor.

  In FIG. 9, when the semiconductor layer is epitaxially formed on the Si substrate 931, the inside of the barrier layer 934 in which the metal material of the drain electrode 935 made of Hf / Al / Au is made of AlGaN via the dislocation 936 caused by lattice mismatch. A metal intrusion region 937 generated by intruding into is observed. The metal intrusion area 937 in FIG. 9 corresponds to the metal intrusion portion 908 in FIG. A level 925 shown in the band diagram of FIG. 8 is formed by the metal intrusion portion 908. 8, reference numeral 927 denotes a hole, reference numeral 924 denotes a region corresponding to the drain electrode 906 in FIG. 7, reference numeral 923 denotes a region corresponding to the barrier layer 903 in FIG. 7, and reference numeral 922 denotes the channel in FIG. The region corresponding to layer 902 is shown. In FIG. 9, reference numeral 932 represents a buffer layer, and reference numeral 933 represents a channel layer made of GaN.

  In such a case, when the source electrode 904 and the substrate 901 are connected and a voltage is applied to the drain electrode 906, a vertical electric field Z from the drain electrode 906 to the substrate 901 is generated below the drain electrode 906. As the electric field Z increases, as shown in FIG. 8, the hole 927 is caused by metal intrusion from the region of the drain electrode 906 represented by reference numeral 924 into the region of the barrier layer 903 represented by reference numeral 923. It is injected into the region of the channel layer 902 denoted by reference numeral 922 through the level 925. Thus, it is considered that the metal intrusion from the drain electrode into the barrier layer increases the leakage current (hole leakage).

Japanese Patent Laid-Open No. 9-69623 JP 2001-196574 A

  Accordingly, an object of the present invention is to provide a field effect transistor capable of preventing leakage current from the drain electrode.

In order to solve the above problems, a field effect transistor of the present invention comprises a substrate,
A channel layer formed on the substrate;
A source electrode, a drain electrode and a gate electrode formed on the channel layer;
The drain electrode is characterized by having a Schottky junction with the channel layer.

  According to the field effect transistor of the present invention, since the drain electrode is Schottky-bonded to the channel layer, unlike the conventional case where an ohmic contact is formed on the drain electrode by heat treatment, metal penetrates under the drain electrode. Can be avoided. Therefore, it is possible to reduce the leakage current generated due to the metal penetration, and the breakdown voltage in the field effect transistor can be improved. Therefore, the field effect transistor according to the present invention is particularly effective in a lateral field effect transistor used for high power / high frequency applications.

  In addition, according to the field effect transistor of the present invention, since a Schottky junction is used for the junction of the drain electrode, it has a good current interruption capability when a reverse voltage is applied. Therefore, it is particularly useful in a power conversion device such as a matrix converter.

  In one embodiment, the source electrode is in ohmic contact with the channel layer.

  According to this embodiment, ohmic voltage-current characteristics can be obtained in the electrical connection between the source electrode and the channel layer.

  In one embodiment, the channel layer is a group III nitride compound semiconductor layer.

  According to this embodiment, it is possible to prevent leakage current from the drain electrode in a field effect transistor using a nitride semiconductor, in which generation of leakage current from the drain electrode tends to be significant.

  In one embodiment, the substrate is a conductive substrate.

  According to this embodiment, by using a conductive substrate, it is possible to prevent an increase in current due to an increase in electric field strength to the base substrate portion and breakdown.

  That is, when the lower part of the substrate is grounded (or connected to the source electrode) by mounting or the like and a high voltage is applied to the drain electrode, a large electric field is generated from the drain electrode to the substrate. There is a possibility of causing breakdown on the substrate. In contrast, by using a conductive substrate, breakdown due to an increase in electric field strength inside the substrate can be prevented, and an increase in current due to breakdown can be prevented.

  For example, as a problem in manufacturing a high breakdown voltage device of GaN on Si, element breakdown occurs in the Si substrate under the GaN before GaN breakdown occurs. This breakdown occurs because the breakdown voltage of Si is smaller than the breakdown voltage of GaN. Therefore, for example, by using a conductive Si substrate, it is possible to prevent electric field concentration on the Si substrate that is the underlying substrate of GaN. Thereby, Si can be prevented from breaking down before GaN, and element breakdown (increase in leakage current) can be prevented.

In one embodiment, the field effect transistor has a diffusion region formed between the drain electrode and the channel layer and having the same conductivity type as the channel layer,
The drain electrode is joined to the channel layer by the diffusion region.

  According to this embodiment, the contact resistance between the drain electrode and the two-dimensional electron gas can be reduced by the diffusion region.

In one embodiment of the field effect transistor, a buffer layer formed on the substrate between the substrate and the channel layer;
A semiconductor template layer formed immediately below the channel layer between the buffer layer and the channel layer;
A barrier layer formed on the channel layer,
The source electrode, drain electrode and gate electrode are formed on the barrier layer,
The source electrode is in ohmic contact with the channel layer through the barrier layer,
The drain electrode is Schottky joined to the channel layer through the barrier layer,
The channel layer has a band gap smaller than that of the template layer and the barrier layer.

  According to this embodiment, since the channel layer has a band gap smaller than the band gaps of the template layer and the barrier layer, carriers can be confined in the channel layer. That is, leakage current (that is, parallel conduction) due to carriers moving through the semiconductor template layer, the buffer layer, and the substrate can be reduced.

Further, in the field effect transistor of one embodiment, the buffer layer is a group III nitride compound semiconductor layer,
The semiconductor template layer is an AlGaN layer;
The channel layer is a GaN layer;
The barrier layer is an AlGaN layer;
The source electrode, drain electrode and gate electrode are formed on the barrier layer via a GaN layer as a cap layer,
The source electrode is in ohmic contact with the semiconductor channel layer through the barrier layer and the cap layer,
The drain electrode is Schottky bonded to the channel layer via the barrier layer and the cap layer.

  According to this embodiment, by using a GaN-based material, a high breakdown voltage and a high-speed switching operation can be realized.

  In one embodiment, the gate electrode is formed on a recess structure.

  According to this embodiment, normally-off can be achieved by forming the gate electrode on the recess structure. Further, mutual conductance can be improved.

  The above-mentioned normally-off can be made in principle by producing a gate recess structure. For example, it becomes possible by deeply recessing the two-dimensional electron gas region and combining it with the MIS structure.

  Moreover, in the field effect transistor of one embodiment, the gate electrode constitutes a MIS structure.

  According to this embodiment, the gate leakage current can be reduced and the breakdown voltage can be improved by the MIS (Metal Insulator Semiconductor Structure) gate structure.

  According to the field effect transistor of the present invention, since the drain electrode is Schottky-bonded to the channel layer, unlike the case where an ohmic contact is formed on the drain electrode by conventional heat treatment, metal penetrates into the lower portion of the drain electrode. Can be avoided. Therefore, it is possible to reduce the leakage current caused by the metal penetration, and improve the breakdown voltage in the field effect transistor. Therefore, according to the field effect transistor of the present invention, it is possible to realize a lateral field effect transistor that is effectively used particularly for high power / high frequency applications.

  In addition, according to the field effect transistor of the present invention, since a Schottky junction is used for the junction of the drain electrode, it has a good current interruption capability when a reverse voltage is applied. Therefore, it is particularly useful in a power conversion device such as a matrix converter.

It is sectional drawing which shows 1st Embodiment of the field effect transistor of this invention. 6 is a graph showing a characteristic of a leakage current (A) with respect to a voltage (V) applied to a drain electrode in the first embodiment and the comparative example. It is sectional drawing which shows 2nd Embodiment of the field effect transistor of this invention. It is sectional drawing which shows 3rd Embodiment of the field effect transistor of this invention. It is sectional drawing which shows 4th Embodiment of the field effect transistor of this invention. It is sectional drawing which shows 5th Embodiment of the field effect transistor of this invention. It is sectional drawing which shows the conventional field effect transistor. FIG. 8 is an energy band diagram along a dashed line B-B ′ in FIG. 7. It is the cross-sectional photograph by TEM of the drain electrode lower part of the conventional FET.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments, but the present invention is not limited to the following embodiments.

(First embodiment)
FIG. 1 is a schematic cross-sectional view of a field effect transistor according to the first embodiment. In the first embodiment, the source electrode 107, have ^{n +} -type regions 113 and 112 are each diffusion region under the drain electrode 109 are formed, formed on the GaN channel layer 104 by the drain electrode 109 is a Schottky junction Has been.

As shown in FIG. 1, the field effect transistor which is a semiconductor device according to the first embodiment includes a buffer layer 102 made of AlN having a thickness of 0.5 μm, and Al _X Ga _1-X N having a thickness of 1 μm. A template layer 103 made of GaN, a channel layer 104 made of GaN having a thickness of 0.02 μm, a barrier layer 105 made of Al _X Ga _1-X N having a thickness of 0.025 μm, and a cap layer 106 made of GaN having a thickness of 10 mm. Are sequentially formed on the conductive substrate 101 made of n ⁺ -Si, and in the first conductivity type channel, electrons become carriers and the transistor operates. In FIG. 1, reference numeral 110 represents a two-dimensional electron gas, and reference numeral 111 represents a metal intrusion portion.

  In this embodiment, the Al mixed crystal ratio x in the template layer 103 is set to 0.05, and the Al mixed crystal ratio x in the barrier layer 105 is set to 0.25.

Note that an n ⁺ -Si substrate, a high-resistance substrate, or the like may be used instead of the conductive substrate 101.

  The gate electrode 108 is formed on the GaN cap layer 106 using a vacuum deposition method.

Next, a method for forming the n ⁺ region 112 and the source electrode 107 under the source electrode 107 in this embodiment will be described.

The n ⁺ -type region 113 formed under the source electrode 107 is formed by ion implantation of Si. That is, the n ⁺ -type region 113 is formed by etching the GaN cap layer 106 with a width of 2.6 μm by dry etching in order to reduce the contact resistance in the ohmic contact, and then adding Si as a dopant by ion implantation. It is fabricated by injecting at × 10 ¹⁵ (1 / cm ² ).

The source electrode 107 is formed by stacking Hf / Al / Au having a width of 3.0 μm on the n ⁺ region 113 by using a vacuum evaporation method, and performing a heat treatment at 850 ° C. for 30 seconds to thereby form GaN. The channel layer 104 is electrically connected.

  The metal used to form the source electrode 107 is at least one metal selected from Ti, Zr, Hf, Al, AlSi, W, WN, Au, and Pt. Further, the source electrode 107 may be formed by a sputtering method.

Next, a method for forming the n ⁺ -type region (diffusion region) 112 and the drain electrode 109 under the drain electrode 109 in this embodiment will be described.

The n ⁺ -type region 112 formed under the drain electrode 109 is formed by Si ion implantation. Further, in this n ⁺ -type region 112, after etching the GaN cap layer 106 with a width of 2.6 μm by dry etching, a dopant Si is implanted at 1 × 10 ¹⁵ (1 / cm ² ) by ion implantation. It is made. The n ⁺ -type region 112 may be formed using epitaxial growth or Si thermal diffusion.

The drain electrode 109 is formed by stacking WN / Al having a width of 3.0 μm on the n ⁺ region 112 using a vacuum deposition method, and the GaN channel layer 104 and the n ⁺ type region 112 are connected to the drain electrode 109. Schottky connected. The metal used to form the drain electrode 109 is most preferably W / Au, which is thermally stable. For example, another thermally stable electrode metal such as Ti / Pt / Au may be used. Good. Further, the drain electrode 109 may be formed by a sputtering method.

  Next, the effect obtained by the lateral field effect transistor of this embodiment will be described.

  FIG. 2 is a graph showing the characteristics of the leakage current (A) with respect to the voltage (V) applied to the drain electrode 109 in a state where the source electrode 107 and the substrate 101 are connected in the first embodiment. The characteristic K1 in this graph is a characteristic when Hf / Al / Au is used as the metal material constituting the drain electrode 109, and the characteristic K2 is the case where WN / Au is used as the metal material constituting the drain electrode 109. It is a characteristic.

  As shown by the characteristic K1 in FIG. 2, when the drain electrode 109 is made of Hf / Al / Au and an ohmic contact is formed by a conventional heat treatment, the leakage current rapidly increases as the applied voltage to the drain electrode 109 increases. It shows that it increases.

  On the other hand, as shown by the characteristic K2 in FIG. 2, when the drain electrode 109 is made of WN / Au which is a thermally stable electrode material, an increase in leakage current generated when a voltage is applied to the drain electrode is larger than that of the characteristic K1. Is suppressed. This is because the drain electrode 109 made of WN / Au is thermally stable compared to the drain electrode 109 made by heat treatment using Hf / Al / Au, and the dislocation to the AlGaN barrier layer 105 is performed. This is thought to be the result of the suppression of metal intrusion via.

  As described above, the drain electrode 109 made of WN / Au can obtain an effect of suppressing leakage current due to holes from the drain electrode 109 to the channel layer 104.

In this embodiment, the band gap of the channel layer 104 made of GaN is equal to the band gap of the template layer 103 made of Al _0.05 Ga _0.95 N and the barrier layer 105 made of Al _0.25 Ga _0.75 N. Is smaller than the band gap. That is, since it has a double heterostructure, electrons as carriers can be confined in the GaN channel layer 104. Further, the n ⁺ regions 113 and 112 which are ion implantation regions under the source electrode 107 and the drain electrode 109 are formed so as not to reach the template layer 103 under the source electrode 107.

With this configuration, most of electrons serving as carriers are confined in the channel layer 104, so that leakage current, that is, parallel conduction due to electrons moving through the template layer 103, the buffer layer 102, and the substrate 101 can be reduced. Furthermore, since the n ⁺ regions 112 and 113 that are ion implantation regions are formed, the contact resistance between the electrodes 107 and 109 and the two-dimensional electron gas 110 can also be reduced.

  The present invention is effective when the electric field from the drain electrode to the substrate is increased, particularly when the source electrode and the substrate are grounded.

  Although the present invention is particularly effective when a conductive substrate that generates a large electric field from the drain electrode to the substrate is used, an insulating substrate may be used. In addition, the present invention is effective when the semiconductor layer is epitaxially grown on the substrate, particularly when dislocations are formed vertically, for example, when the semiconductor layer is formed by c-plane epitaxial growth of a nitride semiconductor.

(Second embodiment)
FIG. 3 is a schematic sectional view of a field effect transistor according to the second embodiment of the present invention. This field effect transistor has a double hetero structure.

In the second embodiment, as shown in FIG. 3, n ⁺ regions 213 and 212 which are diffusion regions are formed under the source electrode 207 and the drain electrode 209, respectively. The n ⁺ region (diffusion region) 213 is formed by a Schottky junction under the source electrode 207, and the n ⁺ region (diffusion region) 212 is formed by a Schottky junction under the drain electrode 209. That is, in this embodiment, both the source electrode 207 and the drain electrode 209 are Schottky-bonded to the channel layer 204 via the n ⁺ regions (diffusion regions) 213 and 212.

As shown in FIG. 3, in the second embodiment, a buffer layer 202 having a laminated structure of AlN / GaN having a thickness of 0.5 μm, Al _X Ga _1-X N having a thickness of 1 μm (x = 0. 05), a channel layer 204 made of GaN having a thickness of 0.02 μm, a barrier layer 205 made of Al _X Ga _1- XN (x = 0.25) having a thickness of 0.025 μm, a thickness A cap layer 206 made of GaN having a thickness of 10 mm is formed in order on the conductive substrate 201 made of n ⁺ -Si. In the channel layer 204, electrons act as carriers and the transistor operates. In FIG. 3, reference numeral 210 represents a two-dimensional electron gas.

  Further, the gate electrode 208 is formed on the cap layer 206 using a vacuum deposition method.

Next, a method of forming the source electrode 207 and the drain electrode 209, and the n ⁺ region (diffusion region) 213 under the source electrode 207 and the n ⁺ region (diffusion region) 212 under the drain electrode 209 in the second embodiment will be described. To do.

The n ⁺ regions (diffusion regions) 212 and 213 under the drain electrode 209 and the source electrode 207 were formed by ion implantation. Further, the source electrode 207 and the drain electrode 209 were formed by stacking WN / Au having a width of 3.0 μm on the n ⁺ regions (diffusion regions) 212 and 213 using a vacuum deposition method. Note that the source electrode 207 and the drain electrode 209 may be formed by a sputtering method.

  As in the second embodiment, the source electrode 207 and the drain electrode 209 made of WN / Au are thermally compared with the source electrode and the drain electrode made by heat treatment using Hf / Al / Au. And the metal intrusion through the dislocation to the AlGaN barrier layer 205 can be suppressed. Therefore, according to the second embodiment, similarly to the first embodiment described above, metal penetration from the drain electrode 209 into the AlGaN barrier layer 205 can be suppressed, leakage current due to metal penetration can be prevented, and the drain electrode 209 can be prevented. Thus, an effect of suppressing leakage current due to holes from to the channel layer 204 can be obtained.

In the second embodiment, the band gap of the channel layer 204 made of GaN is that of the template layer 203 made of Al _0.05 Ga _0.95 N and the barrier layer 205 made of Al _0.25 Ga _0.75 N. Since it is smaller than the band gap, electrons as carriers are usually confined in the channel layer 204. Further, n ⁺ regions 213 and 212 which are ion implantation regions under the source electrode 207 and the drain electrode 209 are formed so as not to reach the template layer 203 under the source electrode 207 and the drain electrode 209.

  With this configuration, since most of the electrons that are carriers are confined in the channel layer 204, leakage current, that is, parallel conduction due to electrons moving through the template layer 203, the buffer layer 202, and the substrate 201 can be reduced. Furthermore, since the n + regions 212 and 213 that are ion implantation regions are formed, the contact resistance between the electrodes 207 and 209 and the two-dimensional electron gas 210 can be reduced.

  The present invention is particularly effective when the source electrode and the substrate are grounded, where the electric field from the drain electrode to the substrate increases. It is particularly effective when used as a bidirectional switch in a power converter such as a matrix converter.

(Third embodiment)
FIG. 4 is a schematic cross-sectional view of a field effect transistor according to the third embodiment of the present invention. The third embodiment has a MISFET structure.

In the third embodiment, as shown in FIG. 4, a buffer layer 302, a template layer 303, a channel layer 304, a barrier layer 305, and an insulating film layer 313 are sequentially formed on a substrate 301. In this embodiment, as an example, the buffer layer 302 is made of AlN having a thickness of 0.5 μm, and the template layer 303 is made of Al _X Ga _1- XN (x = 0.05) having a thickness of 1 μm. In this embodiment, as an example, the channel layer 304 is made of GaN having a thickness of 0.02 μm, and the barrier layer 305 is Al _X Ga _1-X N having a thickness of 0.025 μm (x = 0.25). Consists of. In the channel layer 304, electrons act as carriers and the FET operates. In FIG. 4, reference numeral 310 denotes a two-dimensional electron gas. Reference numeral 311 represents a metal intrusion portion. In this embodiment, the substrate 301 is a conductive substrate. However, an n ⁺ -Si substrate or a high resistance substrate may be used.

  The gate electrode 308 is formed on the insulating film layer 313 in order to obtain good gate insulating characteristics. That is, the third embodiment has a MISFET structure. Note that an oxide film may be used as the insulating film layer 313 under the gate electrode 308.

  The source electrode 307 made of WN / Au is formed by laminating a material metal in a region where the insulating film layer 313 is etched so as to be in direct contact with the AlGaN barrier layer 305, and is electrically connected to the channel layer 304. Connected. That is, the WN / Au source electrode 307 is in ohmic contact with the GaN channel layer 304.

Next, a method for forming the n ⁺ region (diffusion region) 312 and the drain electrode 309 under the drain electrode 309 made of WN / Au will be described.

An n ⁺ region (active region) 312 under the drain electrode 309 is formed by ion implantation or diffusion. The drain electrode 309 is formed so as to be in direct contact with the n ⁺ region (active region) 312 by etching the insulating film layer 313 and is Schottky connected to the GaN channel layer 304 via the n ⁺ region 312.

  According to the third embodiment, similarly to the first embodiment described above, the WN / Au drain electrode 309 is thermally stable, and metal intrusion via dislocation to the AlGaN barrier layer 305 is suppressed. As a result, leakage current due to holes from the drain electrode 309 to the channel layer 304 can be suppressed.

(Fourth embodiment)
FIG. 5 is a schematic sectional view of a field effect transistor according to a fourth embodiment of the present invention. In the fourth embodiment, the gate electrode 408 is formed on the recess structure.

In the fourth embodiment, as shown in FIG. 5, a buffer layer 402, a channel layer 404, and a barrier layer 405 are sequentially formed on a substrate 401. The buffer layer 402 has a laminated structure of AlN / GaN having a thickness of 0.5 μm, and the channel layer 404 is made of GaN having a thickness of 1.0 μm. Moreover, the barrier layer 405 is made of Al _X Ga _1-X N (x = 0.25) having a thickness of 0.025 μm, and the substrate 401 is a conductive substrate made of n ⁺ -Si. Further, a cap layer 406 made of GaN having a thickness of 10 mm is formed on the barrier layer 405.

  In the GaN channel layer 404, electrons act as carriers and the FET operates. In FIG. 5, reference numeral 410 represents a two-dimensional electron gas.

  Further, in order to obtain good pinch-off characteristics, the gate electrode 408 is formed on the channel layer 404 on the region where the barrier layer 405 and the cap layer 406 are etched, as shown in FIG. That is, the gate electrode 408 is formed on the recess structure.

Next, a method for forming the source electrode 407 and the drain electrode 409 and the n ⁺ regions (diffusion regions) 413 and 412 under the source electrode 407 and the drain electrode 409 will be described.

  The diffusion regions 413 and 412 below the source electrode 407 and the drain electrode 409 are formed by Si diffusion. That is, the cap layer 406 is etched, a Si layer is formed so as to cover the etched portion, and Si in the Si layer is diffused under the portion where the electrodes 407 and 409 are formed by heat treatment to form the active regions 413 and 412. Forming.

  The source electrode 407 and the drain electrode 409 are formed on the active regions 413 and 412 and are Schottky connected. In the fourth embodiment, as an example, the source electrode 407 and the drain electrode 409 are formed by laminating WN / Au.

  According to the fourth embodiment, similarly to the first embodiment described above, metal penetration from the drain electrode 409 into the AlGaN barrier layer 405 can be suppressed, and leakage current due to metal penetration can be prevented.

(Fifth embodiment)
Next, FIG. 6 shows a schematic cross section of a field effect transistor according to a fifth embodiment of the present invention. The fifth embodiment has a MES (Metal Semiconductor) structure.

  In the fifth embodiment, as shown in FIG. 6, a buffer layer 502 and a channel layer 504 are sequentially formed on a substrate 501, and in the channel layer 504, electrons become carriers and a transistor operates. In the fifth embodiment, as an example, the buffer layer 502 is made of AlN having a thickness of 0.5 μm, and the channel layer 504 is made of GaN having a thickness of 1.0 μm.

  In the fifth embodiment, the gate electrode 508 is formed on the channel layer 504. The source electrode 507 and the drain electrode 509 are formed on the channel layer 504 by a Schottky junction. In the fifth embodiment, as an example, the source electrode 507 and the drain electrode 509 are formed by stacking Ti / Pt / Au.

  According to the fifth embodiment, as in the first embodiment, an increase in leakage current due to metal intrusion from the drain electrode 509 to the channel layer 504 can be suppressed.

  In the first to fifth embodiments, the case where the carrier is an electron has been described, but it is needless to say that the present invention can also be applied when the carrier is a hole.

101, 201, 301, 401, 501 Substrate 102, 202, 302, 402, 502 Buffer layer 103, 203, 303 Template layer 104, 204, 304, 404, 504 Channel layer 105, 205, 305, 405 Barrier layer 106, 206, 406 Cap layer 107, 207, 307, 407, 507 Source electrode 108, 208, 308, 408, 508 Gate electrode 109, 209, 309, 409, 509 Drain electrode 110, 210, 310, 410 Two-dimensional electron gas 111 311 Metal intrusion 112, 113, 212, 213, 312, 412, 413 Diffusion region 313 Insulating film layer

Claims (9)

A substrate,
A channel layer formed on the substrate;
A source electrode, a drain electrode and a gate electrode formed on the channel layer;
2. The field effect transistor according to claim 1, wherein the drain electrode is a Schottky junction with the channel layer. The field effect transistor according to claim 1,
The channel layer is
A field effect transistor, which is a group III nitride compound semiconductor layer. The field effect transistor according to claim 1 or 2,
A diffusion region formed between the drain electrode and the channel layer and having the same conductivity type as the channel layer;
The field effect transistor according to claim 1, wherein the drain electrode is joined to the channel layer by the diffusion region. The field effect transistor according to any one of claims 1 to 3,
The field effect transistor according to claim 1, wherein the source electrode is in ohmic contact with the channel layer. In the field effect transistor according to any one of claims 1 to 4,
The field effect transistor according to claim 1, wherein the substrate is a conductive substrate. The field effect transistor according to any one of claims 1 to 5,
A buffer layer formed on the substrate between the substrate and the channel layer;
A semiconductor template layer formed immediately below the channel layer between the buffer layer and the channel layer;
A barrier layer formed on the channel layer,
The source electrode, drain electrode and gate electrode are formed on the barrier layer,
The source electrode is in ohmic contact with the channel layer through the barrier layer,
The drain electrode is Schottky joined to the channel layer through the barrier layer,
The channel layer has a band gap smaller than the band gap of the template layer and the barrier layer. The field effect transistor according to claim 6, wherein
The buffer layer is a group III nitride compound semiconductor layer,
The semiconductor template layer is an AlGaN layer;
The channel layer is a GaN layer;
The barrier layer is an AlGaN layer;
The source electrode, drain electrode and gate electrode are formed on the barrier layer via a GaN layer as a cap layer,
The source electrode is in ohmic contact with the semiconductor channel layer through the barrier layer and the cap layer,
2. The field effect transistor according to claim 1, wherein the drain electrode is in Schottky junction with the channel layer through the barrier layer and the cap layer. The field effect transistor according to any one of claims 1 to 7,
A field effect transistor, wherein the gate electrode is formed on a recess structure. The field effect transistor according to any one of claims 1 to 8,
A field effect transistor, wherein the gate electrode constitutes a MIS structure.

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