CN112287506B - Simulation model of power metal oxide semiconductor transistor - Google Patents
Simulation model of power metal oxide semiconductor transistor Download PDFInfo
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- 238000004088 simulation Methods 0.000 title claims abstract description 76
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 21
- 150000004706 metal oxides Chemical class 0.000 title abstract description 21
- 239000004065 semiconductor Substances 0.000 title abstract description 21
- 230000015556 catabolic process Effects 0.000 claims abstract description 30
- 230000000694 effects Effects 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 21
- 230000002277 temperature effect Effects 0.000 claims description 9
- 238000011084 recovery Methods 0.000 claims description 4
- 230000006903 response to temperature Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 7
- 238000012546 transfer Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
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- 230000001413 cellular effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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Abstract
A simulation model of a power metal oxide semiconductor field effect transistor is used for measuring a plurality of parameters of the power metal oxide semiconductor field effect transistor to respectively generate a plurality of corresponding simulation results. Wherein the first voltage controlled voltage source simulates a gate charge behavior on the gate node with the first sub-circuit in response to a temperature change. The first lookup current source is used for simulating an equivalent current value generated by the capacitance between the grid electrode and the drain electrode according to the lookup current value of the second sub-circuit. The transistor sub-circuit is used for simulating the behavior of the conductive voltage in a small current interval and a large current interval. The breakdown voltage module simulates a breakdown voltage effect between the drain node and the source node according to the voltage value of the first sub-circuit.
Description
Technical Field
The present invention relates to a simulation model of a power Metal Oxide Semiconductor (MOS) transistor, and more particularly, to a simulation model of a power Metal Oxide Semiconductor (MOS) transistor capable of reducing an operational load during simulation.
Background
Transistors are electrical components in computers, televisions, cellular telephones, and many other electronic products. Designers often use simulator programs to simulate a schematic version of a transistor to observe its circuit behavior.
For complex electronic circuit designs, simulations are typically performed for verifying the functionality of the electronic circuit and for optimizing its performance. By modeling the target electronic component, it is desirable to be able to accurately model the electronic component used in the circuit. In particular, as products change day by day, a lot of human resources and time are consumed to measure each parameter characteristic of the electronic component. It is therefore desirable to be able to perform simulations directly using an accurate model of a power transistor with time and effort saving to reduce development time.
In existing circuit simulation software, a number of existing transistor simulation models have been provided that can widely simulate power transistors. However, in some cases, the use of these existing transistor simulation models may lead to inaccurate predictions of the behavior of certain transistor circuits. In addition, existing transistor analog models often use a large number of components, and thus may place a large burden on the computing system.
Therefore, there is an urgent need for a simulation model of a power transistor that can reduce the number of components used and reduce the simulation load of an operation system while having a certain accuracy.
Disclosure of Invention
The invention aims to provide a simulation model of a power Metal Oxide Semiconductor (MOS) field effect transistor aiming at the defects of the prior art.
In order to solve the above-mentioned problems, one of the technical solutions adopted in the present invention is to provide a simulation model of a power mosfet, which is configured to measure a plurality of parameters of the power mosfet to generate a plurality of simulation results, where the simulation model of the power mosfet includes: a gate node, a source node, and a drain node; a gate resistor connected between the gate node and a first node; a first voltage controlled voltage source connected between the gate resistor and a first node configured to simulate a gate charge behavior on the gate node with a first sub-circuit in response to temperature changes; a source resistor connected between the source node and a second node; a gate-source capacitance and a gate-source resistance connected between the first node and the second node; a drain resistor connected between the drain node and a third node; the first table look-up current source is connected between the drain node and the first node and is used for simulating an equivalent current value generated by a capacitance between a grid and a drain according to a table look-up current value of a second sub-circuit; a transistor sub-circuit comprising: a first transistor connected to the first node, the second node and the third node; and a second transistor connected to the first node, the second node and the third node, wherein the first transistor and the second transistor are used for simulating the behavior of a conductive voltage in a small current interval and a large current interval; and a breakdown voltage module connected between a fourth node between the source node and the source resistor and a fifth node between the drain node and the drain resistor, the breakdown voltage module being configured to simulate a breakdown voltage effect between the drain node and the source node according to a voltage value of the first sub-circuit.
Preferably, the first sub-circuit includes: a current source connected between a sixth node and a seventh node; a breakdown resistor connected between the seventh node and an eighth node; a temperature effect resistor connected between the sixth node and the eighth node; and a first direct current power supply connected between the sixth node and the temperature effect resistor.
Preferably, the sixth node is connected to the second node.
Preferably, the voltage of the first voltage-controlled voltage source is generated according to the voltages of the sixth node and the eighth node.
Preferably, the breakdown voltage module includes: a breakdown diode connected to the fifth node; and a second voltage-controlled voltage source connected between the breakdown diode and the fourth node.
Preferably, the voltage of the second voltage-controlled voltage source is generated according to the voltages of the seventh node and the eighth node.
Preferably, the second sub-circuit includes: the second direct current power supply is connected between a grounding end and a ninth node; a capacitor connected between the ninth node and a tenth node; the third voltage-controlled voltage source is connected between the tenth node and the grounding end, wherein the voltage of the third voltage-controlled voltage source is generated according to the voltages of the first node and the fifth node; and a lookup table configured to query a voltage-current comparison table according to the voltage value of the tenth node to generate the lookup current value, wherein the first lookup current source simulates the equivalent current value according to the lookup current value.
Preferably, the analog model of the power mosfet further includes a gate inductance circuit connected between the gate node and the gate resistor, the gate inductance circuit including a gate inductance and a gate inductance resistor connected in parallel.
Preferably, the analog model of the power mosfet further includes a source inductor circuit connected between the source node and the source resistor, and the source inductor circuit includes a source inductor and a source inductor resistor connected in parallel.
Preferably, the simulation model of the power mosfet further includes a drain inductance circuit connected between the drain node and the drain resistor, and the drain inductance circuit includes a drain inductance and a drain inductance resistor connected in parallel.
Preferably, the parameters include at least one of a conduction voltage, an on-resistance, a body diode with reverse recovery charge, a gate charge, an input capacitance, an output capacitance, and a feedback capacitance.
One of the advantages of the invention is that the simulation model of the power Metal Oxide Semiconductor (MOS) transistor provided by the invention uses fewer components, so that the load of an operation system during simulation can be reduced.
In addition, the simulation model of the power metal oxide semiconductor field effect transistor has a certain degree of accuracy, and a plurality of parameters can be adjusted individually according to the requirements of users due to high parameter independence. In addition, the design of the first sub-circuit can respond to temperature change to provide a change function with high-temperature and low-temperature electrical characteristics, and a parametric model of a high-order metal oxide semiconductor field effect transistor is not needed.
For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for purposes of reference only and are not intended to limit the invention.
Drawings
Fig. 1 is a flow chart of a simulation method of a power Metal Oxide Semiconductor (MOS) transistor according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a simulation model of a power mosfet according to an embodiment of the invention.
Fig. 3A and 3B are graphs of transfer characteristics at different temperatures and actually measured transfer characteristics, respectively, generated when a simulation is performed using a simulation model of the power mosfet of the present invention.
Fig. 4A and 4B are graphs of gate charge characteristics and graphs of actually measured gate charge characteristics, respectively, generated when a simulation is performed using a simulation model of the power mosfet of the present invention.
Fig. 5A and 5B are graphs of drain-source on-resistance junction temperature plots and actually measured drain-source on-resistance junction temperature plots, respectively, generated when a simulation is performed using a simulation model of the power mosfet of the present invention.
Fig. 6A and 6B are graphs of the capacitance values of the output power capacitor (Coss) and the feedback capacitor (Crss) generated when the simulation model of the power mosfet of the present invention is used for simulation, and graphs of the capacitance values of the actually measured input power capacitor (Ciss), output power capacitor (Coss) and feedback capacitor (Crss) are plotted against the drain-source voltage, respectively.
Detailed Description
The following specific examples are presented to illustrate the embodiments of the present invention disclosed herein with respect to "simulation method of power mos transistors", and those skilled in the art will appreciate the advantages and effects of the present invention from the disclosure herein. The invention is capable of other and different embodiments and its several details are capable of modifications and various other uses and applications, all of which are obvious from the description, without departing from the spirit of the invention. The drawings of the present invention are merely schematic illustrations, and are not intended to be drawn to actual dimensions. The following embodiments will further illustrate the related art content of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or signal from another signal. In addition, the term "or" as used herein shall include any one or combination of more of the associated listed items as the case may be.
Fig. 1 is a flow chart of simulation using a model of a power Metal Oxide Semiconductor (MOS) transistor in accordance with an embodiment of the present invention.
Referring to fig. 1, when the model of the power Metal Oxide Semiconductor (MOS) transistor according to the embodiment of the present invention is used for simulation, the method at least includes the following steps:
Step S1: power mosfet simulation models are used to simulate power mosfets.
Step S2: a plurality of parameters are input into a power MOSFET analog model, respectively.
Step S3: a corresponding plurality of simulation results are generated.
The power mosfet simulation model created in step S1 may include simulation model 1 of fig. 2, and may be used in a simulation such as a SPICE simulation or other simulation procedure.
In creating the simulation model of the power mosfet, information may be included that provides information indicative of, for example, the connections between the various nodes of the simulation model of the transistor.
For example, information may be provided indicating the connection between the anode and cathode of the diode analog model, the base, collector, and emitter of the transistor analog model, and various nodes of the analog model, and information may be provided indicating that the nodes of the analog model correspond to the base, collector, and emitter of the power transistor.
In addition, the information of the analog model of the power Metal Oxide Semiconductor (MOS) transistor of the present invention may include information conforming to SPICE analog format. For example, information to create a simulation model may be provided to a computer system, which may receive information of a power mosfet simulation model and use the information to simulate a power transistor.
With further reference to fig. 2, a schematic diagram of a simulation model of a power mosfet in accordance with an embodiment of the present invention is shown.
Referring to fig. 2, the present invention provides a simulation model 1 of a power mosfet, which includes a gate node G, a source node S, a drain node D, a gate resistor Rg, a first voltage-controlled voltage source Es1, a source resistor Rs, a drain resistor Rd, a first lookup current source G11, a transistor circuit 10, and a breakdown voltage module 12.
The gate resistor Rg is connected between the gate node G and the first node N1, and the first voltage-controlled voltage source Es1 is connected between the gate resistor Rg and the first node N1. Here, the first voltage controlled voltage source Es1 is configured to simulate the gate charge behavior on the gate node G with the first subnetwork 14 in response to temperature variations.
In detail, the switching rate of the power mosfet is mainly operated by the charge and discharge of the gate, and the smaller the amount of charge (Qg) inputted to the gate is, the faster the switching rate is. All power mosfets lose energy during switching, which translates into thermal energy and reduces performance. The energy lost during switching is directly related to the switching time, which in turn is related to the magnitude of the capacitance in the structure, and in particular the magnitude of the amount of charge (Qgd) present between the gate and the drain. Also, gate charge is an important characteristic that determines the switching rate of a mosfet.
The source resistor Rs is connected between the source node S and the second node N2. On the other hand, the breakdown voltage module 12 is connected between the fourth node N4 between the source node S and the source resistor Rs and the fifth node N5 between the drain node D and the drain resistor Rd, and is configured to simulate the breakdown voltage effect between the drain node D and the source node S according to a voltage value of the first sub-circuit 14. The breakdown voltage module 12 may include a breakdown diode Dbr and a second voltage controlled voltage source Esb. The breakdown diode Dbr is connected to the fifth node N5, and the second voltage-controlled voltage source Esb is connected between the breakdown diode Dbr and the fourth node N4. The body diode Dbo is connected between the fourth node N4 and the fifth node N5.
Here, the breakdown voltage between the drain node D and the source node S is the maximum voltage that can be sustained between the drain and the source of the power mosfet, and is mainly limited by the inclusion of a reverse diode, such as the breakdown voltage of the breakdown diode Dbr.
Specifically, the first subnetwork 14 includes a current source It, a breakdown resistor Rbr, a temperature effect resistor Rvt and a first dc power supply Vt, the current source It is connected between the sixth node N6 and the seventh node N7, the breakdown resistor Rbr is connected between the seventh node N7 and the eighth node N8, the temperature effect resistor Rvt is connected between the sixth node N6 and the eighth node N8, and the first dc power supply Vt is connected between the sixth node and the temperature effect resistor Rvt.
In the present embodiment, the sixth node N6 is connected to the second node N2, and the voltage of the second voltage-controlled voltage source Esb is generated according to the voltages of the seventh node N7 and the eighth node N8. Here, it should be noted that the voltages of the seventh node N7 and the eighth node N8 are affected by the current source It, the breakdown resistor Rbr, the temperature effect resistor Rvt and the first dc power supply Vt, wherein the temperature effect resistor Rvt and the first dc power supply Vt are used for the effect of the equivalent breakdown diode Dbr with the temperature change, and the magnitude of the charge amount (Qgd) existing between the gate and the drain is also affected by the temperature change, so that the voltage of the first voltage-controlled voltage source Es1 can be generated according to the voltages of the sixth node N6 and the eighth node N8.
On the other hand, the first lookup current source G11 is connected between the drain node D and the first node N1, and is configured to simulate an equivalent current value generated by the inter-gate-drain capacitance according to the lookup current value of the second subnetwork 16.
As device density increases, the charge between the gate and the drain, or feedback capacitance (REVERSE TRANSFER CAPACITANCE, abbreviated as Crss, this is also called the gate-drain capacitance Cgd) also increases, which slows the charge-discharge rate of the gate node G and affects device performance. This Cgd value is an important parameter to increase the current density of the device and maintain the high frequency characteristics of the device.
In order to simulate the parameter, the second subnet 16 includes a second dc power V11, a capacitor C11, a third voltage-controlled voltage source E11 and a Table lookup Table. The second dc power source V11 is connected between the ground terminal and the ninth node N9, the capacitor C11 is connected between the ninth node N9 and the tenth node N10, and the third voltage-controlled voltage source E11 is connected between the tenth node N10 and the ground terminal. The voltage of the third voltage-controlled voltage source E11 is generated according to the voltages of the first node N1 and the fifth node N5.
The Table lookup unit Table is configured to query the voltage-current comparison Table according to the voltage value of the tenth node N10 to generate a Table lookup current value as the equivalent current value generated by the first Table lookup current source G11.
In addition, in the case of power mosfet, the conduction voltage of the transistor varies depending on the amount of current generated by the transistor. In order to simulate the behavior of the conduction voltage in the small current region and the large current region, a transistor sub-circuit 10 is provided, which is connected to the first node N1, the second node N2 and the third node N3, and the transistor sub-circuit 10 includes a first transistor Ms and a second transistor Mw. The first transistor Ms has a gate connected to the first node, a source connected to the second node N2, and a drain connected to the third node N3, and is suitable for simulating the behavior of the conductive voltage in the high current interval. On the other hand, the second transistor Mw has a gate connected to the first node N1, a source connected to the second node N2, and a drain connected to the third node N3, and is adapted to simulate the behavior of the conduction voltage in the small current interval.
In addition, the power mosfet simulation model 1 further includes a gate inductance circuit 100 connected between the gate node G and the gate resistor Rg, and the gate inductance circuit 100 includes a gate inductance Lg and a gate inductance resistor RLg connected in parallel. Similarly, the power mosfet simulation model 1 further includes a source inductor circuit 102 connected between the source node S and the source resistor Rs, and the source inductor circuit 102 includes a source inductor Ls and a source inductor resistor RLs connected in parallel. Similarly, the power mosfet simulation model 1 further includes a drain inductance circuit 104 connected between the drain node D and the drain resistance Rd, and the drain inductance circuit 104 includes a drain inductance Ld and a drain inductance resistance RLd connected in parallel.
In addition, the power mosfet simulation model 1 further includes a gate-source capacitance Cgs and a gate-source resistance Rgs. The gate-source capacitance Cgs and the gate-source resistance Rgs are connected between the first node N1 and the second node N2. The drain resistor Rd is connected between the drain node D and the third node N3.
The power mosfet simulation model 1 is created to generate a plurality of simulation results, such as conductive voltage, on-resistance, body diode with reverse recovery charge, gate charge, input capacitance, output capacitance, and feedback capacitance.
In the simulation method of the power Metal Oxide Semiconductor (MOS) transistor provided in the above embodiment, since fewer components are used in the model of the power metal oxide semiconductor transistor, the load of the operation system during simulation can be reduced.
In addition, the simulation model of the power metal oxide semiconductor field effect transistor has a certain degree of accuracy, and a plurality of parameters can be adjusted individually according to the requirements of users due to high parameter independence. In addition, the first sub-circuit is designed to respond to temperature change to provide a change function with high-temperature and low-temperature electrical characteristics, and the second sub-circuit can be used for simulating the effect of feedback capacitance, so that electrical characteristic parameters such as conducting voltage, on-resistance, body diode with reverse recovery charge, grid charge, input capacitance, output capacitance and feedback capacitance can be obtained without using a parameter model of a high-order metal oxide semiconductor field effect transistor.
Various characteristic curves generated by the simulation method of the power mosfet of the present invention are presented further below and are compared with actual measurement curves to show that the present invention has a certain degree of accuracy.
Referring to fig. 3A and 3B, the transfer characteristic curves at different temperatures and the actually measured transfer characteristic curves are generated when the simulation model of the power mosfet of the present invention is used for simulation. As shown in the figure, the present invention simulates the generated drain-source current Ids versus the gate-source voltage Vgs at 125 ℃, 25 ℃ and-20 ℃ respectively, i.e., the transfer characteristic curve, and the trend of the present invention in the linear region is the same as that of the actual measured transfer characteristic curve.
Referring to fig. 4A and 4B, graphs of gate charge characteristics and graphs of actually measured gate charge characteristics are generated when the simulation model of the power mosfet of the present invention is used for simulation, respectively. As shown in the figure, the gate-source voltage Vgs obtained by simulation has a tendency of the gate-source charge amount Qgs to be in the 1.8nC section and the gate-drain charge amount Qgd to be in the 5.7nC section, which are close to the tendency of the gate-source charge amount Qgs to be in the 2nC section and the gate-drain charge amount Qgd to be in the 5.5nC section, which are actually measured.
Referring to fig. 5A and 5B, graphs of drain-source on-resistance junction temperature maps and graphs of actually measured drain-source on-resistance junction temperatures are generated when the simulation model of the power mosfet of the present invention is used for simulation. As shown, the trend of the normalized drain-source on-resistance plotted against junction temperature is the same in the range of-50 ℃ to 150 ℃ and the normalized drain-source on-resistance produced at junction temperatures-50 ℃ and 150 ℃ respectively.
Referring to fig. 6A and 6B, graphs of the capacitance values of the output power capacitor (Coss) and the feedback capacitor (Crss) plotted against the drain-source voltage and graphs of the capacitance values of the input power capacitor (Ciss), the output power capacitor (Coss) and the feedback capacitor (Crss) plotted against the drain-source voltage (Vds) are generated when the simulation model of the power mosfet of the present invention is used for simulation, respectively. Wherein, the input power capacitance (Ciss) represents the inter-gate-source capacitance plus the inter-gate-drain capacitance (cgs+cgd), the output power capacitance (Coss) represents the inter-drain-source capacitance plus the inter-gate-drain capacitance (cds+cgd), and the feedback capacitance (Crss) represents the inter-gate-drain capacitance (Cgd). As shown in the figure, in the simulation model of the power mosfet of the present invention, the input power capacitor (Ciss) is set to a constant value by looking up the characteristic table of the corresponding component, and the change trend of the drain-source voltage is the same as the change trend of the actually measured output power capacitor (Coss) and feedback capacitor (Crss) with respect to the capacitance value of the output power capacitor (Coss) and feedback capacitor (Crss), and the capacitance values of the corresponding output power capacitor (Coss) and feedback capacitor (Crss) are 630pF and 378pF, respectively, when the drain-source voltage is 0, which also coincides with the actually measured value.
Based on the above results, it can be seen that the simulation model parameter of the power mosfet of the present invention has high independence, so that multiple parameters can be individually adjusted according to the user's needs, and the simulation result also has a certain degree of accuracy.
Advantageous effects of the embodiments
One of the advantages of the invention is that the simulation method of the power Metal Oxide Semiconductor (MOS) transistor provided by the invention uses fewer components, so that the load of an operation system during simulation can be reduced.
In addition, the simulation model of the power metal oxide semiconductor field effect transistor has a certain degree of accuracy, and a plurality of parameters can be adjusted individually according to the requirements of users due to high parameter independence. In addition, the design of the first sub-circuit can respond to temperature change to provide a change function with high-temperature and low-temperature electrical characteristics, and a parametric model of a high-order metal oxide semiconductor field effect transistor is not needed.
The foregoing disclosure is only a preferred embodiment of the present invention and is not intended to limit the scope of the claims, so that all equivalent technical changes made by the application of the present invention and the accompanying drawings are included in the scope of the claims.
Claims (10)
1. A simulation model of a power mosfet, for measuring a plurality of parameters of the power mosfet to generate a plurality of simulation results, the simulation model of the power mosfet comprising:
A gate node, a source node, and a drain node;
A gate resistor connected between the gate node and a first node;
a first voltage controlled voltage source connected between the gate resistor and a first node configured to simulate a gate charge behavior on the gate node with a first sub-circuit in response to temperature changes;
a source resistor connected between the source node and a second node;
a gate-source capacitance and a gate-source resistance connected between the first node and the second node;
A drain resistor connected between the drain node and a third node;
The first table look-up current source is connected between the drain node and the first node and is used for simulating an equivalent current value generated by a capacitance between a grid and a drain according to a table look-up current value of a second sub-circuit;
A transistor sub-circuit comprising:
a first transistor connected to the first node, the second node and the third node; and
A second transistor connected to the first node, the second node and the third node, wherein the first transistor and the second transistor are used for simulating the behavior of a conductive voltage in a small current interval and a large current interval; and
A breakdown voltage module connected between a fourth node between the source node and the source resistor and a fifth node between the drain node and the drain resistor, the breakdown voltage module being configured to simulate a breakdown voltage effect between the drain node and the source node according to a voltage value of the first sub-circuit;
Wherein the first sub-circuit comprises:
a current source connected between a sixth node and a seventh node;
a breakdown resistor connected between the seventh node and an eighth node;
a temperature effect resistor connected between the sixth node and the eighth node; and
And the first direct current power supply is connected between the sixth node and the temperature effect resistor.
2. The model of claim 1, wherein the sixth node is connected to the second node.
3. The model of claim 1, wherein the voltage of the first voltage controlled voltage source is generated based on the voltages of the sixth node and the eighth node.
4. The simulation model of a power mosfet of claim 1 wherein the breakdown voltage module comprises:
a breakdown diode connected to the fifth node; and
And a second voltage-controlled voltage source connected between the breakdown diode and the fourth node.
5. The model of claim 4, wherein the voltage of the second voltage controlled voltage source is generated based on the voltages of the seventh node and the eighth node.
6. The analog model of a power mosfet of claim 1, wherein the second sub-circuit comprises:
The second direct current power supply is connected between a grounding end and a ninth node;
A capacitor connected between the ninth node and a tenth node;
the third voltage-controlled voltage source is connected between the tenth node and the grounding end, wherein the voltage of the third voltage-controlled voltage source is generated according to the voltages of the first node and the fifth node; and
And the table lookup device is configured to query a voltage-current comparison table according to the voltage value of the tenth node so as to generate the table lookup current value, wherein the first table lookup current source simulates the equivalent current value according to the table lookup current value.
7. The model of claim 1, further comprising a gate inductor circuit connected between the gate node and the gate resistor, the gate inductor circuit comprising a gate inductor and a gate inductor resistor connected in parallel.
8. The model of claim 1, further comprising a source inductor circuit connected between the source node and the source resistor, the source inductor circuit comprising a source inductor and a source inductor resistor connected in parallel.
9. The model of claim 1, further comprising a drain inductor circuit connected between the drain node and the drain resistor, the drain inductor circuit comprising a drain inductor and a drain inductor resistor connected in parallel.
10. The model of claim 1, wherein the parameters include at least one of conduction voltage, on-resistance, body diode with reverse recovery charge, gate charge, input capacitance, output capacitance, and feedback capacitance.
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