CN112287506B - Simulation model of power metal oxide semiconductor transistor - Google Patents

Abstract

A simulation model of a power metal oxide semiconductor field effect transistor is used to measure multiple parameters of the power metal oxide semiconductor field effect transistor to generate corresponding multiple simulation results respectively. The simulation model of the power metal oxide semiconductor field effect transistor includes a first voltage-controlled voltage source, a first table lookup current source, a transistor subcircuit and a breakdown voltage module. The first voltage-controlled voltage source simulates the gate charge behavior on the gate node with the first subcircuit in response to temperature changes. The first table lookup current source is used to simulate the equivalent current value generated by the gate-drain capacitance according to the table lookup current value of the second subcircuit. The transistor subcircuit is used to simulate the behavior of the conductive voltage in the small current interval and the large current interval. The breakdown voltage module simulates the breakdown voltage effect between the drain node and the source node according to the voltage value of the first subcircuit.

Description

Simulation Model of Power MOS Transistor

Technical Field

The present invention relates to a simulation model of a power metal oxide semiconductor (MOS) transistor, and in particular to a simulation model of a power metal oxide semiconductor (MOS) transistor capable of reducing computational load during simulation.

Background technique

Transistors are electrical components in computers, televisions, cellular phones, and many other electronic products. Designers often use simulator programs to simulate a schematic version of a transistor to observe its circuit behavior.

For the design of complex electronic circuits, simulations are typically performed to verify the functionality of the electronic circuit and to optimize its performance. By simulating the target electronic component, it is expected that the model of the electronic component used in the circuit can be accurately established. In particular, as products change with each passing day, it will take a lot of human resources and time to measure each parameter characteristic of the electronic component. Therefore, it is expected to be able to directly use the accurate model of the power transistor for simulation in a time-saving and labor-saving manner to reduce development time.

In existing circuit simulation software, many existing transistor simulation models that can be widely used to simulate power transistors have been provided. However, in some cases, the use of these existing transistor simulation models may lead to inaccurate predictions of the behavior of certain transistor circuits. In addition, existing transistor simulation models often use a large number of components, which may cause a large burden on the computing system.

Therefore, there is an urgent need for a simulation model of a power transistor that can reduce the number of components used and reduce the simulation load of the computing system while having a certain accuracy.

Summary of the invention

The technical problem to be solved by the present invention is to provide a simulation model of a power metal oxide semiconductor (MOS) field effect transistor in view of the deficiencies in the prior art.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a simulation model of a power metal oxide semiconductor field effect transistor, which is used to measure multiple parameters of a power metal oxide semiconductor field effect transistor to generate corresponding multiple simulation results respectively. The simulation model of the power metal oxide semiconductor field effect transistor includes: a gate node, a source node and a drain node; a gate resistor connected between the gate node and a first node; a first voltage-controlled voltage source connected between the gate resistor and a first node, configured to simulate a gate charge behavior on the gate node with a first subcircuit in response to temperature changes; a source resistor connected between the source node and a second node; a gate-source capacitor and a gate-source resistor connected between the first node and the second node; a drain resistor connected between the drain node and a third node. points; a first table lookup current source connected between the drain node and the first node, the first table lookup current source being used to simulate an equivalent current value generated by a gate-drain capacitance according to a table lookup current value of a second sub-circuit; a transistor sub-circuit comprising: a first transistor connected to the first node, the second node and the third node; and a second transistor connected to the first node, the second node and the third node, wherein the first transistor and the second transistor are used to simulate the behavior of a conductive voltage in a small current interval and a large current interval; and a breakdown voltage module connected between a fourth node between the source node and the source resistor and a fifth node between the drain node and the drain resistor, the breakdown voltage module being configured to simulate a breakdown voltage effect between the drain node and the source node according to a voltage value of the first sub-circuit.

Preferably, the first subcircuit includes: a current source connected between a sixth node and a seventh node; a collapse resistor connected between the seventh node and an eighth node; a temperature effect resistor connected between the sixth node and the eighth node; and a first DC power supply connected between the sixth node and the temperature effect resistor.

Preferably, the sixth node is connected to the second node.

Preferably, the voltage of the first voltage-controlled voltage source is generated according to the voltages of the sixth node and the eighth node.

Preferably, the breakdown voltage module comprises: a breakdown diode connected to the fifth node; and a second voltage-controlled voltage source connected between the breakdown diode and the fourth node.

Preferably, the voltage of the second voltage-controlled voltage source is generated according to the voltages of the seventh node and the eighth node.

Preferably, the second sub-circuit includes: a second DC power supply connected between a ground terminal and a ninth node; a capacitor connected between the ninth node and a tenth node; a third voltage-controlled voltage source connected between the tenth node and the ground terminal, wherein the voltage of the third voltage-controlled voltage source is generated based on the voltages of the first node and the fifth node; and a lookup table configured to query a voltage-current comparison table based on the voltage value of the tenth node to generate the lookup current value, wherein the first lookup current source simulates the equivalent current value based on the lookup current value.

Preferably, the simulation model of the power metal oxide semiconductor field effect transistor further includes a gate inductance circuit, wherein the gate inductance circuit is connected between the gate node and the gate resistor, and the gate inductance circuit includes a gate inductor and a gate inductance resistor connected in parallel.

Preferably, the simulation model of the power metal oxide semiconductor field effect transistor further includes a source inductor circuit connected between the source node and the source resistor, and the source inductor circuit includes a source inductor and a source inductor resistor connected in parallel.

Preferably, the simulation model of the power metal oxide semiconductor field effect transistor further includes a drain inductance circuit connected between the drain node and the drain resistor, and the drain inductance circuit includes a drain inductor and a drain inductance resistor connected in parallel.

Preferably, the parameters include at least one of a conduction voltage, an on-resistance, a body diode including a reverse recovery charge, a gate charge, an input capacitance, an output capacitance and a feedback capacitance.

One of the beneficial effects of the present invention is that the simulation model of the power metal oxide semiconductor (MOS) transistor provided by the present invention uses fewer components, thereby reducing the load of the computing system during simulation.

In addition, the simulation model of the power metal oxide semiconductor field effect transistor of the present invention has a certain degree of accuracy, and due to the high independence of parameters, multiple parameters can be individually adjusted according to user needs. In addition, the design of the first sub-circuit can respond to temperature changes to provide a function of changing high temperature and low temperature electrical characteristics, without the need to use a high-order metal oxide semiconductor field effect transistor parameter model.

To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart of a method for simulating a power metal oxide semiconductor (MOS) transistor according to an embodiment of the present invention.

FIG. 2 is a structural diagram of a power MOSFET simulation model according to an embodiment of the present invention.

3A and 3B are respectively transfer characteristic curves at different temperatures generated when the simulation model of the power MOSFET of the present invention is used for simulation and transfer characteristic curves actually measured.

4A and 4B are respectively a graph of gate charge characteristics generated when a simulation is performed using the simulation model of the power MOSFET of the present invention and a graph of gate charge characteristics actually measured.

5A and 5B are respectively a graph of the drain-source on-resistance versus temperature plotted when the simulation model of the power MOSFET of the present invention is used for simulation and a graph of the drain-source on-resistance versus temperature plotted when actually measured.

6A and 6B are respectively graphs of the capacitance values of the output power capacitance (Coss) and the feedback capacitance (Crss) plotted against the drain-source voltage when the simulation model of the power metal oxide semiconductor field effect transistor of the present invention is used for simulation, and graphs of the capacitance values of the input power capacitance (Ciss), the output power capacitance (Coss) and the feedback capacitance (Crss) plotted against the drain-source voltage when the actual measurement is performed.

Detailed ways

The following is an explanation of the implementation method of the "simulation method of power metal oxide semiconductor transistor" disclosed in the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention.

It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

FIG. 1 is a flow chart of a simulation using a model of a power metal oxide semiconductor (MOS) transistor according to an embodiment of the present invention.

Referring to FIG. 1 , when a model of a power metal oxide semiconductor (MOS) transistor according to an embodiment of the present invention is used for simulation, at least the following steps are included:

Step S1: using a power MOSFET simulation model to simulate a power MOSFET.

Step S2: inputting a plurality of parameters into a power MOSFET simulation model respectively.

Step S3: Generate a corresponding plurality of simulation results.

The power MOSFET simulation model created in step S1 may include the simulation model 1 of FIG. 2 , and may be used in a simulation such as a SPICE simulation or other simulation programs.

When creating a simulation model of a power MOSFET, it may include providing information indicating, for example, connections between various nodes of the transistor simulation model.

For example, it can provide information indicating the connection between the anode and cathode of a diode simulation model, the base, collector and emitter of a transistor simulation model and each node of the simulation model, and it can also provide information indicating that the nodes of the simulation model correspond to the base, collector and emitter of a power transistor.

In addition, the information of the simulation model of the power metal oxide semiconductor (MOS) transistor of the present invention may include information conforming to the SPICE simulation format. For example, the information used to create the simulation model may be provided to a computer system, and the computer system may receive the information of the simulation model of the power metal oxide semiconductor field effect transistor and use the information to simulate a power transistor.

Further referring to FIG. 2 , it is a structural diagram of a simulation model of a power metal oxide semiconductor field effect transistor according to an embodiment of the present invention.

2 , the present invention provides a simulation model 1 of a power metal oxide semiconductor field effect transistor, including a gate node G, a source node S, a drain node D, a gate resistor Rg, a first voltage-controlled voltage source Es1, a source resistor Rs, a drain resistor Rd, a first table lookup current source G11, a transistor sub-circuit 10 and a breakdown voltage module 12.

The gate resistor Rg is connected between the gate node G and the first node N1, and the first voltage-controlled voltage source Es1 is connected between the gate resistor Rg and the first node N1. Here, the first voltage-controlled voltage source Es1 is used to simulate the gate charge behavior on the gate node G with the first subnet 14 in response to temperature changes.

In detail, the switching rate of power MOSFETs is mainly driven by the charging and discharging of the gate. The smaller the charge (Qg) input to the gate, the faster the switching speed. All power MOSFETs lose energy during the switching process, and this lost energy is converted into heat energy and reduces efficiency. The energy lost during switching is directly related to the switching time, and the switching time is related to the size of the capacitance in the structure, especially the size of the charge (Qgd) between the gate and the drain. Therefore, the gate charge is an important characteristic that determines the switching rate of MOSFETs.

The source resistor Rs is connected between the source node S and the second node N2. On the other hand, the breakdown voltage module 12 is connected between the fourth node N4 between the source node S and the source resistor Rs and between the fifth node N5 between the drain node D and the drain resistor Rd, and is configured to simulate the breakdown voltage effect between the drain node D and the source node S according to a voltage value of the first sub-circuit 14. The breakdown voltage module 12 may include a breakdown diode Dbr and a second voltage-controlled voltage source Esb. The breakdown diode Dbr is connected to the fifth node N5, and the second voltage-controlled voltage source Esb is connected between the breakdown diode Dbr and the fourth node N4. The body diode Dbo is connected between the fourth node N4 and the fifth node N5.

Here, the breakdown voltage between the drain node D and the source node S is the maximum voltage that the drain and source of the power MOSFET can withstand, and is mainly limited by the withstand voltage of the included reverse diode, such as the breakdown diode Dbr.

Specifically, the first subnet 14 includes a current source It, a breakdown resistor Rbr, a temperature effect resistor Rvt and a first DC power supply Vt, the current source It is connected between the sixth node N6 and the seventh node N7, the breakdown resistor Rbr is connected between the seventh node N7 and the eighth node N8, the temperature effect resistor Rvt is connected between the sixth node N6 and the eighth node N8, and the first DC power supply Vt is connected between the sixth node and the temperature effect resistor Rvt.

In this embodiment, the sixth node N6 is connected to the second node N2, and the voltage of the second voltage-controlled voltage source Esb is generated according to the voltages of the seventh node N7 and the eighth node N8. Here, it should be noted that the voltages of the seventh node N7 and the eighth node N8 will be affected by the current source It, the breakdown resistor Rbr, the temperature effect resistor Rvt and the first DC power source Vt, wherein the temperature effect resistor Rvt and the first DC power source Vt are used to achieve the effect of the equivalent breakdown diode Dbr changing with temperature, and the amount of charge (Qgd) between the gate and the drain will also be affected by the temperature change, so the voltage of the first voltage-controlled voltage source Es1 can be generated according to the voltages of the sixth node N6 and the eighth node N8.

On the other hand, the first table lookup current source G11 is connected between the drain node D and the first node N1 and is configured to simulate the equivalent current value generated by the gate-drain capacitance according to the table lookup current value of the second subnet 16 .

When the device density increases, the gate-drain charge, or the feedback capacitance (Reverse Transfer capacitance, Crss for short, also known as the gate-drain capacitance Cgd) will also increase, slowing down the charging and discharging speed of the gate node G and affecting the performance of the device. To increase the current density of the device and maintain the high-frequency characteristics of the device, this Cgd value will be an important parameter.

In order to simulate this parameter, the second subnet 16 includes a second DC power source V11, a capacitor C11, a third voltage-controlled voltage source E11 and a lookup table Table. The second DC power source V11 is connected between the ground terminal and the ninth node N9, the capacitor C11 is connected between the ninth node N9 and the tenth node N10, and the third voltage-controlled voltage source E11 is connected between the tenth node N10 and the ground terminal. The voltage of the third voltage-controlled voltage source E11 is generated according to the voltages of the first node N1 and the fifth node N5.

The table lookup device Table is configured to look up a voltage-current comparison table according to the voltage value of the tenth node N10 to generate a table lookup current value as an equivalent current value generated by the first table lookup current source G11.

In addition, for a power metal oxide semiconductor field effect transistor, the conduction voltage portion of the transistor will be different due to the magnitude of the current generated by the transistor. In order to simulate the behavior of the conduction voltage in the small current interval and the large current interval, a transistor subcircuit 10 is provided, connected to the first node N1, the second node N2 and the third node N3, and the transistor subcircuit 10 includes a first transistor Ms and a second transistor Mw. The gate of the first transistor Ms is connected to the first node, the source is connected to the second node N2, and the drain is connected to the third node N3, which is suitable for simulating the behavior of the conduction voltage in the large current interval. On the other hand, the gate of the second transistor Mw is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3, which is suitable for simulating the behavior of the conduction voltage in the small current interval.

In addition, the power metal oxide semiconductor field effect transistor simulation model 1 also includes a gate inductance circuit 100, connected between the gate node G and the gate resistor Rg, and the gate inductance circuit 100 includes a gate inductance Lg and a gate inductance resistor RLg connected in parallel. Similarly, the power metal oxide semiconductor field effect transistor simulation model 1 also includes a source inductance circuit 102, connected between the source node S and the source resistor Rs, and the source inductance circuit 102 includes a source inductance Ls and a source inductance resistor RLs connected in parallel. Similarly, the power metal oxide semiconductor field effect transistor simulation model 1 also includes a drain inductance circuit 104, connected between the drain node D and the drain resistor Rd, and the drain inductance circuit 104 includes a drain inductance Ld and a drain inductance resistor RLd connected in parallel.

In addition, the power MOSFET simulation model 1 further includes a gate-source capacitor Cgs and a gate-source resistor Rgs. The gate-source capacitor Cgs and the gate-source resistor Rgs are connected between the first node N1 and the second node N2. The drain resistor Rd is connected between the drain node D and the third node N3.

Here, the power MOSFET simulation model 1 has been created and can be used to generate multiple simulation results, such as conduction voltage, on-resistance, body diode including reverse recovery charge, gate charge, input capacitance, output capacitance, feedback capacitance and other electrical characteristic parameters.

The simulation method of the power metal oxide semiconductor (MOS) transistor provided in the above embodiment can reduce the load of the computing system during simulation because fewer components are used in the model of the power metal oxide semiconductor transistor.

In addition, the simulation model of the power metal oxide semiconductor field effect transistor of the present invention has a certain degree of accuracy, and due to the high independence of parameters, multiple parameters can be individually adjusted according to user needs. In addition, the design of the first sub-circuit can respond to temperature changes to provide a function of changing high temperature and low temperature electrical characteristics, and the second sub-circuit can be used to simulate the effect of feedback capacitance, and electrical characteristic parameters such as conduction voltage, on-resistance, body diode with reverse recovery charge, gate charge, input capacitance, output capacitance and feedback capacitance can be obtained without using a high-order parameter model of the metal oxide semiconductor field effect transistor.

Various characteristic curves generated by the simulation method of the power MOSFET of the present invention will be further presented below, and compared with actual measured curves to show that the present invention has a certain degree of accuracy.

Please refer to Figures 3A and 3B, which are respectively transfer characteristic curves at different temperatures generated when the simulation model of the power metal oxide semiconductor field effect transistor of the present invention is used for simulation and transfer characteristic curves actually measured. As shown in the figure, it can be seen that the simulated drain-source current Ids versus gate-source voltage Vgs, i.e., transfer characteristic curves, generated at temperatures of 125°C, 25°C and -20°C, respectively, have the same tendency in the linear region as compared with the transfer characteristic curves actually measured.

Please refer to Figures 4A and 4B, which are respectively a graph of the gate charge characteristic generated when the simulation model of the power metal oxide semiconductor field effect transistor of the present invention is used for simulation and a graph of the gate charge characteristic actually measured. As shown in the figure, the gate charge characteristic obtained by simulation, the trend of the gate-source voltage Vgs in the interval of 1.8nC of the gate-source charge amount Qgs, and the trend of the gate-drain charge amount Qgd in the interval of 5.7nC, are close to the trend of the gate charge characteristic actually measured in the interval of 2nC of the gate-source charge amount Qgs, and the trend of the gate-drain charge amount Qgd in the interval of 5.5nC.

Please refer to FIG5A and FIG5B, which are respectively a graph of the drain-source on-resistance versus interface temperature plotted when the simulation model of the power metal oxide semiconductor field effect transistor of the present invention is used for simulation, and a graph of the drain-source on-resistance versus interface temperature plotted when actually measured. As shown in the figure, in the range of the junction temperature of -50°C to 150°C, the curve trend of the normalized drain-source on-resistance versus interface temperature plot is also the same, and the normalized drain-source on-resistance generated at the junction temperature of -50°C and 150°C is also the same.

Please refer to FIG6A and FIG6B, which are respectively graphs of the output power capacitance (Coss) and the feedback capacitance (Crss) plotted against the drain-source voltage when the simulation model of the power MOSFET of the present invention is used for simulation, and graphs of the actual measured input power capacitance (Ciss), output power capacitance (Coss) and feedback capacitance (Crss) plotted against the drain-source voltage (Vds). Wherein, the input power capacitance (Ciss) represents the gate-source capacitance plus the gate-drain capacitance (Cgs+Cgd), the output power capacitance (Coss) represents the drain-source capacitance plus the gate-drain capacitance (Cds+Cgd), and the feedback capacitance (Crss) represents the gate-drain capacitance (Cgd). As shown in the figure, in the power metal oxide semiconductor field effect transistor simulation model of the present invention, the input power capacitor (Ciss) is set by querying the characteristic table of the corresponding component and is a fixed value. As for the capacitance values of the output power capacitor (Coss) and the feedback capacitor (Crss), the variation trend of the drain-source voltage is the same as the variation trend of the capacitance values of the output power capacitor (Coss) and the feedback capacitor (Crss) with respect to the drain-source voltage in actual measurement. When the drain-source voltage is 0, the corresponding capacitance values of the output power capacitor (Coss) and the feedback capacitor (Crss) are 630pF and 378pF, respectively, which is also consistent with the actual measured values.

Based on the above results, it can be seen that the simulation model parameters of the power MOSFET of the present invention are highly independent, so multiple parameters can be individually adjusted according to user requirements, and the simulation results also have a certain degree of accuracy.

Advantageous Effects of Embodiments

One of the beneficial effects of the present invention is that the simulation method of a power metal oxide semiconductor (MOS) transistor provided by the present invention uses fewer components, thereby reducing the load of the computing system during simulation.

In addition, the simulation model of the power metal oxide semiconductor field effect transistor of the present invention has a certain degree of accuracy, and due to the high independence of parameters, multiple parameters can be individually adjusted according to user needs. In addition, the design of the first sub-circuit can respond to temperature changes to provide a function of changing high temperature and low temperature electrical characteristics, without using a high-order metal oxide semiconductor field effect transistor parameter model.

The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the protection scope of the claims of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention description and drawings are included in the protection scope of the claims of the present invention.

Claims (10)

1. A simulation model of a power mosfet, for measuring a plurality of parameters of the power mosfet to generate a plurality of simulation results, the simulation model of the power mosfet comprising:

A gate node, a source node, and a drain node;

A gate resistor connected between the gate node and a first node;

a first voltage controlled voltage source connected between the gate resistor and a first node configured to simulate a gate charge behavior on the gate node with a first sub-circuit in response to temperature changes;

a source resistor connected between the source node and a second node;

a gate-source capacitance and a gate-source resistance connected between the first node and the second node;

A drain resistor connected between the drain node and a third node;

The first table look-up current source is connected between the drain node and the first node and is used for simulating an equivalent current value generated by a capacitance between a grid and a drain according to a table look-up current value of a second sub-circuit;

A transistor sub-circuit comprising:

a first transistor connected to the first node, the second node and the third node; and

A second transistor connected to the first node, the second node and the third node, wherein the first transistor and the second transistor are used for simulating the behavior of a conductive voltage in a small current interval and a large current interval; and

A breakdown voltage module connected between a fourth node between the source node and the source resistor and a fifth node between the drain node and the drain resistor, the breakdown voltage module being configured to simulate a breakdown voltage effect between the drain node and the source node according to a voltage value of the first sub-circuit;

Wherein the first sub-circuit comprises:

a current source connected between a sixth node and a seventh node;

a breakdown resistor connected between the seventh node and an eighth node;

a temperature effect resistor connected between the sixth node and the eighth node; and

And the first direct current power supply is connected between the sixth node and the temperature effect resistor.

2. The model of claim 1, wherein the sixth node is connected to the second node.

3. The model of claim 1, wherein the voltage of the first voltage controlled voltage source is generated based on the voltages of the sixth node and the eighth node.

4. The simulation model of a power mosfet of claim 1 wherein the breakdown voltage module comprises:

a breakdown diode connected to the fifth node; and

And a second voltage-controlled voltage source connected between the breakdown diode and the fourth node.

5. The model of claim 4, wherein the voltage of the second voltage controlled voltage source is generated based on the voltages of the seventh node and the eighth node.

6. The analog model of a power mosfet of claim 1, wherein the second sub-circuit comprises:

The second direct current power supply is connected between a grounding end and a ninth node;

A capacitor connected between the ninth node and a tenth node;

the third voltage-controlled voltage source is connected between the tenth node and the grounding end, wherein the voltage of the third voltage-controlled voltage source is generated according to the voltages of the first node and the fifth node; and

And the table lookup device is configured to query a voltage-current comparison table according to the voltage value of the tenth node so as to generate the table lookup current value, wherein the first table lookup current source simulates the equivalent current value according to the table lookup current value.

7. The model of claim 1, further comprising a gate inductor circuit connected between the gate node and the gate resistor, the gate inductor circuit comprising a gate inductor and a gate inductor resistor connected in parallel.

8. The model of claim 1, further comprising a source inductor circuit connected between the source node and the source resistor, the source inductor circuit comprising a source inductor and a source inductor resistor connected in parallel.

9. The model of claim 1, further comprising a drain inductor circuit connected between the drain node and the drain resistor, the drain inductor circuit comprising a drain inductor and a drain inductor resistor connected in parallel.

10. The model of claim 1, wherein the parameters include at least one of conduction voltage, on-resistance, body diode with reverse recovery charge, gate charge, input capacitance, output capacitance, and feedback capacitance.