CN112417804A - GaN HEMT zooming model circuit topological structure - Google Patents
GaN HEMT zooming model circuit topological structure Download PDFInfo
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Abstract
The invention discloses a GaN HEMT scaling model circuit topology structure, wherein a grid G, a source S and a drain D of a transistor GH1 are respectively connected with anodes of direct current power sources VG, VS and VD; a gate G, a source S and a drain D of the transistor GH2 are respectively connected with one end of the inductor L2, one end of the inductor L1 and one end of the inductor L3; the other end of the inductor L2 is connected with the anode of a direct current power supply Vgs; the other end of the inductor L1 is connected with the negative electrode of a direct-current power supply V0; the other end of the inductor L3 is connected with the anode of a direct-current power supply Vds; the source S and the drain D of the transistor GH2 are also connected with two ends of the meter base current source. The GaN HEMT scaling model circuit topology structure disclosed by the invention can solve the problems of model precision and ductility and simultaneously meet the temperature change characteristic, thereby realizing higher model precision and meeting the circuit simulation requirement.
Description
Technical Field
The invention relates to the technical field of semiconductor device modeling, in particular to a GaN HEMT scaling model circuit topological structure.
Background
With the deepening of the research level of GaN (gallium nitride) and the improvement of product technology, the reliability of GaN microwave power devices is continuously improved, and the GaN microwave power devices are already in the market from laboratories and are widely applied to the fields of civilian use and national defense.
For the fixed characteristic dimension (gate length) process, as the total output power of a transistor device is in direct proportion to the total gate width of the transistor device, when a microwave millimeter wave GaN circuit is designed, particularly a monolithic microwave integrated circuit is designed, the gate index and the unit gate width scale of a device model need to be optimized and selected so as to realize the best circuit performance. Therefore, the modeling method of the large-signal scalable model has great significance for the development of the GaN circuit.
For a measurement-based large-signal model, due to the limitation of factors such as the highest frequency, the maximum current, the impedance range or the maximum power of the current measurement instrument (or accessory), it is difficult to perform necessary tests on all required device sizes (especially on-chip pulling of large-size devices), and therefore, the scalability of the model is an important modeling means for large-size devices.
The existing models comprise a lookup table model, an empirical model and the like, and each model has advantages and disadvantages.
The lookup table model is based on a large amount of test data, has high precision, but has difficult guarantee on the precision of the prediction data outside the measurement range, and adopts a table form to store the input and output responses of the transistor and the corresponding relation between the parameter value and the external bias voltage. The lookup table model has the advantages that: the method does not need to extract parameters and establish an equivalent circuit, is intuitive and simple, but has the following defects: these relationships are not continuous, require polynomial fitting, and accuracy cannot be guaranteed at transistor model characteristics that are outside the look-up table. In addition, the look-up table model cannot accurately predict the characteristics of transistors such as temperature variation, frequency shift, scaling relationship of devices with different sizes, and as the characteristics of the novel semiconductor compound transistor become more complex, the range and data of the required look-up table are too large, which is not beneficial to simulation. The empirical model has simple parameter extraction and good ductility.
Typically, an empirical model is an equivalent circuit representation of a transistor. Various electrical characteristic measurements are a process of determining transistor characteristic parameters, which are mapped to network element simulation electronics for characteristic analysis. The parameters of the equivalent circuit can be extracted through different measurements, such as current-voltage (I-V) and small signal S parameters. This method, which is practical for small signal models, can form a bias-dependent linear transistor model. And for the large-signal equivalent circuit parameters, fitting needs to be carried out by using a mathematical analytic expression to obtain an equation description of a large-signal model. But the mathematical formula or function itself is meaningless.
In summary, in order to solve the problem of ductility of the model, achieve higher model precision, satisfy characteristics such as temperature variation, and achieve the purpose of more accurate circuit simulation, a new technology is urgently needed to be developed.
Disclosure of Invention
The invention aims to provide a GaN HEMT scaling model circuit topology structure aiming at the technical defects in the prior art.
Therefore, the invention provides a GaN HEMT scaling model circuit topology structure which comprises a direct-current power supply VG, a direct-current power supply VD, a direct-current power supply VS, a transistor GH1, a transistor GH2, an inductor L1, an inductor L2, an inductor L3, a direct-current power supply V0, a direct-current power supply Vgs and a direct-current power supply VDs;
the grid G, the source S and the drain D of the transistor GH1 are respectively connected with the anode of the direct-current power supply VG, the anode of the direct-current power supply VS and the anode of the direct-current power supply VD;
the cathodes of the direct current power supply VG, the direct current power supply VS and the direct current power supply VD are all grounded;
the gate G, the source S and the drain D of the transistor GH2 are respectively connected with one end of the inductor L2, one end of the inductor L1 and one end of the inductor L3;
the other end of the inductor L2 is connected with the anode of a direct current power supply Vgs;
the other end of the inductor L1 is connected with the negative electrode of a direct-current power supply V0;
the other end of the inductor L3 is connected with the anode of a direct-current power supply Vds;
the negative electrode of the direct current power supply Vgs is grounded;
the positive electrodes of the direct current power supplies V0 are respectively connected with the positive electrode of the direct current power supply VD;
the negative electrode of the direct current power supply Vds is connected with the positive electrode of the direct current power supply VS;
the source S and the drain D of the transistor GH2 are also connected with two ends of the meter base current source.
Preferably, the transistor GH1 and the transistor GH2 are both gallium nitride high electron mobility transistor GaN HEMTs.
Preferably, the drain-source current of transistor GH2 is in the opposite direction to the drain-source current of the watch base current source.
Compared with the prior art, the GaN HEMT scaling model circuit topological structure provided by the invention can solve the problems of model precision and ductility and simultaneously meet the temperature change characteristic, thereby realizing higher model precision, meeting the circuit simulation requirement and having great practical significance.
Drawings
Fig. 1 is a structural diagram of a GaN HEMT scaling model circuit topology structure provided in the present invention.
Detailed Description
In order to make the technical means for realizing the invention easier to understand, the following detailed description of the present application is made in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 1, the present invention provides a GaN HEMT scaling model circuit topology, which is a GaN HEMT (HEMT is a high electron mobility transistor) scaling model circuit topology based on a lookup table model and an Angelov model (a model invented by Angelov, a foreign inventor), and includes a dc power source VG, a dc power source VD, a dc power source VS, a transistor GH1, a transistor GH2, an inductor L1, an inductor L2, an inductor L3, a dc power source V0, a dc power source VGs and a dc power source VDs;
the grid G, the source S and the drain D of the transistor GH1 are respectively connected with the anode of the direct-current power supply VG, the anode of the direct-current power supply VS and the anode of the direct-current power supply VD;
the cathodes of the direct current power supply VG, the direct current power supply VS and the direct current power supply VD are all grounded;
the gate G, the source S and the drain D of the transistor GH2 are respectively connected with one end of the inductor L2, one end of the inductor L1 and one end of the inductor L3;
the other end of the inductor L2 is connected with the anode of a direct current power supply Vgs;
the other end of the inductor L1 is connected with the negative electrode of a direct-current power supply V0;
the other end of the inductor L3 is connected with the anode of a direct-current power supply Vds;
the negative electrode of the direct current power supply Vgs is grounded;
the positive electrodes of the direct current power supplies V0 are respectively connected with the positive electrode of the direct current power supply VD;
the negative electrode of the direct current power supply Vds is connected with the positive electrode of the direct current power supply VS;
the source S and the drain D of the transistor GH2 are also connected to two ends of the table-based current source Itbm (Vgs, Vds).
It should be noted that, in the present invention, table-based current source Itbm (Vgs, Vds) represents a look-up table model, which is a form of characterizing the drain current of the GaN HEMT transistor according to an interpolation approximation spline of test data, and forms a difference with the Angelov model represented by GH2 for correcting the drain current of the original Angelov model (GH 1).
In the invention, the direct current power supplies VG, VD and VS are voltage values added at two ends of the tested GaN HEMT device, VG is grid voltage, and the tube is controlled to be opened; VD is leakage voltage, which can enable the tube to form current; VS is grounded. Normally, the voltage values of VG, VD have no fixed values, depending on the test requirements actually applied across the transistor.
Note that, in the present invention, the dc power supplies V0, Vgs, and Vd are used to provide dc bias for the Angelov model represented by GH2 and table-based current source Itbm (Vgs, Vds). Vgs provides gate voltage, and the size of the gate voltage is the same as that of VG; vds provides leakage voltage, and the magnitude of the leakage voltage is the same as that of VD; v0 is a compensation power supply for offsetting the voltage of VD and forming a zero potential.
In the present invention, the transistors GH1 and GH2 represent the same Angelov model, and represent the drain current flowing through the GaN HEMT under test. The inductor L1, the inductor L2, and the inductor L3 function as an ac signal open circuit and a dc signal short circuit.
In the present invention, the transistor GH1 and the transistor GH2 are both gallium nitride high electron mobility transistors (GaN HEMTs).
In the present invention, detailed implementation, referring to fig. 1, the present invention discloses a novel circuit topology with a large signal scaling model that combines a look-up table model and an Angelov model.
In particular, the GaN HEMT scaling model circuit topology structure provided by the present invention is a new scaling model, and the principle is shown in the following formula (1), that is, the circuit topology structure of the present invention needs to satisfy the following formula:
ids — Angelov _2(Vgs, Vds)) (Ids _ Angelov _ I (Vgs, Vds) — α × Itbm (Vgs, Vds));
wherein α ═ α 1 ═ α 2,
formula (2);
in the formula (1), the parameters Ids _ Angelov _2(Vgs, Vds) and Ids _ Angelov _1(Vgs, Vds) represent the same Angelov model, represent the drain-source current flowing through the GaN HEMT, and are empirical models established by extracting empirical parameters according to drain-source current test data of the GaN HEMT test device; the parameter α represents a scaling factor, and the parameter value is obtained by equation (2); the parameter Itbm (Vgs, Vds) is a lookup table model and is obtained according to an interpolation approximation spline of the GaN HEMT test device drain-source circuit test data.
It should be noted that, for the present invention, the model formula combines the advantages of two different models: scalability of the Angelov model and accuracy of the look-up table model. Ids _ Angelov _2(Vgs, Vds) and Ids _ Angelov _1(Vgs, Vds) represent the same Angelov model, wherein the difference formed by the Ids _ Angelov _1(Vgs, Vds) and the lookup table model Itbm (Vgs, Vds) is used for compensating the Ids _ Angelov _2(Vgs, Vds) and completing the correction of the original Angelov model.
In the formula (2), the parameters α 1 and α 2 are normalization factors of the gate index and the single finger gate width, respectively, and the parameter Ng、WgThe grid index and the single finger grid width of the tested GaN HEMT device (namely the tested device); parameter ng、wgThe gate index and the single finger gate width of the GaN HEMT device (i.e., the new device) to be scaled).
It should be noted that, in the present invention, the device under test, that is, the actually tested GaN HEMT device, is the basis for modeling.
The new device is a device to be scaled, and the GaN HEMT device cannot be tested due to the fact that the size of the new device is too large, and the new device is the target of model establishment. The device to be tested in the whole text is the GaN HEMT device to be tested, and the new device is the GaN HEMT device to be scaled.
For the present invention, it should be noted that the whole fig. 1 is a model that can characterize the drain-source current of the GaN HEMT device, and by adjusting the scaling factor α, the drain-source current of the device under test (α ═ 1) can be characterized, and the drain-source current of the new device (device to be scaled) can be characterized.
In particular, the tested device and the new device are GaN HEMT devices with the same grid length and different grid indexes and grid widths. The tested device is a GaN HEMT device which can be actually tested, and a corresponding model is established according to the tested drain-source current data. The new device (GaN HEMT device to be scaled) may then build a corresponding model based on the model formed by the device under test according to a scaling factor with the device under test gate index and gate width.
It should be noted that, for the present invention, it uses a large signal scaling model, and the core of the model is the parallel original Angelov model and the look-up table model (Itbm).
Here, the drain-source current of the original Angelov model Ids _ Angelov _1 (i.e. the drain-source current embodied as transistor GH2) is opposite to the drain-source current direction of table-based current source Itbm (Vgs, Vds), as shown in fig. 1.
For the invention, 3 ideal inductors L1, L2 and L3 are respectively arranged at the grid, the drain and the source of a transistor GH2 core, and are respectively used for AC signal open circuit and DC signal short circuit.
In addition, three power supplies are respectively arranged at a grid electrode, a drain electrode and a power supply terminal of the core of the transistor GH2, and respectively provide direct current power supplies. Unlike the two sources of gate G (i.e., gate) and drain D, the source S source acts as a compensation source and is coupled to the drain dc source of a modified Angelov _1 (embodied in the circuit as transistor GH2) to regulate the core supply voltage, resulting in an active compensation sub-circuit. The topological structure of the active compensation subcircuit is clear, and the elements of the active compensation subcircuit are easy to realize in ADS simulation software.
In the invention, the modeling of the drain-source current employs a look-up table model, which is defined as a function of Vgs and Vds. The look-up table model is based on a piecewise parametric polynomial, approximated by a spline representation of interpolation of the measured data. As can be known from the above equation (1), the active compensation sub-circuit can simulate the difference between the original Angelov model Ids _ Angelov _1 (embodied as the transistor GH2 in the circuit) and the table-based current source Itbm (Vgs, Vds), and when the active compensation sub-circuit is connected in parallel with the original Angelov model, the drain-source current of the original Angelov model can be accurately corrected. Meanwhile, the Angelov model has the characteristics of scaling, self-heating and the like, and when the Angelov model is connected with the lookup table model in parallel, the defects that the lookup table model cannot be scaled and the temperature change can be predicted can be overcome.
In order to more clearly understand the technical solution of the present invention, the following describes the circuit topology of the present invention, and the specific design and specific implementation are as follows:
first, according to formula (2), normalization factors alpha 1 and alpha 2 of grid index and single-finger grid width are determined, wherein N isg、WgIs the gate index and the width of a single finger of the device under test, ng、wgThe gate index and the single finger gate width of the new device.
And secondly, establishing a lookup table model Itbm according to the data of the tested device. The drain-source current is modeled using a look-up table model defined as a function of Vgs and Vds. And the lookup table model is based on the segmented parameter polynomial and is expressed by utilizing interpolation approximation spline of the measured data.
Third, an Angelov _1, Angelov _2 model (embodied in the circuit as transistors GH1 and GH2) is built from the data of the device under test. The Angelov _1 model and the look-up table model (Itbm) are connected in parallel and are the core of the model, but the drain-source current of the Angelov model Ids _ Angelov _1 is opposite to the drain-source current direction of the table base current source Itbm (Vgs, Vds). Then 3 ideal inductors L1, L2 and L3 are respectively arranged at the gate, drain and source of the transistor GH2 core, respectively, for ac signal open circuit and dc signal short circuit. Secondly, 3 direct current power supplies are respectively arranged at a grid electrode, a drain electrode and a power supply terminal of a core of the transistor GH2 and respectively provide the direct current power supplies. Unlike the two sources at the gate and drain, the source acts as the compensation source and is coupled to the drain dc source of the modified Angelov _1 model (embodied as transistor GH2 in the circuit) to regulate the core supply voltage, resulting in an active compensation sub-circuit.
And fourthly, establishing a complete large signal model shown as formula (1) to form the circuit topology structure shown in the figure 1.
Compared with the prior art, the GaN HEMT scaling model circuit topology structure provided by the invention has the following beneficial technical effects:
1. the precision of the scaling model is met;
2. achieving ductility of the model;
3. the model has the characteristic of temperature change;
4. it is easy to integrate with simulation software.
In summary, compared with the prior art, the GaN HEMT scaling model circuit topology structure provided by the invention can solve the problems of model precision and ductility and simultaneously meet the temperature change characteristic, thereby realizing higher model precision, meeting the circuit simulation requirements and having great practical significance.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (3)
1. A GaN HEMT scaling model circuit topology structure is characterized by comprising a direct-current power supply VG, a direct-current power supply VD, a direct-current power supply VS, a transistor GH1, a transistor GH2, an inductor L1, an inductor L2, an inductor L3, a direct-current power supply V0, a direct-current power supply Vgs and a direct-current power supply VDs;
the grid G, the source S and the drain D of the transistor GH1 are respectively connected with the anode of the direct-current power supply VG, the anode of the direct-current power supply VS and the anode of the direct-current power supply VD;
the cathodes of the direct current power supply VG, the direct current power supply VS and the direct current power supply VD are all grounded;
the gate G, the source S and the drain D of the transistor GH2 are respectively connected with one end of the inductor L2, one end of the inductor L1 and one end of the inductor L3;
the other end of the inductor L2 is connected with the anode of a direct current power supply Vgs;
the other end of the inductor L1 is connected with the negative electrode of a direct-current power supply V0;
the other end of the inductor L3 is connected with the anode of a direct-current power supply Vds;
the negative electrode of the direct current power supply Vgs is grounded;
the positive electrodes of the direct current power supplies V0 are respectively connected with the positive electrode of the direct current power supply VD;
the negative electrode of the direct current power supply Vds is connected with the positive electrode of the direct current power supply VS;
the source S and the drain D of the transistor GH2 are also connected with two ends of the meter base current source.
2. The GaN HEMT scaling model circuit topology of claim 1, wherein transistor GH1 and transistor GH2 are both gallium nitride high electron mobility transistor GaN HEMTs.
3. The GaN HEMT scaling model circuit topology of claim 1, wherein the drain-source current of transistor GH2 is in the opposite direction of the drain-source current of the watch-based current source.
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