TW202103040A - Simulation method of power metal oxide semiconductor transistor - Google Patents

Abstract

A simulation model of a power MOSFET for measuring a plurality of parameters of a power MOSFET to respectively generate corresponding plurality of simulation results, the simulation model of the power MOSFET includes a first voltage-controlled voltage source, a first look-up current source, a transistor sub-circuit and a breakdown voltage module. The first voltage-controlled voltage source responds to the temperature change, and uses the first sub-circuit to simulate gate charge behavior on the gate node. The first look-up table current source is configured to simulate an equivalent current value generated by the capacitance between the gate and the drain according to the look-up current value of the second sub-circuit. The transistor sub-circuit is used to simulate the behavior of the conductive voltage in small current intervals and large current intervals. The breakdown voltage module simulates a breakdown voltage effect between a drain node and a source node according to a voltage value of the first sub-circuit.

Description

Simulation Model of Power Metal Oxide Semiconductor Transistor

The invention relates to a simulation model of a power metal oxide semiconductor (MOS) transistor, in particular to a simulation model of a power metal oxide semiconductor (MOS) transistor which can reduce the computational load during simulation.

Electronic components in computers, televisions, cellular phones and many other electronic products. Designers usually use simulator programs to simulate a schematic version of the transistor to observe its circuit behavior.

For the design of complex electronic circuits, simulations are typically performed to verify the functionality of the electronic circuit and to optimize its performance. By simulating the target electronic component, it is expected that the model of the electronic component used in the circuit can be accurately established. In particular, as products change with each passing day, it will consume a lot of human resources and time to measure each parameter characteristic of electronic components. Therefore, it is expected that the accurate model of the power transistor can be directly used for simulation in a time-saving and labor-saving situation, so as to reduce the development time.

In the existing circuit simulation software, many existing transistor simulation models that can simulate power transistors extensively have been provided. However, in some cases, the use of these existing transistor simulation models may lead to inaccurate predictions of the behavior of certain transistor circuits. In addition, the existing transistor simulation models often use a large number of components, which may cause a lot of burden on the computing system.

Therefore, there is an urgent need for a power transistor simulation model that can reduce the number of components used, and reduce the simulation load of the computing system, and at the same time have a certain accuracy.

The technical problem to be solved by the present invention is to provide a simulation model of a power metal oxide semiconductor (MOS) transistor in view of the shortcomings of the prior art.

In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a power metal oxide semiconductor field effect transistor (MOSFET) simulation model for comparing a power metal oxide semiconductor field effect transistor (MOSFET). MOSFET) parameters are measured to generate corresponding simulation results. The simulation model of the power MOSFET includes gate node, source node, drain node, gate resistance, first voltage-controlled voltage source, The source resistance, the capacitance between the gate and the source, the resistance between the gate and the source, the drain resistance, the first look-up current source, the transistor sub-circuit and the breakdown voltage module. The gate resistor is connected between the gate node and a first node, and the first voltage-controlled voltage source is connected between the gate resistor and the first node, and is configured to respond to temperature changes to simulate a gate with a first sub-circuit The behavior of the gate charge on the pole node. The source resistor is connected between the source node and the second node. The capacitance between the gate and the source and the resistance between the gate and the source are connected between the first node and the second node. The drain resistor is connected between the drain node and the third node. The first look-up table current source is connected between the drain node and the first node. The first look-up table current source is used to simulate the equivalent current generated by the capacitance between the gate and the drain according to the look-up current value of the second sub-circuit value. The transistor sub-circuit includes a first transistor and a second transistor. The first transistor is connected to the first node, the second node, and the third node, and the second transistor is connected to the first node, the second node, and the third node. The first transistor and the second transistor are used for Simulate the behavior of a conductive voltage in a small current interval and a large current interval. The breakdown voltage module is connected between the fourth node between the source node and the source resistor and the fifth node between the drain node and the drain resistor, and is configured to simulate according to the voltage value of the first sub-circuit The collapse voltage effect between the drain node and the source node.

One of the beneficial effects of the present invention is that the simulation model of the power metal oxide semiconductor (MOS) transistor provided by the present invention uses fewer components, thereby reducing the load of the computing system during simulation.

In addition, the simulation model using the power MOSFET of the present invention has a certain degree of accuracy, and because of the high parameter independence, it is possible to individually adjust multiple parameters according to user requirements. In addition, the design of the first sub-circuit can respond to temperature changes to provide a change function with high and low temperature electrical characteristics, and there is no need to use high-end MOSFET parameter models.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the provided drawings are only for reference and description, and are not used to limit the present invention.

The following are specific examples to illustrate the implementation of the “simulation method for power metal oxide semiconductor transistors” disclosed in the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual size, and are stated in advance. The following embodiments will further describe the related technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as "first", "second", and "third" may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another, or one signal from another signal. In addition, the term "or" used in this document may include any one or a combination of more of the associated listed items depending on the actual situation.

FIG. 1 is a flowchart of simulation using a model of a power metal oxide semiconductor (MOS) transistor according to an embodiment of the present invention.

Referring to FIG. 1, when using the power metal oxide semiconductor (MOS) transistor model of the embodiment of the present invention for simulation, at least the following steps are included:

Step S1: Use the power MOSFET simulation model to simulate the power MOSFET.

Step S2: Input multiple parameters into the power MOSFET simulation model respectively.

Step S3: Generate multiple corresponding simulation results.

Wherein, the power MOSFET simulation model created in step S1 can include the simulation model 1 of FIG. 2 and can be used in a simulation such as a SPICE simulation or other simulation programs.

When creating a simulation model of a power MOSFET, it may include providing information for indicating connections between various nodes of, for example, a transistor simulation model.

For example, it can provide information about the connection between the anode and cathode of the diode simulation model, the base, collector and emitter of the transistor simulation model, and the various nodes of the simulation model. It can also be used to indicate the simulation. The nodes of the model correspond to the information of the base, collector and emitter of the power transistor.

In addition, the information of the simulation model of the power metal oxide semiconductor (MOS) transistor of the present invention may include information conforming to the SPICE simulation format. For example, the computer system can be provided with information for creating a simulation model, and the computer system can receive the information of the power MOSFET simulation model and use the information to simulate a power transistor.

Further refer to FIG. 2, which is a structural diagram of a simulation model of a power MOSFET according to an embodiment of the present invention.

Referring to FIG. 2, the present invention provides a simulation model 1 of a power MOSFET, which includes a gate node G, a source node S, a drain node D, a gate resistor Rg, a first voltage-controlled voltage source Es1, and a source resistor. Rs, drain resistance Rd, first look-up table current source G11, transistor sub-circuit 10 and breakdown voltage module 12.

The gate resistor Rg is connected between the gate node G and the first node N1, and the first voltage-controlled voltage source Es1 is connected between the gate resistor Rg and the first node N1. Here, the first voltage-controlled voltage source Es1 is used to simulate the gate charge behavior on the gate node G with the first subnet 14 in response to temperature changes.

In detail, the switching rate of the power MOSFET is mainly operated by the charging and discharging of the gate electrode. The smaller the amount of charge (Qg) input by the gate electrode, the faster the switching speed. All power metal oxide half field effect transistors lose energy during the switching process, and this lost energy will be converted into a form of heat energy and reduce the efficiency. The energy lost during switching is directly related to the switching time, and the switching time is related to the size of the capacitance in the structure, especially the amount of charge (Qgd) that exists between the gate and the drain. size. Therefore, the gate charge is an important characteristic that determines the switching rate of the MOSFET.

The source resistor Rs is connected between the source node S and the second node N2. On the other hand, the breakdown voltage module 12 is connected between the fourth node N4 between the source node S and the source resistor Rs, and the fifth node N5 between the drain node D and the drain resistor Rd, and is configured to follow A voltage value of the first sub-circuit 14 simulates the collapse voltage effect between the drain node D and the source node S. The breakdown voltage module 12 may include a breakdown diode Dbr and a second voltage-controlled voltage source Esb. The breakdown diode Dbr is connected to the fifth node N5, and the second voltage-controlled voltage source Esb is connected between the breakdown diode Dbr and the fourth node N4. The body diode Dbo is connected between the fourth node N4 and the fifth node N5.

Here, the breakdown voltage between the drain node D and the source node S is the maximum voltage that the drain and source of the power MOSFET can withstand, and is mainly subject to the contained reverse secondary body, such as breakdown The withstand voltage of the diode Dbr.

Specifically, the first subnet 14 includes a current source It, a breakdown resistance Rbr, a temperature effect resistance Rvt, and a first DC power source Vt. The current source It is connected between the sixth node N6 and the seventh node N7, and the breakdown resistance Rbr is connected between the seventh node N7 and the eighth node N8, the temperature effect resistor Rvt is connected between the sixth node N6 and the eighth node N8, and the first DC power source Vt is connected between the sixth node and the temperature effect resistor Between Rvt.

In this embodiment, the sixth node N6 is connected to the second node N2, and the voltage of the second voltage-controlled voltage source Esb is generated according to the voltages of the seventh node N7 and the eighth node N8. Here, it should be noted that the voltages of the seventh node N7 and the eighth node N8 will be affected by the current source It, the breakdown resistance Rbr, the temperature effect resistance Rvt, and the first DC power supply Vt. The temperature effect resistance Rvt And the first DC power supply Vt is used to equivalently collapse the effect of the temperature change of the diode Dbr, and the amount of charge (Qgd) existing between the gate and the drain will also be affected by the temperature change, so the first The voltage of a voltage-controlled voltage source Es1 can be generated according to the voltages of the sixth node N6 and the eighth node N8.

On the other hand, the first look-up current source G11 is connected between the drain node D and the first node N1, and is configured to simulate the capacitance generation between the gate and the drain according to the look-up current value of the second subnet 16 The equivalent current value.

When the component density increases, the gate-drain charge, or the feedback capacitance (Reverse Transfer capacitance, Crss for short, which is also the gate-drain capacitance Cgd) will also increase, causing the gate node G to charge The discharge speed slows down and affects the performance of the device. To increase the current density of the device and maintain the high frequency characteristics of the device, the Cgd value will be an important parameter.

In order to simulate this parameter, the second subnet 16 includes a second DC power supply V11, a capacitor C11, a third voltage-controlled voltage source E11 and a table lookup device. The second DC power source V11 is connected between the ground terminal and the ninth node N9, the capacitor C11 is connected between the ninth node N9 and the tenth node N10, and the third voltage-controlled voltage source E11 is connected to the tenth node N10 and the ground terminal between. The voltage of the third voltage-controlled voltage source E11 is generated according to the voltages of the first node N1 and the fifth node N5.

The table look-up device Table is configured to look up the voltage and current comparison table according to the voltage value of the tenth node N10 to generate a look-up current value as the equivalent current value generated by the first look-up current source G11.

In addition, for power MOSFETs, the conduction voltage of the transistor is different due to the current generated by the transistor. In order to simulate the behavior of the conductive voltage in the low current interval and the high current interval, a transistor sub-circuit 10 is provided, which is connected to the first node N1, the second node N2, and the third node N3, which includes the first transistor Ms and the third node N3. Two transistor Mw. The gate of the first transistor Ms is connected to the first node, the source is connected to the second node N2, and the drain is connected to the third node N3, which is suitable for simulating the behavior of the conductive voltage in the high current interval. On the other hand, the gate of the second transistor Mw is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3, which is suitable for simulating the behavior of the conductive voltage in the small current interval.

In addition, the power MOSFET simulation model 1 further includes a gate inductance circuit 100 connected between the gate node G and the gate resistance Rg. The gate inductance circuit 100 includes a gate inductance Lg and a gate inductance resistance RLg connected in parallel. Similarly, the power MOSFET simulation model 1 further includes a source inductor circuit 102, which is connected between the source node S and the source resistor Rs. The source inductor circuit 102 includes a source inductor Ls and a source inductor resistor RLs connected in parallel. . Similarly, the power MOSFET simulation model 1 further includes a drain inductance circuit 104 connected between the drain node D and the drain resistance Rd. The drain inductance circuit 104 includes a drain inductance Ld and a drain inductance resistance RLd connected in parallel.

In addition, the power MOSFET simulation model 1 further includes the capacitance Cgs between the gate and the source and the resistance Rgs between the gate and the source. The gate-source capacitance Cgs and the gate-source resistance Rgs are connected between the first node N1 and the second node N2. The drain resistor Rd is connected between the drain node D and the third node N3.

Here, the power MOSFET simulation model 1 has been created, which can be used to generate multiple simulation results, such as conduction voltage, on-resistance, body diode with reverse recovery charge, gate charge, input capacitance, output capacitance and feedback capacitance Isoelectric characteristic parameters.

In the simulation method of the power metal oxide semiconductor (MOS) transistor provided in the above embodiment, since fewer components are used in the model of the power metal oxide semiconductor transistor, the load of the computing system during simulation can be reduced. .

In addition, the simulation model using the power MOSFET of the present invention has a certain degree of accuracy, and because of the high parameter independence, it is possible to individually adjust multiple parameters according to user needs. In addition, the design of the first sub-circuit can respond to temperature changes to provide a change function with high and low temperature electrical characteristics, and the second sub-circuit can be used to simulate the effect of the feedback capacitor without using high-end MOSFET parameter models. Then electrical characteristic parameters such as conduction voltage, on-resistance, body diode with reverse recovery charge, gate charge, input capacitance, output capacitance and feedback capacitance can be obtained.

The following will further present various characteristic curves generated by the simulation method of the power MOSFET of the present invention, and compare them with actual measurement curves to show that the present invention has a certain degree of accuracy.

Please refer to FIG. 3A and FIG. 3B, which are respectively the transfer characteristic curves at different temperatures and the actually measured transfer characteristic curves generated when the simulation model of the power MOSFET of the present invention is used for simulation. As shown in the figure, it can be seen that the simulated drain-source current Ids versus gate-source voltage Vgs, that is, the transfer characteristic curve, and the Compared with the actual measured transfer characteristic curve, the trend of working in the linear region is the same.

Please refer to FIG. 4A and FIG. 4B, which are respectively a graph of the gate charge characteristics generated when the simulation model of the power MOSFET of the present invention is used for simulation and a graph of the actually measured gate charge characteristics. As shown in the figure, the simulated gate charge characteristics, the voltage Vgs between the gate and the source in the gate-source charge Qgs is 1.8nC, and the gate-drain charge Qgd is in the 5.7nC zone The trend is close to the actual measured gate charge characteristics in the gate-source charge Qgs in the 2nC range, and the gate-drain charge Qgd in the 5.5nC range.

Please refer to FIG. 5A and FIG. 5B, respectively, when using the simulation model of the power MOSFET of the present invention for simulation, the generated drain-source on-resistance butting surface temperature plot and the actual measured drain-source on-resistance butt connection Graph of surface temperature mapping. As shown in the figure, in the range of junction temperature from -50°C to 150°C, the curve trend of the drain-source on-resistance versus junction temperature is also the same, and the junction temperature is -50°C and 150°C respectively. When, the normalized on-resistance generated is also the same.

Please refer to FIGS. 6A and 6B, respectively, when the simulation model of the power MOSFET of the present invention is used for simulation, the generated output power capacitor (Coss) and feedback capacitor (Crss) are plotted against the drain-source voltage. Figure, as well as the actual measured input power capacitor (Ciss), output power capacitor (Coss) and feedback capacitor (Crss) capacitance values plotted against the drain-source voltage. Among them, the input power capacitance (Ciss) represents the capacitance between the gate and the source plus the capacitance between the gate and the drain (Cgs+Cgd), and the output power capacitance (Coss) represents the capacitance between the drain and the source plus the capacitance between the gate and the drain (Cds+Cgd), and the feedback capacitor (Crss) represents the capacitance between the gate and drain (Cgd). As shown in the figure, in the power MOSFET simulation model of the present invention, the input power capacitor (Ciss) is set by querying the characteristic table of the corresponding component and is a fixed value. For the output power capacitor (Coss) and feedback capacitor (Crss) In terms of the capacitance value, the change trend of the drain-source voltage is the same as the change trend of the actually measured output power capacitor (Coss) and feedback capacitor (Crss) to the drain-source voltage. When the drain-source voltage is 0, the corresponding capacitance values of the output power capacitor (Coss) and feedback capacitor (Crss) are 630 pF and 378 pF, respectively, which are also consistent with the actual measured values.

Based on the above results, it can be seen that the simulation model parameters of the power MOSFET of the present invention are highly independent, so that multiple parameters can be individually adjusted according to user requirements, and the simulation results also have a certain degree of accuracy.

[Beneficial effects of the embodiment]

One of the beneficial effects of the present invention is that the simulation method for power metal oxide semiconductor (MOS) transistors provided by the present invention uses fewer components, so that the load of the computing system during simulation can be reduced.

In addition, the simulation model using the power MOSFET of the present invention has a certain degree of accuracy, and because of the high parameter independence, it is possible to individually adjust multiple parameters according to user requirements. In addition, the design of the first sub-circuit can respond to temperature changes to provide a change function with high and low temperature electrical characteristics, and there is no need to use high-end MOSFET parameter models.

The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the description and schematic content of the present invention are included in the application of the present invention. Within the scope of the patent.

1: Power MOSFET simulation model G: gate node S: source node D: Drain node Rg: gate resistance Es1: The first voltage-controlled voltage source Rs: source resistance Rd: Drain resistance G11: First look-up table current source 12: Crash voltage module N1: the first node 14: The first subnet N2: second node N3: third node N4: Fourth node N5: fifth node Dbr: breakdown diode Dbo: body diode Esb: second voltage-controlled voltage source It: current source Rbr: breakdown resistance Rvt: temperature effect resistance Vt: First DC power supply N6: sixth node N7: seventh node N8: The eighth node G11: First look-up table current source 16: The second sub-circuit V11: Second DC power supply C11: Capacitance E11: The third voltage-controlled voltage source Table: Checker N9: Ninth node N10: Tenth node 10: Transistor sub-circuit Ms: first transistor Mw: second transistor 100: gate inductance circuit Lg: gate inductance RLg: gate inductance resistance 102: Source inductor circuit Ls: source inductance RLs: source inductance resistance 104: Drain inductance circuit Ld: Drain inductance RLd: Drain inductance resistance Cgs: capacitance between gate and source Rgs: resistance between gate and source Ids: current between drain and source Vgs: voltage between gate and source Qgs: charge between gate and source Qgd: charge between gate and drain Crss: feedback capacitor Coss: output power capacitor

FIG. 1 is a flowchart of a simulation method of a power metal oxide semiconductor (MOS) transistor according to an embodiment of the present invention.

FIG. 2 is a structural diagram of a power MOSFET simulation model according to an embodiment of the present invention.

3A and 3B are respectively the transfer characteristic curve diagrams at different temperatures and the actually measured transfer characteristic curve diagrams generated when the simulation model of the power MOSFET of the present invention is used for simulation.

4A and 4B are respectively a graph of gate charge characteristics and a graph of gate charge characteristics actually measured when the simulation model of the power MOSFET of the present invention is used for simulation.

5A and 5B, respectively, when using the simulation model of the power MOSFET of the present invention for simulation, the generated drain-source on-resistance butt junction temperature graph and the actual measured drain-source on-resistance butt junction temperature Graphs for graphing.

6A and 6B are respectively a graph of the capacitance value of the output power capacitor (Coss) and feedback capacitor (Crss) generated against the drain-source voltage when the simulation model of the power MOSFET of the present invention is used for simulation, and The actual measured input power capacitor (Ciss), output power capacitor (Coss) and feedback capacitor (Crss) capacitance values plotted against the drain-source voltage.

1: Power MOSFET simulation model

G: gate node

S: source node

D: Drain node

Rg: gate resistance

Es1: The first voltage-controlled voltage source

Rs: source resistance

Rd: Drain resistance

G11: First look-up table current source

12: Crash voltage module

N1: the first node

14: The first subnet

N2: second node

N3: third node

N4: Fourth node

N5: fifth node

Dbr: breakdown diode

Dbo: body diode

Esb: second voltage-controlled voltage source

It: current source

Rbr: breakdown resistance

Rvt: temperature effect resistance

Vt: First DC power supply

N6: sixth node

N7: seventh node

N8: The eighth node

G11: First look-up table current source

16: The second sub-circuit

V11: Second DC power supply

C11: Capacitance

E11: The third voltage-controlled voltage source

Table: Checker

N9: Ninth node

N10: Tenth node

10: Transistor sub-circuit

Ms: first transistor

Mw: second transistor

100: gate inductance circuit

Lg: gate inductance

RLg: gate inductance resistance

102: Source inductor circuit

Ls: source inductance

RLs: source inductance resistance

104: Drain inductance circuit

Ld: Drain inductance

RLd: Drain inductance resistance

Cgs: capacitance between gate and source

Rgs: resistance between gate and source

Claims (11)

A simulation model of a power metal oxide semiconductor field effect transistor (MOSFET) for measuring multiple parameters of a power metal oxide semiconductor field effect transistor (MOSFET) to generate corresponding multiple simulation results respectively , The simulation model of the power MOSFET includes: A gate node, a source node and a drain node; A gate resistor connected between the gate node and a first node; A first voltage-controlled voltage source is connected between the gate resistor and a first node, and is configured to respond to temperature changes to simulate a gate charge behavior on the gate node with a first sub-circuit; A source resistor connected between the source node and a second node; A capacitance between the gate and the source and a resistance between the gate and the source are connected between the first node and the second node; A drain resistor connected between the drain node and a third node; A first look-up table current source is connected between the drain node and the first node. The first look-up table current source is used to simulate a gate drain according to a look-up table current value of a second sub-circuit. An equivalent current value generated by the capacitance between electrodes; A transistor sub-circuit, which includes: A first transistor connected to the first node, the second node and the third node; and A second transistor is connected to the first node, the second node, and the third node. The first transistor and the second transistor are used to simulate a conduction voltage in a small current interval and a large current. Behavior in the current range; and A breakdown voltage module is connected between a fourth node between the source node and the source resistance and a fifth node between the drain node and the drain resistance, and is configured to be based on the first A voltage value of a sub-circuit simulates the collapse voltage effect between the drain node and the source node. The simulation model of the power MOSFET as described in item 1 of the scope of patent application, wherein the first sub-circuit includes: A current source connected between a sixth node and a seventh node; A breakdown resistor connected between the seventh node and an eighth node; A temperature effect resistor connected between the sixth node and the eighth node; and A first DC power supply is connected between the sixth node and the temperature effect resistor. According to the power MOSFET simulation model described in item 2 of the scope of patent application, the sixth node is connected to the second node. According to the power MOSFET simulation model described in item 2 of the scope of patent application, the voltage of the first voltage-controlled voltage source is generated based on the voltages of the sixth node and the eighth node. The simulation model of the power MOSFET described in item 2 of the scope of patent application, wherein the breakdown voltage module includes: A breakdown diode, connected to the fifth node; and A second voltage-controlled voltage source is connected between the breakdown diode and the fourth node. According to the power MOSFET simulation model described in item 5 of the scope of patent application, the voltage of the second voltage-controlled voltage source is generated according to the voltage of the seventh node and the eighth node. According to the power MOSFET simulation model described in item 1 of the scope of patent application, the second sub-circuit includes: A second DC power supply connected between a ground terminal and a ninth node; A capacitor connected between the ninth node and a tenth node; A third voltage-controlled voltage source connected between the tenth node and the ground terminal, wherein the voltage of the third voltage-controlled voltage source is generated according to the voltages of the first node and the fifth node; and A look-up meter is configured to look up a voltage and current comparison table based on the voltage value of the tenth node to generate the look-up current value, wherein the first look-up current source simulates the equivalent based on the look-up current value Current value. The simulation model of the power MOSFET described in item 1 of the scope of patent application further includes a gate inductance circuit connected between the gate node and the gate resistor, and the gate inductance circuit includes a gate in parallel. Inductance and a gate inductance and resistance. The simulation model of the power MOSFET described in item 1 of the scope of patent application further includes a source inductance circuit connected between the source node and the source resistance, and the source inductance circuit includes a source in parallel. Inductance and a source inductance and resistance. The simulation model of the power MOSFET described in claim 1 further includes a drain inductance circuit connected between the drain node and the drain resistance, and the drain inductance circuit includes a drain connected in parallel. Inductance and a drain inductance and resistance. The simulation model of the power MOSFET as described in item 1 of the scope of patent application, wherein these parameters include conduction voltage, on-resistance, body diode with reverse recovery charge, gate charge, input capacitance, output capacitance and feedback capacitance. At least one of them.

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