JP2009251862A - Simulation circuit for mos transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the simulation circuit of an MOS (Metal Oxide Semiconductor) transistor for precisely simulating the DC characteristics of the MOS transistor. <P>SOLUTION: A voltage controlled type voltage source EGD1 (10) sets the output voltage V1 of a voltage controlled type voltage source EGD1 (10) so that an inter-drain/source voltage VDS and drain currents ID as a simulation result can be respectively matched with measured inter-drain/source voltage VDS and drain currents ID. Voltage conversion by the voltage controlled type voltage source EGD1 (10) may be achieved by an expression, or may be achieved by referring to a table. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a MOS transistor simulation circuit, and more particularly to a MOS transistor simulation circuit capable of accurately simulating the DC characteristics of a MOS transistor.

  Conventionally, several MOS transistor simulation circuits have been disclosed. For example, FIG. 7 shows an example of a conventional MOS transistor simulation circuit, which is a simulation circuit disclosed by Siliconics.

  The simulation circuit shown in the figure has a gate terminal G (31), a drain terminal D (32), and a source terminal S (33). The gate terminal G (31) is connected to the gate electrode of an N-channel lateral MOSFET (hereinafter abbreviated as “NMOS”) 2 (34). The source terminal S (33) is connected to the source electrode and bulk electrode of the NMOS 2 (34). The drain terminal D (32) is connected to the drain electrode of the NMOS 2 (34) via the drain resistor R2 (35). A gate-source capacitor C2 (36) is connected between the gate terminal G (31) and the source terminal S (33). A body diode D2 (38) is connected between the drain terminal D (32) and the source terminal S (33). A gate electrode of a P-channel lateral MOSFET (hereinafter abbreviated as “PMOS”) 1 (37) is connected to the gate terminal G (31), and a bulk electrode of the PMOS 1 (37) is connected to a drain terminal D (32). ing. The drain electrode and the source electrode of the PMOS 1 (37) are both connected to the source terminal S (33) in order to prevent the parasitic diode of the PMOS 1 (37) from operating.

  In this MOS transistor simulation circuit, the PMOS1 (37) acts only as a feedback capacitor formed between the gate electrode and the drain electrode of the NMOS2 (34), and the DC characteristic is the NMOS2 (34) and the drain resistance R2 ( 35).

FIG. 8 shows another example of a conventional MOS transistor simulation circuit, which is a simulation circuit disclosed by IR.
The MOS transistor simulation circuit shown in FIG. 8 has a gate terminal G (41), a drain terminal D (42), and a source terminal S (43), similarly to the simulation circuit shown in FIG. The gate terminal G (41) is connected to the gate electrode of the NMOS 3 (45) via the gate resistor R3 (44), and the drain terminal D (42) is connected to the drain electrode of the NMOS 3 (45) via the drain resistor R4 (46). The source terminal S (43) is connected to the source electrode of the NMOS 3 (45) via the source resistor R5 (47). A body diode D3 (48) and a resistor R6 (49) are connected in parallel between the drain terminal D (42) and the source terminal S (43). Between the gate electrode and the drain electrode of the NMOS 3 (45), a feedback capacitance simulation circuit CGD1 (50) constituted by a voltage control type voltage source, a current control type current source, a capacitor and the like is connected.

  In the conventional MOS transistor simulation circuit shown in FIG. 8, since the CGD1 (50) acts only as a feedback capacitor of the NMOS 3 (45), the DC characteristics are NMOS 3 (45) and resistors R3 (44), R4 (46), It is determined by R5 (47) and R6 (49).

FIG. 9 shows another example of a conventional MOS transistor simulation circuit, which is a simulation circuit disclosed in Patent Document 1 below. The simulation circuit shown in FIG. 9 has a gate terminal G (51), a drain terminal D (52), and a source terminal S (53), similarly to the simulation circuit disclosed by IR company shown in FIG. The gate electrode G (51) is connected to the gate electrode of the NMOS 4 (55) via the gate resistor R7 (54), and the drain terminal D (52) is connected to the drain electrode of the NMOS 4 (55) via the drain resistor R8 (56). Has been. The source terminal S (53) is connected to the source electrode of the NMOS 4 (55). A gate-source capacitor C3 (57) is connected between the gate electrode and the source electrode of the NMOS 4 (55). A body diode D4 (58) is connected between the drain terminal D (52) and the source terminal S (53). A feedback capacitance simulation circuit CGD2 (59) different from the circuit configuration shown in FIG. 8 is connected between the drain terminal D (52) and the gate electrode of the NMOS 4 (55). Also in the MOS transistor simulated by this MOS transistor simulation circuit, the DC characteristic is determined by the NMOS 4 (55) and the resistors R7 (54) and R8 (56).
JP 2002-163319 A

  By the way, in the conventional MOS transistor simulation circuit (FIGS. 7 to 9) described in the above background art, an equivalent circuit for simulating the feedback capacitance of the MOS transistor is provided between the drain and the gate to improve the simulation accuracy of the transient characteristics. It is improving. In such a simulation circuit (simulation circuits shown in FIGS. 7 to 9), the direct current characteristics indicating the relationship between the drain-source voltage and the drain current when a constant gate voltage is applied have NMOS and NMOS characteristics. It is determined by the resistance value connected in series.

FIG. 10 is a graph showing a comparison between a DC characteristic simulation result in a conventional MOS transistor simulation circuit and an actual measurement result of a vertical MOS transistor.
However, in the comparison between the DC characteristic simulation result in the conventional MOS transistor simulation circuit and the actual measurement result of the vertical MOS transistor (see FIG. 10), when the gate voltage is low, the simulation result almost coincides with the actual measurement value. On the other hand, as the gate voltage becomes higher, the output current more than the actual measurement result flows in the simulation result, and it is clear that there is a big difference between the simulation result and the actual measurement result especially in the saturation region. Yes.

  This is due to the JFET resistance of the internal drift layer of the vertical MOSFET, and this JFET resistance varies depending on the gate-emitter voltage and the collector-emitter voltage. As is apparent from this fact, in the conventional simulation circuit (FIGS. 7 to 9), the change in the JFET resistance cannot be simulated by the parameters provided in the NMOS. There was a problem that it was impossible to simulate DC characteristics with high accuracy.

  The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a MOS transistor simulation circuit capable of accurately simulating the DC characteristics of a MOS transistor.

  In order to solve the above-described problems, a MOS transistor simulation circuit according to the present invention is a MOS transistor simulation circuit having a gate terminal, a drain terminal, and a source terminal, wherein a drain electrode is connected to the drain terminal, and A lateral MOSFET simulation circuit in which a bulk electrode is connected to the source terminal; a body diode in which an anode is connected to the source terminal and a cathode is connected to the drain terminal in parallel with the lateral MOSFET simulation circuit; The resistor connected between the gate terminal and the source terminal is insulated from the input side and the output side, and the voltage at both ends of the resistor is input to obtain a desired voltage of the lateral MOSFET simulation circuit. A voltage-controlled voltage source that is applied between the gate electrode and the source electrode. To.

In the MOS transistor simulation circuit, an element connected between the gate terminal and the source terminal is replaced with a capacitor from the resistor.
In the MOS transistor simulation circuit, a characteristic indicating the relationship between the differential value obtained by differentiating the square root of the drain current with the voltage value between the gate and the source and the voltage value between the gate and the source (hereinafter referred to as “d (√ID ) / D (VGS) −VGS characteristic ”) is determined so that the simulation result matches the measured d (√ID) / d (VGS) −VGS characteristic. It is characterized by defining an expression.

  Furthermore, the present invention provides a semiconductor device simulation circuit that includes an IGBT (Insulated Gate Bipolar Transistor) in the category, in which the MOS transistor simulation circuit is used as a MOS circuit structure simulation circuit on the surface portion.

  As described above, according to the MOS transistor simulation circuit of the present invention, the voltage input to the gate terminal is converted to a desired voltage by the voltage control type voltage source and input to the gate electrode of the lateral MOSFET simulation circuit. Thus, there is an effect that it is possible to provide a MOS transistor simulation circuit in which a DC characteristic simulation result is fitted to an actual measurement result.

  Furthermore, by replacing the resistor (detection resistor) connected in parallel with the voltage-controlled voltage source with a capacitor (detection capacitor), this detection capacitor also acts as a gate capacitance between the gate and source. In addition to the effect of improving the DC characteristics, there is an effect of improving the fitting accuracy of the transient characteristics.

  In addition, by calculating the conversion formula of the gate voltage of the voltage control type voltage source from the actually measured d (√ID) / d (VGS) -VGS characteristic, the simulation circuit of the MOS transistor for fitting the simulation result to the actually measured value can be obtained. There is an effect that can be easily constructed.

  Furthermore, by applying the MOS transistor simulation circuit according to the present invention to the MOS structure simulation circuit of another semiconductor element, the simulation results of the DC characteristics can be obtained for other semiconductor elements such as IGBTs having a MOS structure. There is an effect that the measurement result can be fitted.

  A MOS transistor simulation circuit according to the present invention includes a lateral MOSFET simulation circuit, a voltage control type voltage source connected to the gate electrode of the lateral MOSFET simulation circuit, and an input side of the voltage control voltage source in parallel. A voltage detection device (resistor or capacitor) connected to the gate terminal, and the voltage applied to the gate terminal is changed to a desired voltage by the voltage detection device and the voltage controlled voltage source. By converting and applying to the gate, it is possible to obtain a simulation result of DC characteristics in accordance with the actual measurement result.

The best mode of the MOS transistor simulation circuit of the present invention will be described below in detail in the order of [First Embodiment] to [Fourth Embodiment] with reference to the drawings.
[First Embodiment]
FIG. 1 is a circuit diagram of a MOS transistor simulation circuit according to the first embodiment of the present invention.

In the figure, the MOS transistor simulation circuit of this embodiment first has a gate terminal G (1), a drain terminal D (2), and a source terminal S (3) as terminals.
The drain terminal D (2) is connected to the node N3 (4), and the drain electrode of the NMOS 1 (5) which is a lateral MOSFET simulation circuit is connected to the node N3 (4). The source electrode and bulk electrode of the NMOS 1 (5) are connected to the node N4 (6), and the node N4 (6) is connected to the source terminal S (3). The cathode of the body diode D1 (7) is connected to the node N3 (4), and the anode of the body diode D1 (7) is connected to the node N4 (4).

  The gate terminal G (1) is connected to the node N1 (8). A voltage detection resistor R1 (9) is connected between the node N1 (8) and the node N4 (6). Further, the positive input terminal (+) of the voltage controlled voltage source EGD1 (10) is connected to the node N1 (8), and the negative of the voltage controlled voltage source EGD1 (10) is connected to the node N4 (6). The input terminal (one) is connected. Further, the minus output terminal (−) of the voltage controlled voltage source EGD1 (10) is connected to the node N4 (6), and the plus output terminal (ten) of the voltage controlled voltage source EGD1 (10) is connected to the node. N2 (11). The gate electrode of the lateral MOSFET simulation circuit NMOS1 (5) is connected to the node N2 (11). These lateral MOSFET simulation circuit NMOS1 (5), body diode D1 (7), voltage detection resistor R1 (9), and voltage control type voltage source EGD1 (10), the MOS transistor simulation circuit according to the present invention The whole is composed.

The operating characteristics of the MOS transistor simulation circuit of this embodiment will be described below.
The voltage control type voltage source EGD1 (10) has an input side and an output side insulated from each other, inputs a gate-source voltage VGS between the gate terminal G and the source terminal S, and outputs an arbitrary output voltage V1. . By applying this output voltage V1 between the gate electrode and the source electrode of the lateral MOSFET simulation circuit NMOS1 (5), a drain-source voltage VDS between the drain terminal D and the source terminal S as a simulation result and The drain current ID is determined.

Here, the drain-source voltage VDS and the drain current ID as the above-described simulation results match the measured drain-source voltage VDS and the drain current ID, respectively. By setting the output voltage V1, the actual measurement of the DC characteristic and the simulation result are matched with high accuracy. The voltage conversion by the voltage control type voltage source (10) may be realized by an equation or may be realized by referring to a table.
[Second Embodiment]
FIG. 2 is a circuit diagram of a MOS transistor simulation circuit according to the second embodiment of the present invention. In the figure, the same reference numerals are given to the same parts as those in the MOS transistor simulation circuit (FIG. 1) according to the first embodiment of the present invention, and the description thereof is omitted.

  In the figure, the MOS transistor simulation circuit of this embodiment is a voltage detection resistor R1 connected between a node N1 and a node N4 in the MOS transistor simulation circuit shown in the first embodiment of the present invention. Is replaced with a voltage detection capacitor C1.

The operating characteristics of the MOS transistor simulation circuit of this embodiment will be described below.
Since the voltage detection capacitor C1 (12) also functions as a gate capacitance between the gate and the source that greatly affects the transient characteristics, the capacitor C1 (12) improves the fitting accuracy of the DC characteristics and improves the fitting accuracy of the transient characteristics. Improvements can also be realized.
[Third Embodiment]
The circuit diagram of the MOS transistor simulation circuit according to the third embodiment of the present invention is the same as the MOS transistor simulation circuit according to the first embodiment and the MOS transistor simulation circuit according to the second embodiment. . However, a voltage conversion equation between the input voltage VGB and the output voltage V1 of the voltage control type voltage source EGD1 is derived using the actually measured d (√ID) / (VGS) -VGS characteristic. The derivation method is as follows.

  First, in this MOS transistor simulation circuit, the relationship in the saturation region between the voltage V1 applied between the gate electrode and the source electrode of the lateral MOSFET simulation circuit NMOS1 (5) and the drain current ID is defined by equation (1). The

When d (√ID) / d (V1) is calculated from this equation (1), equation (2) is obtained, and d (√ID) / d (V1) is between the gate electrode and the source electrode of NMOS 1 (5). It is a constant value that does not depend on the voltage V1.

On the other hand, the result of differentiating the drain current ID of the MOS transistor simulation circuit with the voltage VGS between the gate terminal and the source terminal is expressed by the following equation (3).

Equation (4) is derived from Equations (2) and (3).

On the other hand, FIG. 3 is a graph showing the d (√ID) / d (VGS) -VGS characteristic obtained from the measured data. As shown in the figure, the actually measured d (√ID) / d (VGS) -VGS characteristic is a curve having a maximum value. By approximating this curve with a plurality of approximate expressions whose variables are VGS, and substituting this approximate expression into equation (4), the curve between the input voltage VGS and the output voltage V1 of the voltage controlled voltage source EGD1 is obtained. It becomes possible to easily derive the voltage conversion formula.

The graph of FIG. 4 shows the result of comparing the DC characteristics of the simulated circuit in which the voltage conversion equation is derived by the above method with the actual measurement value and the simulation value. FIG. 4 is a graph showing the direct current characteristics of the simulation circuit from which the voltage conversion equation is derived by comparing the measured value with the simulated value. It can be understood that the error between the actual measurement and the simulation is considerably reduced in the region of high VG (high gate voltage) as compared with the case where voltage conversion is not performed.
[Fourth Embodiment]
The first to third embodiments are embodiments related to the MOS transistor simulation circuit. However, in this embodiment, the MOS transistor simulation circuit according to the present invention is replaced with another semiconductor element having a MOS structure. (Here, it is applied to IGBT (Insulated Gate Bipolar Transistor)). First, a general equivalent circuit of an IGBT is shown in FIG.

  FIG. 5 is a general equivalent circuit of an IGBT. The surface structure of the IGBT has a MOS structure, and the IGBT simulation circuit is configured by combining a MOS transistor simulation circuit and a BJT (bipolar junction transistor) simulation circuit.

FIG. 6 is a circuit diagram of an IGBT simulation circuit according to the fourth embodiment of the present invention.
As shown in the figure, the MOS transistor simulation circuit according to the present invention is applied to the MOS transistor portion (lateral MOSFET simulation circuit NMOS5 (24)) in the IGBT simulation circuit.

  As a result, it is possible to improve the accuracy of the direct current characteristics as compared with conventional IGBT simulation circuits.

  The present invention provides a MOS transistor simulation circuit capable of simulating suitable DC characteristics in a simulation using a simulator such as SPICE (Simulation Program Integrated Circuit Emphasis) of a semiconductor element such as an IGBT having a MOS transistor and a MOS transistor structure, The present invention can be applied to the construction of a simulation circuit of a semiconductor element such as an IGBT having a MOS transistor structure.

FIG. 3 is a circuit diagram of a MOS transistor simulation circuit according to the first embodiment of the present invention. It is a circuit diagram of the simulation circuit of the MOS transistor which concerns on the 2nd Embodiment of this invention. It is a graph which shows the d (√ID) / d (VGS) -VGS characteristic calculated | required from actual measurement data. It is the graph which showed the direct-current characteristic of the simulation circuit which derived | led-out the voltage conversion type | formula by the comparison with an actual value and a simulation value. This is a general equivalent circuit of an IGBT. It is a circuit diagram of the simulation circuit of IGBT which concerns on the 4th Embodiment of this invention. It is an example of a conventional MOS transistor simulation circuit, and is a simulation circuit disclosed by Siliconics. It is another example of a conventional MOS transistor simulation circuit, and is a simulation circuit disclosed by IR. Another example of a conventional MOS transistor simulation circuit is shown, which is a simulation circuit disclosed in Patent Document 1. It is a graph which shows the comparison with the DC characteristic simulation result in the simulation circuit of the conventional MOS transistor, and the actual measurement result of a vertical MOS transistor.

Explanation of symbols

1 Gate terminal G
2 Drain terminal D
3 Source terminal S
4 Node N3
5 NMOS1
6 Node N4
7 Body diode 8 Node N1
9 Resistance R1 for voltage detection
10 Voltage controlled voltage source EGD1
11 Node N2
12 Voltage detection capacitor C1
21 Gate terminal G
22 Collector terminal C
23 Emitter terminal 24 NMOS5
25 Bipolar Transistor (pnp-Tr1)
26 Resistance R1 for voltage detection
27 Voltage controlled voltage source EGD1

Claims (4)

In a simulated circuit of a MOS transistor having a gate terminal, a drain terminal, and a source terminal,
A lateral MOSFET simulation circuit in which a drain electrode is connected to the drain terminal, and a source electrode and a bulk electrode are connected to the source terminal;
A body diode having an anode connected to the source terminal and a cathode connected to the drain terminal in parallel with the lateral MOSFET simulation circuit;
A resistor connected between the gate terminal and the source terminal;
A voltage-controlled voltage source that is insulated between the input side and the output side, and that applies a voltage across the resistor as an input to apply a desired voltage between the gate electrode and the source electrode of the lateral MOSFET simulation circuit;
A MOS transistor simulation circuit comprising:   2. The MOS transistor simulation circuit according to claim 1, wherein an element connected between the gate terminal and the source terminal is replaced with a capacitor from the resistor.   The simulation result of the characteristics showing the relationship between the differential value obtained by differentiating the square root of the drain current with the voltage value between the gate and the source and the voltage value between the gate and the source shows 2. A conversion equation for determining a voltage of a voltage-controlled voltage source is defined so as to coincide with a characteristic indicating a relationship between a differential value differentiated by a value and a voltage value between the gate and the source. The simulation circuit of the MOS transistor according to claim 2.   4. A semiconductor device simulation circuit including an IGBT in a category, wherein the MOS transistor simulation circuit according to claim 1 is used as a MOS circuit structure simulation circuit on a surface portion.