JP2010257174A - Igbt transient characteristics simulation circuit - Google Patents
Igbt transient characteristics simulation circuit Download PDFInfo
- Publication number
- JP2010257174A JP2010257174A JP2009105886A JP2009105886A JP2010257174A JP 2010257174 A JP2010257174 A JP 2010257174A JP 2009105886 A JP2009105886 A JP 2009105886A JP 2009105886 A JP2009105886 A JP 2009105886A JP 2010257174 A JP2010257174 A JP 2010257174A
- Authority
- JP
- Japan
- Prior art keywords
- current
- electrode
- model
- igbt
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 27
- 230000001052 transient effect Effects 0.000 title claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000005259 measurement Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 6
- 239000000969 carrier Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002123 temporal effect Effects 0.000 description 2
- 238000003079 width control Methods 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Abstract
Description
本発明は、MOSFET(Metal Oxide Semiconductor Field Effect Transistor：MOS型電界効果トランジスタ)及びIGBT(Insulated Gate Bipolar Transistor：絶縁ゲートバイポーラトランジスタ)等の半導体素子のSPICE(Simulation Program with Integrated Circuit Emphasis)などのシミュレータによるシミュレーションにおいて、好適な過渡特性をシミュレーションできる簡便なIGBTの過渡特性シミュレーション回路(IGBTモデル)に関する。 The present invention is based on a simulator such as a SPICE (Simulation Program with Integrated Circuit Emphasis) of a semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor). The present invention relates to a simple IGBT transient characteristic simulation circuit (IGBT model) that can simulate suitable transient characteristics in simulation.
図４は、IGBTの基本構造を示す図である。また図５は、一般的に用いられるIGBT等価回路の回路構成を示す図である。IGBTは図４に示すように、Nch型MOSFET41とPNP型BJT(Bipolar Junction Transistor：バイポーラトランジスタ)42の複合素子である。Nch型MOSFET41では、ドレインはN-層でPNP型BJT42のベースに、ソースはN+層でIGBTのエミッタ端子Eに、ゲートはIGBTのゲート端子Gにそれぞれ接続され、PNP型BJT42では、エミッタはP+層でIGBTのコレクタ端子Cに、エミッタはP層でIGBTのエミッタ端子Eに、ベースはN-層でNch型MOSFETのドレインにそれぞれ接続されている。これを等価回路で示すと図５となる。 FIG. 4 is a diagram showing a basic structure of the IGBT. FIG. 5 is a diagram showing a circuit configuration of a commonly used IGBT equivalent circuit. As shown in FIG. 4, the IGBT is a composite element of an Nch type MOSFET 41 and a PNP type BJT (Bipolar Junction Transistor) 42. In the Nch-type MOSFET 41, the drain is connected to the base of the PNP-type BJT42 in the N-layer, the source is connected to the emitter terminal E of the IGBT in the N + layer, and the gate is connected to the gate terminal G of the IGBT, and in the PNP-type BJT42, the emitter is P + The layer is connected to the collector terminal C of the IGBT, the emitter is connected to the emitter terminal E of the IGBT in the P layer, and the base is connected to the drain of the Nch-type MOSFET in the N− layer. This is shown by an equivalent circuit in FIG.
図５に示す等価回路の回路構成において、IGBTの過渡特性をシミュレーションすると、ターンON特性は表現できるが、ターンOFF特性は表現できない。この理由は、IGBT特有の特性であるテイル電流が表現できないからである。 In the circuit configuration of the equivalent circuit shown in FIG. 5, when the transient characteristics of the IGBT are simulated, the turn-on characteristics can be expressed, but the turn-off characteristics cannot be expressed. This is because the tail current, which is a characteristic unique to IGBTs, cannot be expressed.
図６は、IGBTのターンOFF波形を示す図である。図６に示すように、IGBTの実測の波形（図６に示す実線）に対し、図５に示すMOSFET＋BJTからなるモデルのシミュレーション波形（図６に示す破線）は、テイル電流が考慮されていない分だけ波形が異なっている。 FIG. 6 is a diagram showing an IGBT turn-off waveform. As shown in FIG. 6, the simulation waveform (broken line shown in FIG. 6) of the model consisting of MOSFET + BJT shown in FIG. 5 does not take into account the tail current in contrast to the actually measured waveform of IGBT (solid line shown in FIG. 6). Only the waveforms are different.
図７でも説明するが、これは、IGBTのターンON時にN-層は過剰キャリアに満たされ（高注入状態）蓄積した少数キャリアである正孔が、ターンOFF時にN-層から掃きだされ、もしくは電子対と再結合し消滅するためと考えられている。図７は、ターンON、OFF時のIGBT内部のキャリアの動作を示す図である。すなわち図７(ａ)は、ターンON状態を示しており、図７(ｂ)は、ターンOFF直後の状態を示している。そのターンOFF過程において正孔の処理のために流れる電流をテイル電流と呼ぶようにしている。 As will be described in FIG. 7, the N-layer is filled with excess carriers when the IGBT is turned on (high injection state), and the accumulated minority carriers are swept away from the N-layer when the turn is turned off. Or it is thought to recombine with the electron pair and disappear. FIG. 7 is a diagram showing the operation of the carriers inside the IGBT when the turn is ON and OFF. That is, FIG. 7 (a) shows a turn-on state, and FIG. 7 (b) shows a state immediately after the turn-off. In the turn-off process, the current that flows for hole processing is called tail current.
図５に示すMOSFET＋BJTモデルのテイル電流を表現できない問題を解決するため、従来から各種モデルが提案されている。これまでに提案されたモデルのなかで、下記特許文献１に示されたモデルは、図８に示すようにIGBT内のBJT42のベースとコレクタ間にテイル電流発生回路80を付加することで、ターンOFF波形を表現する。このテイル電流発生回路80は、電流検出回路(ブロックA)81、経時変化検出回路(ブロックB)82、時間幅制御回路(ブロックC)83および増幅回路(ブロックD)84の４つのブロックで構成される。電流検出回路(ブロックA)81は電流検出用電圧源V1および電流制御型電圧源E1で、また経時変化検出回路(ブロックB)82はコンデンサC3、抵抗R1および検波用ダイオードD1で、また時間幅制御回路(ブロックC)83は抵抗R2およびコンデンサC4で、また増幅回路(ブロックD)84は電圧制御型電圧源E2、抵抗R3,R4およびNPN型BJT Q1で、それぞれ構成される。これら各回路ブロック内の素子のパラメータを調整することで、実測を模擬したテイル電流を発生させ、IGBTのターンOFF波形を表現する。 In order to solve the problem that the tail current of the MOSFET + BJT model shown in FIG. 5 cannot be expressed, various models have been proposed. Among the models proposed so far, the model shown in the following Patent Document 1 has a tail current generating circuit 80 between the base and collector of the BJT 42 in the IGBT as shown in FIG. Express an OFF waveform. This tail current generation circuit 80 is composed of four blocks: a current detection circuit (block A) 81, a temporal change detection circuit (block B) 82, a time width control circuit (block C) 83, and an amplification circuit (block D) 84. Is done. The current detection circuit (block A) 81 is the current detection voltage source V1 and the current control type voltage source E1, and the aging detection circuit (block B) 82 is the capacitor C3, the resistor R1, the detection diode D1, and the time width. The control circuit (block C) 83 includes a resistor R2 and a capacitor C4, and the amplifier circuit (block D) 84 includes a voltage control type voltage source E2, resistors R3 and R4, and an NPN type BJT Q1. By adjusting the parameters of the elements in each of these circuit blocks, a tail current that simulates actual measurement is generated, and an IGBT turn-off waveform is expressed.
図５に示す一般的なIGBTモデル(IGBTの過渡特性シミュレーション回路)では、過渡特性をシミュレーションすると、ターンON特性は表現できるが、ターンOFF特性はIGBT特有の特性であるテイル電流が再現できないために実際の特性を表現できないという課題があった。 In the general IGBT model (IGBT transient characteristics simulation circuit) shown in FIG. 5, when the transient characteristics are simulated, the turn-on characteristics can be expressed, but the turn-off characteristics cannot reproduce the tail current, which is a characteristic peculiar to IGBTs. There was a problem that actual characteristics could not be expressed.
この課題を解決するために特許文献１に開示された図８に示すIGBTモデル(IGBTの過渡特性シミュレーション回路)は、IGBT内PNP型BJT42のベースとコレクタ間にテイル電流発生回路80を付加することで、ターンOFF時のテイル電流を表現している。このテイル電流発生回路80は電流検出回路81、経時変化検出回路82、時間幅制御回路83および増幅回路84の４つのブロックで構成している。実際にIGBTモデルを作成する場合、IGBTの実測結果からテイル電流発生回路80内の各回路ブロックにおける素子のパラメータを決める。この素子数が多いため、テイル電流発生回路内の各回路ブロックにおける素子のパラメータを決定するのに、多くの時間がかかる。つまりテイル電流発生回路が複雑で、回路内の素子の数が多いため、従来のIGBTモデルではターンOFF時のテイル電流は表現できるが、各パラメータを決定してモデルを作成するために多くの時間がかかるという課題があった。 In order to solve this problem, the IGBT model (IGBT transient characteristic simulation circuit) shown in FIG. 8 disclosed in Patent Document 1 adds a tail current generating circuit 80 between the base and collector of the PNP type BJT 42 in the IGBT. The tail current at turn-off is expressed. The tail current generating circuit 80 is composed of four blocks: a current detecting circuit 81, a temporal change detecting circuit 82, a time width control circuit 83, and an amplifier circuit 84. When an IGBT model is actually created, element parameters in each circuit block in the tail current generation circuit 80 are determined from the actual measurement result of the IGBT. Since the number of elements is large, it takes a lot of time to determine the parameters of the elements in each circuit block in the tail current generating circuit. In other words, because the tail current generation circuit is complex and the number of elements in the circuit is large, the tail current at turn-off can be expressed with the conventional IGBT model, but it takes a lot of time to determine each parameter and create the model. There was a problem that it took.
そこで本発明は、IGBTの過渡特性を精度良くシミュレーションできる簡便なIGBTの過渡特性シミュレーション回路を提供することを目的とする。 Therefore, an object of the present invention is to provide a simple IGBT transient characteristic simulation circuit capable of accurately simulating the transient characteristic of an IGBT.
請求項１記載の発明は、ゲート端子、エミッタ端子、コレクタ端子を有するIGBTの過渡特性シミュレーション回路であって、ソース電極及びバルク電極が前記エミッタ端子に、ゲート電極が前記ゲート端子に、ドレイン電極がPNP型BJTモデルのベース電極に接続されるNch型MOSFETモデルと、コレクタ電極が前記エミッタ端子に、エミッタ電極が前記コレクタ端子に接続されるPNP型BJTモデルと、前記PNP型BJTモデルのコレクタ端子に流れる電流を入力として、任意の電流を前記Nch型MOSFETモデルのドレイン電極−ソース電極間に出力する電流制御型電流源と、を備えることを特徴としている。 The invention according to claim 1 is an IGBT transient characteristic simulation circuit having a gate terminal, an emitter terminal, and a collector terminal, wherein a source electrode and a bulk electrode are on the emitter terminal, a gate electrode is on the gate terminal, and a drain electrode is on Nch-type MOSFET model connected to the base electrode of the PNP-type BJT model, PNP-type BJT model with the collector electrode connected to the emitter terminal, the emitter electrode connected to the collector terminal, and the collector terminal of the PNP-type BJT model And a current control type current source that outputs an arbitrary current between the drain electrode and the source electrode of the Nch type MOSFET model using a flowing current as an input.
請求項２記載の発明は、請求項１記載のIGBTの過渡特性シミュレーション回路において、前記電流制御型電流源は、抵抗、コンデンサ、前記PNP型BJTモデルのコレクタ電極に流れる電流と同じ電流を前記抵抗の両端に流す第１の電流制御型電流源、および、前記コンデンサに流れる電流と同じ電流を前記Nch型MOSFETモデルのドレイン電極−ソース電極間に流す第２の電流制御型電流源を備え、前記抵抗、コンデンサ、第１の電流制御型電流源、および、第２の電流制御型電流源を並列に接続したことを特徴としている。 According to a second aspect of the present invention, in the IGBT transient characteristic simulation circuit according to the first aspect, the current control type current source has a resistance, a capacitor, and the same current as the current flowing through the collector electrode of the PNP type BJT model. A first current control type current source that flows between both ends of the Nch type MOSFET model, and a second current control type current source that flows the same current as the current flowing through the capacitor between the drain electrode and the source electrode of the Nch type MOSFET model, A resistor, a capacitor, a first current control type current source, and a second current control type current source are connected in parallel.
請求項３記載の発明は、請求項１または請求項２記載のIGBTの過渡特性シミュレーション回路において、前記Nch型MOSFETモデルのゲート電極−ドレイン電極間の電圧を入力として、任意の電流を前記Nch型MOSFETモデルのゲート電極−ドレイン電極間に出力する電圧制御型電流源を更に備えることを特徴としている。 According to a third aspect of the present invention, in the IGBT transient characteristic simulation circuit according to the first or second aspect, a voltage between the gate electrode and the drain electrode of the Nch type MOSFET model is inputted and an arbitrary current is inputted to the Nch type. A voltage-controlled current source that outputs between the gate electrode and the drain electrode of the MOSFET model is further provided.
本発明によれば、IGBTモデルにおいてNch型MOSFETモデルのドレイン電極−ソース電極間に電流制御型電流源を付加することでテイル電流を表現でき、ターンOFF時の動作をシミュレーションで実現できる。 According to the present invention, the tail current can be expressed by adding a current control type current source between the drain electrode and the source electrode of the Nch type MOSFET model in the IGBT model, and the operation at the time of turn-off can be realized by simulation.
さらに、抵抗、コンデンサ、PNP型BJTモデルのコレクタ電極に流れる電流と同じ電流を前記抵抗の両端に流す電流制御型電流源、および、前記コンデンサに流れる電流と同じ電流をNch型MOSFETモデルのドレイン電極−ソース電極間に流す電流制御型電流源を並列に接続してなるテイル電流発生回路を備えることにより、前記容量に蓄積される電荷の充放電の電流でテイル電流を模擬でき、且つ短時間で簡便にIGBTモデルのパラメータを決定することが可能である。 Furthermore, a resistor, a capacitor, a current control type current source that flows the same current as the current flowing through the collector electrode of the PNP type BJT model across the resistor, and a drain electrode of the Nch type MOSFET model that supplies the same current as the current flowing through the capacitor -By providing a tail current generation circuit formed by connecting in parallel a current-controlled current source that flows between source electrodes, the tail current can be simulated with the charge / discharge current of the charge accumulated in the capacitor, and in a short time It is possible to easily determine the parameters of the IGBT model.
またNch型MOSFETモデルのゲート電極−ドレイン電極間に電圧制御型電流源を付加することで、MOSFETやIGBTのスイッチング時に大きな影響を与えるゲート電極−ドレイン電極間容量を調節することができ、さらに実測結果との差を低減することが可能である。 In addition, by adding a voltage-controlled current source between the gate electrode and drain electrode of the Nch MOSFET model, it is possible to adjust the capacitance between the gate electrode and drain electrode, which has a large effect when switching MOSFETs and IGBTs. It is possible to reduce the difference from the result.
以下、本発明の実施の形態について、詳細に説明する。
［実施形態１］
図１は、本発明の第１の実施形態に係るIGBTモデル(IGBTの過渡特性シミュレーション回路)の回路構成を示す図である。図１(ａ)に示すIGBTモデルは、IGBTとしての動作模擬を行うため、ゲート端子G、エミッタ端子E、コレクタ端子Cを有している。
Hereinafter, embodiments of the present invention will be described in detail.
[Embodiment 1]
FIG. 1 is a diagram showing a circuit configuration of an IGBT model (an IGBT transient characteristic simulation circuit) according to the first embodiment of the present invention. The IGBT model shown in FIG. 1A has a gate terminal G, an emitter terminal E, and a collector terminal C in order to simulate operation as an IGBT.
そしてNch型MOSFETモデル11はソース電極S1及びバルク電極B1がエミッタ端子Eに接続され、ドレイン電極D1がPNP型BJTモデル12のベース電極B2に接続され、ゲート電極G1がゲート端子Gと接続されている。 In the Nch MOSFET model 11, the source electrode S1 and the bulk electrode B1 are connected to the emitter terminal E, the drain electrode D1 is connected to the base electrode B2 of the PNP BJT model 12, and the gate electrode G1 is connected to the gate terminal G. Yes.
PNP型BJTモデル12はコレクタ電極C2がエミッタ端子Eに接続され、エミッタ電極E2がコレクタ端子Cに接続され、ベース電極B2はNch型MOSFETモデル11のドレイン電極D1に接続されている。 In the PNP type BJT model 12, the collector electrode C2 is connected to the emitter terminal E, the emitter electrode E2 is connected to the collector terminal C, and the base electrode B2 is connected to the drain electrode D1 of the Nch type MOSFET model 11.
電流制御型電流源F1（13）はNch型MOSFETモデル11のドレイン電極D1−ソース電極S1間に接続されている。電流制御型電流源F1（13）は、PNP型BJTモデル12のコレクタ電極C2に流れる電流を入力とすることで、IGBTのターンON、ターンOFF状態を検知し、それを受けて任意の電流をNch型MOSFETモデル11のドレイン電極D1−ソース電極S1間に出力することでテイル電流を模擬でき、図１(ｂ)に示すようにシミュレーション結果を精度良く実測と一致させることが可能となる。図１(ｂ)においては、IGBTの実測の波形を太実線で示し、本発明の第１の実施形態に係るIGBTモデルのシミュレーション波形を細実線で示し、また、本発明の第１の実施形態に係るIGBTモデルから上述の電流制御型電流源F1（13）を省いたIGBTモデルのシミュレーション波形を細破線で示している。 The current control type current source F1 (13) is connected between the drain electrode D1 and the source electrode S1 of the Nch type MOSFET model 11. The current control type current source F1 (13) detects the turn-on / turn-off state of the IGBT by inputting the current flowing through the collector electrode C2 of the PNP-type BJT model 12, and receives it to generate an arbitrary current. By outputting between the drain electrode D1 and the source electrode S1 of the Nch type MOSFET model 11, the tail current can be simulated, and the simulation result can be matched with the actual measurement with high accuracy as shown in FIG. In FIG. 1 (b), the measured waveform of the IGBT is shown by a thick solid line, the simulation waveform of the IGBT model according to the first embodiment of the present invention is shown by a thin solid line, and the first embodiment of the present invention is also shown. The simulation waveform of the IGBT model in which the above-described current control type current source F1 (13) is omitted from the IGBT model according to FIG.
このように本発明の第１の実施形態に係るIGBTモデルでは、Nch型MOSFETモデル11のドレイン電極−ソース電極間に任意の電流を出力する電流制御型電流源13の入力電流をIGBT内BJTモデル12のコレクタ端子に流れる電流値とすることで、IGBTのターンON状態とターンOFF状態を正確に判断し、N-層に蓄積される過剰キャリアの状態を表現できるようにしたものである。
［実施形態２］
図２は、本発明の第２の実施形態に係るIGBTモデル(IGBTの過渡特性シミュレーション回路)の回路構成を示す図である。このIGBTモデルは同図に示すように、ゲート端子G、エミッタ端子E、コレクタ端子Cを有している。
As described above, in the IGBT model according to the first embodiment of the present invention, the input current of the current control type current source 13 that outputs an arbitrary current between the drain electrode and the source electrode of the Nch type MOSFET model 11 is used as the BJT model in the IGBT. By using the value of the current flowing through the 12 collector terminals, it is possible to accurately determine the turn-on and turn-off states of the IGBT and express the state of excess carriers accumulated in the N-layer.
[Embodiment 2]
FIG. 2 is a diagram showing a circuit configuration of an IGBT model (an IGBT transient characteristic simulation circuit) according to the second embodiment of the present invention. This IGBT model has a gate terminal G, an emitter terminal E, and a collector terminal C as shown in FIG.
Nch型MOSFETモデル11はソース電極S1及びバルク電極B1がエミッタ端子Eに接続され、ドレイン電極D1がPNP型BJTモデル12のベース電極B2に接続され、ゲート電極G1がゲート端子Gと接続されている。 In the Nch MOSFET model 11, the source electrode S1 and the bulk electrode B1 are connected to the emitter terminal E, the drain electrode D1 is connected to the base electrode B2 of the PNP BJT model 12, and the gate electrode G1 is connected to the gate terminal G. .
PNP型BJTモデル12はコレクタ電極C2がエミッタ端子Eに接続され、エミッタ電極E2がコレクタ端子Cに接続され、ベース電極B2はNch型MOSFETモデル11のドレイン電極D1に接続されている。 In the PNP type BJT model 12, the collector electrode C2 is connected to the emitter terminal E, the emitter electrode E2 is connected to the collector terminal C, and the base electrode B2 is connected to the drain electrode D1 of the Nch type MOSFET model 11.
そして図１に示した電流制御型電流源F1の具体的な構成として、第１及び第２の電流制御型電流源14,17と抵抗R5（15）と容量C5（16）が並列に接続された回路を設けている。第１の電流制御型電流源F2（14）の入力電流は、PNP型BJTモデル12のコレクタ電極C2に流れる電流である。第１の電流制御型電流源F2（14）から電流が流れることで、容量C5（16）に電荷が蓄積され、その充放電の電流を第２の電流制御型電流源F3（17）により、Nch型MOSFETモデル11のドレイン電極D1−ソース電極S1間に流すことでテイル電流を模擬する。この抵抗R5（15）と容量C5（16）のパラメータを調整することで短時間にテイル電流を模擬でき、シミュレーション結果を精度良く実測と一致させることが可能となる。
［実施形態３］
図３は、本発明の第３の実施形態に係るIGBTモデル(IGBTの過渡特性シミュレーション回路)の回路構成を示す図である。本発明の第３の実施形態に係るIGBTモデルは、図２に示した第２の実施形態に係るIGBTモデルの回路構成で、Nch型MOSFETモデル11のゲート電極G1−ドレイン電極D1間に電圧制御型電流源GV1（18）を付加したモデルである。本発明の第３の実施形態に係るIGBTモデルは、図２に示した第２の実施形態に係るIGBTモデルの回路構成と基本的には同じであるため、回路構成として付加された構成部分についてのみ説明する。
As a specific configuration of the current control type current source F1 shown in FIG. 1, first and second current control type current sources 14, 17 are connected in parallel with a resistor R5 (15) and a capacitor C5 (16). A circuit is provided. The input current of the first current control type current source F2 (14) is a current flowing through the collector electrode C2 of the PNP type BJT model 12. As current flows from the first current control type current source F2 (14), electric charge is accumulated in the capacitor C5 (16), and the charge / discharge current is supplied by the second current control type current source F3 (17). The tail current is simulated by flowing between the drain electrode D1 and the source electrode S1 of the Nch MOSFET model 11. By adjusting the parameters of the resistor R5 (15) and the capacitor C5 (16), the tail current can be simulated in a short time, and the simulation result can be accurately matched with the actual measurement.
[Embodiment 3]
FIG. 3 is a diagram showing a circuit configuration of an IGBT model (an IGBT transient characteristic simulation circuit) according to the third embodiment of the present invention. The IGBT model according to the third embodiment of the present invention has the circuit configuration of the IGBT model according to the second embodiment shown in FIG. 2, and controls the voltage between the gate electrode G1 and the drain electrode D1 of the Nch type MOSFET model 11. This is a model to which a current source GV1 (18) is added. The IGBT model according to the third embodiment of the present invention is basically the same as the circuit configuration of the IGBT model according to the second embodiment shown in FIG. Only explained.
本発明の第３の実施形態に係るIGBTモデルは、図２に示した第２の実施形態に係るIGBTモデルの回路構成に付加した電圧制御型電流源GV1（18）で、ゲート電極G1−ドレイン電極D1に流れる電流を制御することで、過渡特性に大きく影響するゲート電極G1−ドレイン電極D1間容量を制御するようにしたものである。これにより、テイル電流を模擬する際に更に実測結果との差を低減させる、つまりフィッティング精度を向上させることが可能となる。 The IGBT model according to the third embodiment of the present invention is a voltage control type current source GV1 (18) added to the circuit configuration of the IGBT model according to the second embodiment shown in FIG. By controlling the current flowing through the electrode D1, the capacitance between the gate electrode G1 and the drain electrode D1, which greatly affects the transient characteristics, is controlled. As a result, when the tail current is simulated, the difference from the actual measurement result can be further reduced, that is, the fitting accuracy can be improved.
11 Nch型MOSFETモデル
12 PNP型BJT(Bipolar Junction Transistor)モデル
13 電流制御型電流源（F1）
14 第１の電流制御型電流源（F2）
15 抵抗（R5）
16 容量（C5）
17 第２の電流制御型電流源（F3）
18 電圧制御型電流源（GV1）
G ゲート端子
C コレクタ端子
E エミッタ端子
G1 ゲート電極
D1 ドレイン電極
S1 ソース電極
B1 バルク電極
B2 ベース電極
C2 コレクタ電極
E2 エミッタ電極
11 Nch type MOSFET model
12 PNP BJT (Bipolar Junction Transistor) model
13 Current-controlled current source (F1)
14 First current-controlled current source (F2)
15 Resistance (R5)
16 capacity (C5)
17 Second current-controlled current source (F3)
18 Voltage controlled current source (GV1)
G Gate terminal
C Collector terminal
E Emitter terminal
G1 gate electrode
D1 Drain electrode
S1 Source electrode
B1 Bulk electrode
B2 Base electrode
C2 collector electrode
E2 Emitter electrode
Claims (3)
ソース電極及びバルク電極が前記エミッタ端子に、ゲート電極が前記ゲート端子に、ドレイン電極がPNP型BJTモデルのベース電極に接続されるNch型MOSFETモデルと、
コレクタ電極が前記エミッタ端子に、エミッタ電極が前記コレクタ端子に接続されるPNP型BJTモデルと、
前記PNP型BJTモデルのコレクタ電極に流れる電流を入力として、任意の電流を前記Nch型MOSFETモデルのドレイン電極−ソース電極間に出力する電流制御型電流源と、
を備えることを特徴とするIGBTの過渡特性シミュレーション回路。 In IGBT transient characteristics simulation circuit with gate terminal, emitter terminal, collector terminal,
An Nch type MOSFET model in which a source electrode and a bulk electrode are connected to the emitter terminal, a gate electrode is connected to the gate terminal, and a drain electrode is connected to a base electrode of a PNP type BJT model;
PNP type BJT model in which a collector electrode is connected to the emitter terminal, and an emitter electrode is connected to the collector terminal;
A current-controlled current source that outputs an arbitrary current between the drain electrode and the source electrode of the Nch MOSFET model, with the current flowing through the collector electrode of the PNP BJT model as an input,
An IGBT transient characteristics simulation circuit comprising:
前記電流制御型電流源は、
抵抗、コンデンサ、前記PNP型BJTモデルのコレクタ電極に流れる電流と同じ電流を前記抵抗の両端に流す第１の電流制御型電流源、および、前記コンデンサに流れる電流と同じ電流を前記Nch型MOSFETモデルのドレイン電極−ソース電極間に流す第２の電流制御型電流源を備え、前記抵抗、コンデンサ、第１の電流制御型電流源、および、第２の電流制御型電流源を並列に接続したことを特徴とするIGBTの過渡特性シミュレーション回路。 In the IGBT transient characteristics simulation circuit according to claim 1,
The current-controlled current source is
A resistor, a capacitor, a first current-controlled current source that causes the same current as the current flowing through the collector electrode of the PNP-type BJT model to flow across the resistor, and the same current as the current that flows through the capacitor are the Nch-type MOSFET model A second current control type current source that flows between the drain electrode and the source electrode, and the resistor, the capacitor, the first current control type current source, and the second current control type current source are connected in parallel. IGBT transient characteristics simulation circuit characterized by
前記Nch型MOSFETモデルのゲート電極−ドレイン電極間の電圧を入力として、任意の電流を前記Nch型MOSFETモデルのゲート電極−ドレイン電極間に出力する電圧制御型電流源を更に備えることを特徴とするIGBTの過渡特性シミュレーション回路。 In the IGBT transient characteristics simulation circuit according to claim 1 or 2,
And a voltage-controlled current source that outputs an arbitrary current between the gate electrode and the drain electrode of the Nch type MOSFET model with the voltage between the gate electrode and the drain electrode of the Nch type MOSFET model as an input. IGBT transient characteristics simulation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009105886A JP5299062B2 (en) | 2009-04-24 | 2009-04-24 | Method for simulating transient characteristics of IGBT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009105886A JP5299062B2 (en) | 2009-04-24 | 2009-04-24 | Method for simulating transient characteristics of IGBT |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010257174A true JP2010257174A (en) | 2010-11-11 |
| JP5299062B2 JP5299062B2 (en) | 2013-09-25 |
Family
ID=43318014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009105886A Expired - Fee Related JP5299062B2 (en) | 2009-04-24 | 2009-04-24 | Method for simulating transient characteristics of IGBT |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5299062B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103792478A (en) * | 2014-02-24 | 2014-05-14 | 东南大学 | Method for simulating direct-current feature of insulated gate bipolar transistor |
| JP2016173727A (en) * | 2015-03-17 | 2016-09-29 | 株式会社日立製作所 | Simulation circuit model and calculation method of switching waveform of simulation circuit model |
| KR20230020282A (en) * | 2021-08-03 | 2023-02-10 | 연세대학교 산학협력단 | Electromagnetic transient simulation method and record medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62198159A (en) * | 1986-02-25 | 1987-09-01 | Toshiba Corp | Semiconductor device |
| JPS6361970A (en) * | 1986-09-02 | 1988-03-18 | Sharp Corp | Determining method for noise parameter of field effect transistor |
| JPH05324750A (en) * | 1992-05-26 | 1993-12-07 | Mitsubishi Electric Corp | Reverse recovery simulation circuit for diode |
| JP2009026298A (en) * | 2007-06-20 | 2009-02-05 | Central Res Inst Of Electric Power Ind | Inverter simulation device, inverter simulation program, and inverter design method |
| JP2009251862A (en) * | 2008-04-04 | 2009-10-29 | Fuji Electric Device Technology Co Ltd | Simulation circuit for mos transistor |
-
2009
- 2009-04-24 JP JP2009105886A patent/JP5299062B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62198159A (en) * | 1986-02-25 | 1987-09-01 | Toshiba Corp | Semiconductor device |
| JPS6361970A (en) * | 1986-09-02 | 1988-03-18 | Sharp Corp | Determining method for noise parameter of field effect transistor |
| JPH05324750A (en) * | 1992-05-26 | 1993-12-07 | Mitsubishi Electric Corp | Reverse recovery simulation circuit for diode |
| JP2009026298A (en) * | 2007-06-20 | 2009-02-05 | Central Res Inst Of Electric Power Ind | Inverter simulation device, inverter simulation program, and inverter design method |
| JP2009251862A (en) * | 2008-04-04 | 2009-10-29 | Fuji Electric Device Technology Co Ltd | Simulation circuit for mos transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103792478A (en) * | 2014-02-24 | 2014-05-14 | 东南大学 | Method for simulating direct-current feature of insulated gate bipolar transistor |
| JP2016173727A (en) * | 2015-03-17 | 2016-09-29 | 株式会社日立製作所 | Simulation circuit model and calculation method of switching waveform of simulation circuit model |
| KR20230020282A (en) * | 2021-08-03 | 2023-02-10 | 연세대학교 산학협력단 | Electromagnetic transient simulation method and record medium |
| KR102571809B1 (en) | 2021-08-03 | 2023-08-25 | 연세대학교 산학협력단 | Electromagnetic transient simulation method and record medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5299062B2 (en) | 2013-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6251310B2 (en) | Measuring method of current-voltage characteristics | |
| WO2010029709A1 (en) | Testing device, testing method, circuit system, power supply device, power supply evaluation device, and method for emulating power supply environment | |
| JP2014105999A (en) | Voltage detection circuit and method for measuring characteristic of transistor | |
| US10866272B2 (en) | Simulation circuit and simulation method | |
| JP5299062B2 (en) | Method for simulating transient characteristics of IGBT | |
| JP2013026924A (en) | Gate drive circuit | |
| CN104640053A (en) | Direct-current impedance detecting method of loudspeaker, circuit and D type audio frequency amplifier | |
| TWI442678B (en) | A system and method for driving a bipolar junction transistor by adjusting a base current | |
| CN105631083A (en) | Method for establishing high-voltage IGBT module switch transient model suitable for circuit simulation | |
| JP2013182525A (en) | Igbt model for circuit simulation | |
| JP2010139273A (en) | Method and device for testing semiconductor element | |
| JP6936341B2 (en) | Current-voltage characteristic measurement method | |
| US20160070288A1 (en) | Voltage generation circuit | |
| JP7381568B2 (en) | How to measure device parameters | |
| CN116540044A (en) | Semiconductor test circuit and method | |
| JP2009251862A (en) | Simulation circuit for mos transistor | |
| JP2013228406A (en) | Power supply unit, test method, power supply evaluation device, method for evaluating power supply, and method for emulating power supply environment | |
| Asparuhova et al. | IGBT behavioral PSpice model | |
| Long et al. | Investigation of negative gate capacitance in MOS-gated power devices | |
| JPH09293863A (en) | Semiconductor element simulator | |
| JP2003189590A (en) | Controller for voltage drive type semiconductor elements connected in series | |
| JP2006162426A (en) | Inspection device for semiconductor device | |
| TW202103040A (en) | Simulation method of power metal oxide semiconductor transistor | |
| JP5476674B2 (en) | Semiconductor device simulation circuit | |
| JP2019086306A (en) | Testing device of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20110422 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20111111 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121030 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121106 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121225 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130521 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130603 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5299062 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |