CN113536723A - Power device drain-source parasitic capacitance sub-circuit model and modeling method thereof - Google Patents
Power device drain-source parasitic capacitance sub-circuit model and modeling method thereof Download PDFInfo
- Publication number
- CN113536723A CN113536723A CN202110779887.9A CN202110779887A CN113536723A CN 113536723 A CN113536723 A CN 113536723A CN 202110779887 A CN202110779887 A CN 202110779887A CN 113536723 A CN113536723 A CN 113536723A
- Authority
- CN
- China
- Prior art keywords
- drain
- node
- source
- parasitic
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a power device drain-source parasitic capacitance sub-circuit model and a modeling method thereof. Firstly, combining the actually measured data of the drain-source capacitance voltage of a flow sheet device, and processing the data by using Origin data processing software; then analyzing and establishing a fitting equation of the capacitance and the voltage in Origin to obtain a corresponding coefficient; inputting corresponding fitting type coefficient data in the model file according to the format to obtain a complete model; and finally, simulating the result that the drain-source capacitance changes along with the drain-source voltage by using the HSPICE simulator, wherein the result shows that the drain-source capacitance modeling method disclosed by the invention is more flexible and accurate compared with the conventional method for modeling the drain-source capacitance of the power device by adopting the diode junction capacitance.
Description
Technical Field
The invention belongs to the field of modeling and simulation of power devices, and particularly relates to a power device drain-source parasitic capacitance sub-circuit model and a modeling method thereof.
Background
The performance simulation of the circuit is carried out on the basis of a device model, and whether the simulation result is accurate or not is mainly determined by the accuracy of the device model. Therefore, the device model is also regarded as a bridge between the process production and the circuit design, and is a very critical link. At present, a modeling method for a power device at home and abroad is generally an equivalent circuit Macro Model (Macro Model), namely, an equivalent circuit Model of a complex device or a novel electronic device is represented by respectively combining basic device physical models in an SPICE universal library. Modeling of power devices such as SGT MOSFETs in the SPICE sub-circuit form is the most convenient and efficient method. In general, a sub-circuit model of a power device is composed of two parts, namely a part for simulating direct current characteristics and a part for simulating alternating current characteristics. The most important of the alternating current characteristics is simulation of each parasitic capacitance of the device, and the size of each parasitic capacitance directly influences the switching speed and the switching power consumption of the device, so that modeling of each parasitic capacitance is particularly important.
For power devices such as an SGT MOSFET, two obvious slope changes of drain-source capacitance along with the change of drain-source voltage are caused by the structural particularity of a Shield grid (Shield) which is short-circuited with a source electrode in a Trench, so that a large error occurs in modeling of the drain-source capacitance. The drain-source capacitance in the currently generally adopted model is simulated by a diode added at two ends of the drain-source, and a large error can occur when the diode junction capacitance is used for modeling the drain-source capacitance, so that the industrial standard cannot be met, and the subsequent circuit design simulation is influenced.
Disclosure of Invention
The invention aims to provide a new model and a new modeling method aiming at the field of power device modeling and simulation, in particular to a power device drain-source parasitic capacitance sub-circuit model and a new modeling method.
The specific technical scheme for realizing the purpose of the invention is as follows:
a modeling method of a power device drain-source parasitic capacitance sub-circuit model comprises the following specific steps:
step 1: capacitive voltage data processing of current slices
Firstly, actually measured voltage data of a drain-source capacitor based on a flow sheet device are imported into Origin software; then, a fitting formula (1) of a six-order polynomial with drain-source voltage as an independent variable and drain-source capacitance as a dependent variable is established in Origin software by using a fitting mode to obtain coefficients A, B in the fitting formula1、B2、B3、B4、B5、B6；
Cds＝A+B1*Vds+B2*Vds2+B3*Vds3+B4*Vds4+B5*Vds5+B6*Vds6 (1)
In the formula, Vds is drain-source voltage, and Cds is drain-source parasitic capacitance;
step 2: modeling of power device drain-source parasitic capacitance sub-circuit
And (3) sequentially filling the coefficients obtained in the step (1) into a model file with a sub-circuit model structure to obtain a power device drain-source parasitic capacitance sub-circuit model.
A power device drain-source parasitic capacitance sub-circuit model constructed by the method, wherein the sub-circuit model comprises: a drain port node D, a gate port node G, a source port node S, a drain parasitic resistor Rd, a gate parasitic resistor Rg, a source parasitic resistor Rs, a gate-drain parasitic capacitor Cgd, a gate-source parasitic capacitor Cgs, a drain-source parasitic variable capacitor Cds, a parasitic body diode Dbody, a MOS transistor, a first node, a second node and a third node, wherein one end of the drain parasitic resistor Rd is connected with the drain port node D, the other end is connected with the first node, one end of the gate parasitic resistor Rg is connected with the gate port node G, the other end is connected with the second node, one end of the source parasitic resistor Rs is connected with the source port node S, the other end is connected with the third node, one end of the gate-drain parasitic capacitor Cgd is connected with the second node, the other end is connected with the first node, one end of the gate-source parasitic capacitor Rg is connected with the second node, the other end is connected with the third node, and the drain, gate and source of the MOS transistor are respectively connected with the first node, The parasitic diode Dbody has an anode connected to the third node, a cathode connected to the first node, and a drain-source parasitic variable capacitor Cds having one end connected to the first node and the other end connected to the third node.
The result proves that the modeling of the drain-source capacitor by the method is more flexible and accurate through the simulation of the HSPICE on the drain-source capacitor and the comparison with the actually measured data of the current sheet.
The invention has the beneficial effects that: compared with the common condition that the drain-source capacitance is modeled by using the diode junction capacitance, the variable capacitance CdS is added between the third node and the first node of the model sub-circuit, meets a high-order polynomial, can select a proper fitting formula according to different capacitance data to model the drain-source capacitance CdS, and improves the flexibility of modeling; meanwhile, the drain-source capacitance CdS modeling method improves the modeling precision, the modeling accuracy is higher than that of a common method for modeling the drain-source capacitance by using the diode junction capacitance, and the standard of the industry can be well met.
The modeling of the drain-source capacitor is more flexible and accurate, so that the accuracy and reliability of subsequent circuit simulation are ensured.
Drawings
FIG. 1 is a modeling flow diagram of the present invention;
FIG. 2 is a diagram of a sub-circuit model architecture of the present invention;
FIG. 3 is a comparison of simulation verification results of the present invention and existing modeling methods.
Detailed Description
The invention is described in detail below with reference to the accompanying drawings and examples.
Examples
Referring to fig. 1, the modeling process of the present embodiment specifically includes:
1. data processing
And (3) processing capacitance voltage data of the current chip: firstly, actually measuring test data based on drain-source capacitance voltage of a tape device, and importing the actually measured test capacitance voltage data into Origin software; then processing data in Origin software, establishing a six-order polynomial fitting type with drain-source voltage as independent variable and drain-source capacitance as dependent variable by using a fitting function, such as an expression (1), and finally obtaining a key coefficient in the fitting type, such as A, B in the expression (1)1、B2、B3、B4、B5、B6；
Cds＝A+B1*Vds+B2*Vds2+B3*Vds3+B4*Vds4+B5*Vds5+B6*Vds6 (1)
In the formula, Vds is drain-source voltage;
2. creating model files
A complete sub-circuit model is constructed in the model file according to the sub-circuit model structure of fig. 2. D, G, S represents drain, gate and source of the device, Rd, Rs and Rg are parasitic resistors, Cgd and Cgs are gate-drain capacitance and gate-source capacitance representing parasitic capacitance, MOS is core mosfet in sub-circuit model for simulating basic DC characteristic of the device, Dbody is parasitic diode of the simulation device, and variable capacitance Cds is parasitic drain-source capacitance. The drain parasitic resistor Rd is respectively connected with the node D and the node 1, the gate parasitic resistor Rg is respectively connected with the node G and the node 2, the source parasitic resistor Rs is respectively connected with the node S and the node 3, the gate-drain parasitic capacitor Cgd is respectively connected with the node 2 and the node 1, the gate-source parasitic capacitor is respectively connected with the node 2 and the node 3, the drain, the gate and the source of the core mosfet MOS are respectively connected with the nodes 1, 2 and 3, the parasitic body diode Dbody is respectively connected with the node 3 and the node 1, and the drain-source parasitic variable capacitor Cds is respectively connected with the node 1 and the node 3.
3. Inputting corresponding key coefficients into a model file of a sub-circuit model
Compared with the common condition that the drain-source capacitance is modeled by diode junction capacitance, the variable capacitance CdS is added between the nodes 3 and 1 at two ends of the drain and the source in the model file, and the coefficient obtained in the previous step is filled in the sub-circuit model file according to the format to obtain a complete model.
4. Capacitance simulation verification model accuracy of model
Referring to fig. 3(a), simulation data of the conventional diode modeling method is compared with flow sheet data, and fig. 3(b) is compared with the flow sheet data. Wherein the root mean square error of the simulation data and the tape-out data in fig. 3(a) is 7.5%, and the root mean square error of the simulation data and the tape-out data in fig. 3(b) is 1.6%.
The root mean square error of the simulation data and the measured flow sheet data is within 5% as shown in figure 3(b) by simulating the drain-source capacitance by HSPICE and comparing the simulation data with the measured flow sheet data.
Claims (2)
1. A modeling method for a power device drain-source parasitic capacitance sub-circuit model is characterized by comprising the following specific steps:
step 1: capacitive voltage data processing of current slices
Firstly, actually measured voltage data of a drain-source capacitor based on a flow sheet device are imported into Origin software; then, a fitting formula (1) of a six-order polynomial with drain-source voltage as an independent variable and drain-source capacitance as a dependent variable is established in Origin software by using a fitting mode to obtain coefficients A, B in the fitting formula1、B2、B3、B4、B5、B6；
Cds＝A+B1*Vds+B2*Vds2+B3*Vds3+B4*Vds4+B5*Vds5+B6*Vds6 (1)
In the formula, Vds is drain-source voltage, and Cds is drain-source parasitic capacitance;
step 2: modeling of power device drain-source parasitic capacitance sub-circuit
And (3) sequentially filling the coefficients obtained in the step (1) into a model file with a sub-circuit model structure to obtain a power device drain-source parasitic capacitance sub-circuit model.
2. A power device drain-source parasitic capacitance sub-circuit model constructed by the method of claim 1, wherein the sub-circuit model comprises: a drain port node D, a gate port node G, a source port node S, a drain parasitic resistor Rd, a gate parasitic resistor Rg, a source parasitic resistor Rs, a gate-drain parasitic capacitor Cgd, a gate-source parasitic capacitor Cgs, a drain-source parasitic variable capacitor Cds, a parasitic body diode Dbody, a MOS transistor, a first node, a second node and a third node, wherein one end of the drain parasitic resistor Rd is connected with the drain port node D, the other end is connected with the first node, one end of the gate parasitic resistor Rg is connected with the gate port node G, the other end is connected with the second node, one end of the source parasitic resistor Rs is connected with the source port node S, the other end is connected with the third node, one end of the gate-drain parasitic capacitor Cgd is connected with the second node, the other end is connected with the first node, one end of the gate-source parasitic capacitor Rg is connected with the second node, the other end is connected with the third node, and the drain, gate and source of the MOS transistor are respectively connected with the first node, The parasitic diode Dbody has an anode connected to the third node, a cathode connected to the first node, and a drain-source parasitic variable capacitor Cds having one end connected to the first node and the other end connected to the third node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110779887.9A CN113536723B (en) | 2021-07-09 | 2021-07-09 | Power device drain-source parasitic capacitance sub-circuit model and modeling method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110779887.9A CN113536723B (en) | 2021-07-09 | 2021-07-09 | Power device drain-source parasitic capacitance sub-circuit model and modeling method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113536723A true CN113536723A (en) | 2021-10-22 |
| CN113536723B CN113536723B (en) | 2022-11-01 |
Family
ID=78127333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110779887.9A Active CN113536723B (en) | 2021-07-09 | 2021-07-09 | Power device drain-source parasitic capacitance sub-circuit model and modeling method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113536723B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117236260A (en) * | 2023-11-13 | 2023-12-15 | 广东芯聚能半导体有限公司 | Modeling method and device for semiconductor device, computer equipment and storage medium |
| CN117709266A (en) * | 2023-12-13 | 2024-03-15 | 燕山大学 | Large-signal equivalent circuit model of vertical-structure power MOSFET |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101769965A (en) * | 2008-12-24 | 2010-07-07 | 东部高科股份有限公司 | Method for calculating capacitance of high voltage depletion capacitor |
| CN107741295A (en) * | 2017-09-15 | 2018-02-27 | 江苏大学 | A kind of MENS capacitive baroceptors test calibration device and method |
| CN108008152A (en) * | 2017-11-28 | 2018-05-08 | 中国电子产品可靠性与环境试验研究所 | Obtain the method and device of the parasitic mismatch capacitance of mems accelerometer |
| CN109918857A (en) * | 2019-04-19 | 2019-06-21 | 南京大学 | The non-linear piecewise temporal model method for building up of GaNHEMT device high frequency dynamic loss |
| CN109933897A (en) * | 2019-03-12 | 2019-06-25 | 中国科学院微电子研究所 | The modeling method and model of the big signal PSPICE model of GaN MIS-HEMT |
| CN111914505A (en) * | 2020-06-15 | 2020-11-10 | 上海集成电路研发中心有限公司 | Modeling method of MOS device |
-
2021
- 2021-07-09 CN CN202110779887.9A patent/CN113536723B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101769965A (en) * | 2008-12-24 | 2010-07-07 | 东部高科股份有限公司 | Method for calculating capacitance of high voltage depletion capacitor |
| CN107741295A (en) * | 2017-09-15 | 2018-02-27 | 江苏大学 | A kind of MENS capacitive baroceptors test calibration device and method |
| CN108008152A (en) * | 2017-11-28 | 2018-05-08 | 中国电子产品可靠性与环境试验研究所 | Obtain the method and device of the parasitic mismatch capacitance of mems accelerometer |
| CN109933897A (en) * | 2019-03-12 | 2019-06-25 | 中国科学院微电子研究所 | The modeling method and model of the big signal PSPICE model of GaN MIS-HEMT |
| CN109918857A (en) * | 2019-04-19 | 2019-06-21 | 南京大学 | The non-linear piecewise temporal model method for building up of GaNHEMT device high frequency dynamic loss |
| CN111914505A (en) * | 2020-06-15 | 2020-11-10 | 上海集成电路研发中心有限公司 | Modeling method of MOS device |
Non-Patent Citations (3)
| Title |
|---|
| 吴宇鹰，等: "碳化硅MOSFET行为建模方法", 《电力电子技术》 * |
| 唐雅欣，等: "一种新型降低GIDL的纳米线环栅场效应晶体管", 《微电子学》 * |
| 曾伊浓，等: "SiC MOSFET 功率器件特性参数的提取与拟合", 《高电压技术》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117236260A (en) * | 2023-11-13 | 2023-12-15 | 广东芯聚能半导体有限公司 | Modeling method and device for semiconductor device, computer equipment and storage medium |
| CN117236260B (en) * | 2023-11-13 | 2024-03-12 | 广东芯聚能半导体有限公司 | Modeling method and device for semiconductor device, computer equipment and storage medium |
| CN117709266A (en) * | 2023-12-13 | 2024-03-15 | 燕山大学 | Large-signal equivalent circuit model of vertical-structure power MOSFET |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113536723B (en) | 2022-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113536723B (en) | Power device drain-source parasitic capacitance sub-circuit model and modeling method thereof | |
| US8099269B2 (en) | Two-step simulation methodology for aging simulations | |
| US20070143719A1 (en) | Synthesizing current source driver model for analysis of cell characteristics | |
| McAndrew | Practical modeling for circuit simulation | |
| CN111368454B (en) | SiC MOSFET SPICE model establishment method based on bare chip packaging structure | |
| CN108062442A (en) | A kind of AlGaN/GaN HEMT microwave power devices small-signal intrinsic parameters extracting method | |
| CN108563801B (en) | Test structure and method for extracting FinFET parasitic resistance model | |
| CN112287626B (en) | Switch current model fitting power consumption change waveform method based on static time sequence information | |
| CN105022878A (en) | Radio frequency SOI-MOS varactor substrate model and parameter extracting method thereof | |
| WO2012126237A1 (en) | Method for modeling soi field-effect transistor spice model series | |
| US20160112041A1 (en) | Power transistor model | |
| US10846451B1 (en) | Methods of modelling irregular shaped transistor devices in circuit simulation | |
| CN105302943A (en) | Bias voltage dominant relevance mismatch model and extracting method | |
| JP5069711B2 (en) | MOSFET model parameter extraction method | |
| McAndrew | Compact models for MOS transistors: successes and challenges | |
| CN108899320B (en) | MOSFET gate oxide layer capacitance calibration structure | |
| CN108846171B (en) | Method for establishing sub-circuit model for simulating MOSFET temperature electrical characteristics | |
| CN114330196A (en) | SPICE modeling method of high-voltage power MOSFET device | |
| CN109815576B (en) | VDMOS device modeling method and model | |
| CN106484938B (en) | The simulation model and emulation mode of junction field effect transistor | |
| US20060236272A1 (en) | System and method for automatically calculating parameters of an mosfet | |
| CN113361229B (en) | Analog calculation method of MOSFET (Metal-oxide-semiconductor field Effect transistor) intrinsic voltage | |
| JP2007328688A (en) | Semiconductor device characteristic simulation method, device and program | |
| CN112287506B (en) | Simulation model of power metal oxide semiconductor transistor | |
| CN111090938B (en) | OLED sub-circuit model |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |