JP2001230407A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for improving breakdown voltage characteristics by reducing the leakage current of a field effect transistor due to a gallium nitride-based semiconductor. SOLUTION: This semiconductor device is provided with a buffer layer 102 containing GaN where a substrate 101 and a surface formed on the substrate 101 are the c surface of a Ga atom, a channel layer 103 containing GaN or InGaN where a surface formed on the buffer layer 102 is the c surface of the Ga or In atom, an electron supply layer 104 containing AlGaN where a surface formed on the channel layer 103 is the c surface of Al or Ga atom, a source electrode 106 and a drain electrode 108 formed on the electron supply layer 104, a cap layer 105 containing the GaN or InGaAlN that is the c surface of the Ga or In atom formed between the source electrode 106 and the drain electrode 108, and a gate electrode that is formed so that it is in contact with the cap layer 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device such as In _x Al _Y Ga.
_{The present} invention relates to a field-effect transistor using a gallium nitride-based semiconductor heterostructure represented by _1-XYN (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1).

[0002]

2. Description of the Related Art GaN, AlGaN, InGaN, InGaN
Gallium nitride based semiconductors such as AlGaN have high dielectric breakdown field strength, high thermal conductivity, and high electron saturation speed, and are promising as high frequency power device materials. In particular,
In a semiconductor device having an AlGaN / GaN heterojunction structure, electrons are accumulated at a high concentration near the heterojunction interface between AlGaN and GaN, and a so-called two-dimensional electron gas is formed. This two-dimensional electron gas exhibits high electron mobility because it is spatially separated from the donor impurity added to AlGaN. When a field effect transistor is manufactured using this heterostructure, the source resistance component is reduced. Can be reduced. Further, since the distance d from the gate electrode to the two-dimensional electron gas is usually as short as tens of nm, the gate length Lg is 1
Even if it is as short as about 00 nm, the ratio (that is, aspect ratio) Lg / d of the gate length Lg to the distance d can be increased to about 5 to 10. Therefore, a semiconductor device using a heterostructure has an excellent feature that a short-channel effect is small and a field-effect transistor having favorable saturation characteristics can be easily manufactured. Further AlGaN / G
The two-dimensional electron in the aN-based hetero structure is 1 × 10 ⁵ V /
In a high electric field region of about cm, the electron velocity is twice or more as compared with the case of the AlGaAs / InGaAs system widely used as a high frequency transistor at present, and application to a high frequency power device is expected.

FIG. 9 shows a conventional semiconductor device 900.
The semiconductor device 900 includes a GaN-containing buffer layer 902 and a GaN-containing buffer layer 902 on a sapphire substrate or a SiC substrate 901.
Or a channel layer 903 formed of InGaN;
This is a structure in which an electron supply layer 904 containing AlGaN is sequentially stacked. A source electrode 906 is provided on the electron supply layer 904.
, A gate electrode 907 and a drain electrode 908 are provided.

[0004] This AlGaN / GaN heterostructure is
Normally [0001] plane (c plane) sapphire substrate or S
It is formed by growing a crystal on the iC substrate 901 by using a metal organic chemical vapor deposition method or a molecular beam epitaxy method. When the buffer layer 902 containing GaN is formed over a sapphire substrate or a SiC substrate 901, the buffer layer 902 needs to be formed thick because the lattice constants of the substrate 901 and the buffer layer 902 are significantly different. Because
By forming the buffer layer 902 thickly, the buffer layer 9
This is because distortion due to lattice mismatch between the substrate 02 and the substrate 901 is sufficiently reduced. On this thick buffer layer 902, S
When the electron supply layer 904 containing AlGaN doped with an n-type impurity such as i is formed with a thickness of several tens nm, the buffer layer 902 having a high electron affinity at the hetero interface between AlGaN and GaN is formed due to the effect of selective doping. Then, a two-dimensional electron gas (that is, a channel layer 903) is formed. In the heterostructure formed by the MOCVD (metal organic chemical vapor deposition) method, the crystal surface is usually a plane of group III atom Ga, and the concentration of the two-dimensional electron gas is included in the electron supply layer 904. AlGaN and (buffer layer 9
02) contained in AlGaN).
The effect of piezo polarization in the c-axis direction due to the tensile stress received by N is added, and electrons having a higher concentration than the value predicted from the concentration of the n-type impurity added to the electron supply layer 904 are accumulated. The Al composition of the AlGaN of the electron supply layer 904 is 0.2
From 0.3 to 0.3, the electron concentration of the channel layer 903 is 1
It is about × 10 ¹³ / cm ² , which is about three times that of a GaAs device. Since such a high concentration of the two-dimensional electron gas is accumulated, the semiconductor device 9 used as a GaN-based heterostructure field effect transistor (FET)
00 is very promising as a power device.

[0005]

However, the conventional semiconductor device 900 has several problems. The problems are that (1) a crystal growth technique and a process related to the crystal growth technique are not perfect, so that high-quality crystals cannot be obtained; and (2) an etching process performed after the etching process. The device characteristics are degraded due to the damage introduced by the above, and the predicted power characteristics are not sufficiently realized.

One of the problems relating to crystal growth is that non-doped GaN contained in the buffer layer 902 usually shows n-type and the carrier concentration is as high as about 10 ¹⁶ / cm ³ or more. This is presumably because nitrogen (N), which is a constituent element, escapes during crystal growth and nitrogen vacancies are easily formed. The presence of such residual carriers increases the leakage current component through the GaN buffer layer 902 of the device, which leads to deterioration of device characteristics such as poor pinch-off characteristics particularly when operated at a high temperature. Also,
When a plurality of GaN-based heterostructure FETs are formed on the same substrate, the FETs interfere with each other, which causes a problem with element isolation that normal operation is prevented. Further, when gate electrode 907 is provided above GaN buffer layer 902, problems such as an increase in gate leak current and a decrease in element withstand voltage occur.

As a problem in the etching process technology, GaN (contained in the buffer layer 902) or
(Included in electron supply layer 904) Damage may be formed on the surface of AlGaN. GaN or Al
Since GaN is difficult to remove or remove using wet etching, etching is usually performed using dry etching. However, the surface of the buffer layer 902 or the electron supply layer 904 is damaged due to damage to the surface formed at the time of dry etching. Leakage current easily flows to the surface. In particular, it is considered that the lack of nitrogen on the surface increases the conductivity of the surface of the buffer layer 902 exposed by etching and increases the leakage current.

The present invention relates to the GaN heterostructure F described above.
The first object of the present invention is to provide a semiconductor device in which surface leakage current due to residual carriers caused by defects or scratches unintentionally introduced into a GaN layer or the surface of a GaN layer is significantly reduced. GaN-based heterostructure FET). A second object of the present invention is to provide a semiconductor device (GaN-based heterostructure FET) capable of improving the withstand voltage (withstand voltage) of an element while reducing surface leakage current.
Is provided.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A buffer layer containing GaN formed on the substrate, wherein the buffer layer has a c-plane of Ga atoms on the surface of the buffer layer; and a Ga layer formed on the buffer layer.
A channel layer containing N or InGaN, wherein the surface of the channel layer is a c-plane of Ga or In atoms, and an electron supply layer containing AlGaN formed on the channel layer, An electron supply layer in which the surface of the electron supply layer is a c-plane of Al or Ga atoms, a source electrode and a drain electrode formed on the electron supply layer,
Ga formed between the source electrode and the drain electrode
A cap layer containing N or InGaAlN, wherein the surface of the cap layer is a c-plane of Ga or In atoms;
The semiconductor device includes a cap layer in which at least a part of the cap layer is in contact with the electron supply layer, and a gate electrode formed so that at least a part is in contact with the cap layer.

[0010] At least a part of the gate electrode may be formed so as to be in contact with the electron supply layer.

[0011] The gate electrode may be formed on the cap layer.

The cap layer is made of InGaAlN. The composition of the cap layer is substantially matched to the lattice constant of the buffer layer in the c-plane, and the absolute value of the magnitude of the polarization generated in the cap layer is as described above. The electron supply layer may be formed so as to be larger than the absolute value of the polarization generated in the electron supply layer.

An n-type impurity may be partially or entirely added to the cap layer.

[0014] The gate electrode may be located closer to the source electrode than the drain electrode.

[0015] The surface area of the gate electrode may be larger than the surface area of the cap layer.

[0016] The gate electrode may be located in a region where the cap layer is thinned or removed.

[0017] The gate electrode may be formed on the source electrode side of the cap layer, and the cap layer may be formed between the gate electrode and the drain electrode.

[0018] The cap layer may include a semiconductor layer formed on the electron supply layer, and an insulating film formed on the semiconductor layer.

With the above structure, the barrier height of the Schottky junction is increased to reduce the leak current while preventing an increase in the source resistance, or to improve the breakdown voltage while preventing the increase in the source resistance. A semiconductor device that can achieve the above can be provided. Further, with the structure in which the cap layer is left in a wider range between the gate and the drain, the withstand voltage of the semiconductor device can be further improved.

The semiconductor substrate of the present invention comprises a substrate and a buffer layer containing AlGaN formed on the substrate,
A buffer layer in which the surface of the buffer layer is a c-plane of N atoms; and an electron supply layer including AlGaN formed on the buffer layer, wherein the surface of the electron supply layer is a c-plane of N atoms. A channel layer including GaN or InGaN formed on the electron supply layer, wherein the surface of the channel layer is a c-plane of N atoms; A source electrode and a drain electrode formed thereon, and a cap layer including AlGaN formed between the source electrode and the drain electrode, wherein a surface of the cap layer is a c-plane of N atoms; The semiconductor device includes a cap layer in which at least a part of the cap layer is in contact with the channel layer, and a gate electrode formed so that at least a part is in contact with the cap layer.

[0021] At least a part of the gate electrode may be formed so as to be in contact with the channel layer.

[0022] The gate electrode may be formed on the cap layer.

[0023] The gate electrode may be located closer to the source electrode than the drain electrode.

The surface area of the gate electrode may be larger than the surface area of the cap layer.

[0025] The gate electrode may be located in a region where the cap layer is thinned or removed.

[0026] The gate electrode may be formed on the source electrode side of the cap layer, and the cap layer may be formed between the gate electrode and the drain electrode.

[0027] The cap layer may include a semiconductor layer formed on the electron supply layer, and an insulating film formed on the semiconductor layer.

With the above structure, the barrier height of the Schottky junction is increased to reduce the leak current while preventing an increase in the source resistance, or to improve the breakdown voltage while preventing the increase in the source resistance. A semiconductor device that can achieve the above can be provided. Further, with the structure in which the cap layer is left in a wider range between the gate and the drain, the withstand voltage of the semiconductor device can be further improved.

[0029]

(First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1A is a sectional view of a field-effect transistor (FET) 100 according to the first embodiment of the present invention, and FIG. 1B is a top view thereof. The field-effect transistor 100 has a GaN buffer layer 102 having a thickness of about 2 to 3 μm on a substrate 101 formed of sapphire or SiC.
Channel layer 10 formed from aN or InGaN
3. The composition ratio of AlN is about 0.15 to 0.5,
An n-type AlGaN electron supply layer 104 to which an n-type impurity such as i is added at a concentration of about 2 × 10 ¹⁸ cm ⁻³ and a film thickness of about 1
It has a structure in which GaN cap layers 105 of 0 to 20 nm are sequentially laminated. The GaN cap layer 105 is selectively etched away leaving only the central portion, and the gate electrode 107 is formed on the GaN cap layer 105. Source electrode 1
06 and the drain electrode 108 are formed adjacent to the gate electrode 107 on the surface of the AlGaN electron supply layer 104 after the GaN cap layer 105 has been removed and exposed. Here, the surface of each nitride layer is formed by the c-plane of group III atoms.

As shown in FIG. 1B, the element forming region 109
Around isolation region 1 surrounding element formation region 109.
10 is formed by a method that does not involve etching such as ion implantation. The GaN cap layer 105 is formed in a range wider than the gate electrode 107. Also, GaN
The cap layer 105 is formed so as not to contact the source electrode 106 and the drain electrode 108. The GaN cap layer 105 acts to increase the effective barrier height (peak potential) of the Schottky electrode.
This is explained by the difference in the magnitude of the polarization generated in the N cap layer 105 and the AlGaN electron supply layer 104.

Next, the effect of polarization generated when a stress is applied to the field effect transistor 100 having such a configuration will be described.

Since the GaN buffer layer 102 is thick enough to alleviate the compressive strain caused by lattice mismatch, piezo polarization due to the influence of the strain does not occur, but only spontaneous polarization occurs. On the other hand, the AlGaN electron supply layer 104 is subjected to tensile strain, and a large piezo polarization is generated in addition to the spontaneous polarization. The direction of this polarization is the c-axis direction of the substrate 101, that is, the direction perpendicular to the surface of the substrate 101. Considering such a polarization effect, the semiconductor device 10 shown in FIG.
0 for the GaN cap layer 105 and the gate electrode 107
FIG. 2 shows the result of theoretically calculating the potential in the depth direction with respect to the interface (distance 0).

In FIG. 2, the thickness of the GaN cap layer 105 is set to 10 nm, and the gate voltage is set to 0V. A potential difference occurs in the GaN cap layer 105 due to the influence of polarization,
Thereby, the potential at the hetero interface with the AlGaN electron supply layer 104 (the peak potential shown in FIG. 2) is raised. This increases the effective Schottky barrier.

FIG. 3 shows the change in the effective barrier height (peak potential) when the thickness of the GaN cap layer 105 is changed from 0 to 20 nm (indicated by X in FIG. 3) and the GaN cap layer The change in the concentration of electrons accumulated at the hetero interface between the electron 105 and the AlGaN electron supply layer 104 (FIG. 3)
(Indicated by に お い て in Table 1) shows the result of theoretical calculation.

As shown in FIG. 3, the GaN cap layer 10
5, the barrier height (peak potential) of the effective Schottky electrode gradually increases, while the GaN cap layer 105 and the AlGaN electron supply layer 1 increase.
It can be seen that the concentration of electrons accumulated at the hetero interface with the H.04 decreases. The reason why the peak potential increases is that Ga
This is because, while the barrier height of the Schottky electrode with respect to the N cap layer 105 is constant, the potential difference generated in the GaN cap layer 105 increases as the thickness of the GaN cap layer 105 increases. Therefore, inserting the GaN cap layer 105 effectively increases the peak potential. Further, as the thickness of the GaN cap layer 105 increases, the electron concentration decreases. This is because a reverse bias is applied to the gate electrode by a potential difference generated in the GaN cap layer 105.

As described above, the provision of the GaN cap layer 105 increases the peak potential and reduces the concentration of electrons accumulated at the hetero interface. These all contribute to a higher breakdown voltage of the field effect transistor. However,
The leak current has a component flowing along the surface of the buffer layer 102, and particularly, the GaN contained in the buffer layer 102
It is important to reduce the leakage current component in a material that generates a donor by deficient nitrogen atoms on the surface as described above. Also, a decrease in the concentration of electrons accumulated at the hetero interface leads to an increase in the resistance in the region where the GaN cap layer 105 is located, which leads to an increase in the source resistance of the field effect transistor, leading to a decrease in transistor performance.

In the field effect transistor 100 of the present invention, the GaN cap layer 105 in the region between the gate and the source
Is removed (that is, the source electrode 106 and the cap layer 105 are not in direct contact), so that the source resistance is further reduced. Further, the GaN cap layer 105 also removes the leak current between the source and the gate and between the gate and the drain (that is, the source electrode 106).
And the cap layer 105 are not in direct contact, and the drain electrode 108 is not in direct contact with the cap layer 105). As described above, the potential becomes discontinuous in the in-plane direction indicated by the arrow a in FIG. 1B due to the potential difference generated in the GaN cap layer 105, and electrons contributing to the leakage current must acquire energy exceeding this discontinuity. Because it does not become. Since the energy at room temperature is about 26 meV, if the potential discontinuity value is 260 meV, the leakage current is reduced by about four digits, which is an extremely large effect. Figure 3
It can be seen from the change in the peak potential that when the GaN cap layer 105 having a thickness of 10 nm is inserted, a potential discontinuity value of about 1 eV is obtained as compared with the case where the GaN cap layer 105 is not inserted. It is expected that the value can be reduced.

FIG. 4 shows a field effect transistor (FET) 400 which is a first modification of the first embodiment of the present invention. The field-effect transistor 400 differs from the field-effect transistor 100 described with reference to FIG. 1A in that a portion of the GaN cap layer 405 on which the gate electrode 407 is stacked is thinned or removed by etching. Different. FIG. 4 illustrates an example in which the gate electrode 407 is in contact with the current supply layer 404. Thus G
Since the aN cap layer 405 is thinned or removed and the gate electrode 407 is stacked in that region, deterioration of the transconductance due to the GaN cap layer 405 is prevented. In this case, although the height of the Schottky barrier is not improved, the use of the potential discontinuity in the direction horizontal to the surfaces of the GaN cap layer and the AlGaN electron supply layer contributes to a reduction in leakage current.

The semiconductor device 100 shown in FIG.
Although the example in which the surface area of the cap layer 105 is larger than the surface area of the gate electrode 107 has been described, the present invention is not limited to this. FIG. 5 shows a field effect transistor (FET) 500 according to a second modification of the first embodiment of the present invention.
The field-effect transistor 500 differs from the field-effect transistor 100 described with reference to FIG. 1A in that the width of the GaN cap layer 505 is smaller than the width of the gate electrode 507. Therefore, in the field-effect transistor 500, the gate electrodes 507 are stacked so as to extend on both sides of the GaN cap layer 505. Even with this configuration, the effects of reducing the leak current and improving the breakdown voltage can be obtained. (Embodiment 2) FIGS. 6A to 6E are sectional views of a field-effect transistor (FET) according to a second embodiment of the present invention. 6A to 6E, the GaN cap layer 605 is provided for the purpose of improving the breakdown voltage.

The field-effect transistor (FET) 600 shown in FIG. 6A is different from the field-effect transistor (FET) 100 shown in FIG. 1 in that the gate electrode 607 provided on the GaN cap layer 605 is different from the source electrode 606 in FIG. They differ in that they are located closer. Accordingly, a depletion layer extending to the channel layer 603 immediately below the gate electrode 607 can be further expanded to the drain electrode 608 side, and the withstand voltage of the field-effect transistor 600 can be improved.

The field-effect transistor 610 shown in FIG. 6B is the same as the field-effect transistor 60 shown in FIG.
The difference from 0 is that the portion of the GaN cap layer 605 where the gate electrode 607 is formed is thinned or removed by etching. In the field-effect transistor 610 of FIG. 6B, the GaN cap layer is etched so that the gate electrode 607 is in contact with the current supply layer 604. Field effect transistor 61 shown in FIG. 6B
At 0, the transconductance, which is deteriorated by introducing the GaN cap layer 605, can be improved.

In the field effect transistor 620 shown in FIG. 6C, the gate electrode 607 is
5 is provided on the side edge of the source electrode 606 side and the electron supply layer 604 along the side edge. Therefore,
The GaN cap layer 605 is located between the gate electrode 607 and the drain electrode 608. In the configuration of the field-effect transistor 620 shown in FIG. 6C, the leakage current between the gate and the source is not improved, but the breakdown voltage between the gate and the drain is improved. In particular, the gate electrode 607 is the source electrode 6
Since the gate electrode 607 is formed over the side edge of the cap layer 605 on the 06 side, the gate electrode 607 is connected to the electron supply layer 604.
, The concentration of the electric field in the region on the side of the drain electrode in contact with the gate electrode can be reduced, and the withstand voltage between the gate and the drain can be further improved. Further, similarly to the field-effect transistor 610 shown in FIG. 6B, an increase in the source resistance can be prevented and the mutual conductance of the FET can be improved.

In the above embodiment, the cap layer 605
Has been described as an example using GaN. However, when GaN is used for the cap layer 605, its thickness cannot be made too large. Because, as shown in FIG.
By increasing the thickness of N, the sheet electron concentration becomes too low and / or the peak potential becomes too high, so that the cap layer 605 and the electron supply layer 604 become too high.
This is because a situation occurs in which holes accumulate during the period. The need to increase the thickness of the cap layer 605 without significantly affecting the sheet electron density arises particularly in the field-effect transistor 620 shown in FIG. 6C. This is because if the cap layer 605 is thickened in the field-effect transistor 620, the electric field concentration near the drain side of the gate electrode 607 is reduced, and the withstand voltage of the field-effect transistor 620 is improved. Further, the field effect transistor 620
When the thickness of the cap layer 605 is increased, the parasitic gate capacitance at the portion where the gate electrode 607 overlaps the cap layer 605 can be reduced, which leads to improvement in the high-frequency characteristics of the field-effect transistor 620.

The following two methods can be used to increase the thickness of the cap layer 605 while keeping the sheet electron density appropriately reduced. The first is to use an InGaAlN cap layer instead of the GaN cap layer 605. Second, an n-type impurity is added to the cap layer to reduce a potential difference generated in the cap layer.

In the first method, one of the requirements for the composition of InGaAlN is that the lattice constant of the c-plane is approximately matched with the lattice constant of the GaN buffer layer in order to increase the film thickness. For this purpose, In _0.18 Al _0.72 N and Ga
Since lattice matching can be _{attained with} N, In _0.18 Al _0.72 N and Ga
A mixed crystal of N may be used. That is, (In _0.18 Al _0.72 )
It may be the composition of _x Ga _1-x N. In practice, some deviation in composition is acceptable. Another requirement is that the magnitude of the polarization inside the InGaAlN cap layer be controlled by the AlGaN electron supply layer 6.
04 is to be kept smaller than the magnitude of the polarization that occurs. This limits the value of x of (In _0.18 Al _0.72 ) _x Ga ₁ -xN, and the upper limit of the value of x is AlG
It depends on the composition of AlN in the aN electron supply layer 604. When the upper limit of x is obtained by calculation for the AlN composition of the AlGaN electron supply layer 604 which is often used,
When the AlN composition of the AlGaN electron supply layer 604 is 10%, the upper limit of x is about 0.16, and the upper limit of x is about 0.16.
When the AlN composition of No. 4 is 30%, the upper limit of x is about 0.47. The upper limit of x is Al of the AlGaN electron supply layer 604.
It may be considered to be about 1.5 times the N composition ratio.

In the second method, an appropriate thickness of the cap layer 605 is determined depending on the concentration of the impurity to be added. The material of the cap layer may be GaN or InGaAlN, but it is assumed that GaN is used. Considering that the thickness of the cap layer is increased while maintaining the same potential as in FIG. 2 in the region below the AlGaN electron supply layer 104 (that is, in the region with a distance of 10 nm or more in FIG. 2), the following is obtained.

In FIG. 2, the surface potential of the cap layer 105 is shown.
Is fixed at a Schottky barrier height of 0.76V
You. At this time, the electric field becomes 0 and the cap layer 10
5 at the boundary between AlGaN electron supply layer 104
(About 1.6V) and doping to make the electric field equal.
If done, undoped any thickness on the cap layer
GaN layer can be formed. Under such conditions
To estimate, the thickness of the cap layer is 16.7 nm, n
3 × 10¹⁸/ Cm ^ThreeBut
can get. A desired thickness is formed on the n-type GaN cap layer.
Undoped GaN cap layer may be formed.

The above-described configuration of the cap layer is an example for showing the feasibility of the embodiment, and in fact, a cap layer having various concentrations and thicknesses can be designed. 6D and 6E when the charge control by the gate electrode is mainly performed at the contact portion between the gate electrode 607 and the electric field supply layer 604 as in the field effect transistors 610 and 620 shown in FIGS. 6B and 6C. The cap layer 605 may be a combination of a semiconductor layer 605b such as an n-type GaN layer and an insulating film 605a formed thereon, like the field effect transistors 630 and 640 shown in FIG. Although an SiO ₂ film or a silicon nitride film can be used as the insulating film, it is more preferable to use a silicon nitride film which is said to have a low interface state density. FIG.
The field-effect transistor 630 shown in FIG.
6E has a semiconductor layer 605b and an insulating film 605a provided thereon instead of the cap layer 605 of the field effect transistor 610. The field effect transistor 640 shown in FIG. Instead of the cap layer 605 of the type transistor 620, a semiconductor layer 605b and an insulating film 605a provided thereon are provided. In the field-effect transistor 630, the gate electrode 607 is formed so as to be in contact with not only the AlGaN electron supply layer 604 but also the upper surface of the cap layer 605.
In the field effect transistor 610, the gate electrode 6
It is needless to say that there is no problem if 07 is formed so as to contact not only the AlGaN electron supply layer 604 but also the upper surface of the cap layer 605. In particular, it is expected that the breakdown voltage is improved by extending the gate electrode 607 on the cap layer 605 to the drain side as described above. (Embodiment 3) In the structure of the field-effect transistor (FET) described in Embodiments 1 and 2, the surface of the heterostructure is a group III atom, but nitrogen of a group V atom forms the surface. If so, another configuration is required. An example where the surface of the heterostructure is nitrogen of a group V atom will be described below.

FIG. 7 shows a field-effect transistor 700 as the above specific example. Field-effect transistor 700
Is a substrate 701 made of sapphire or SiC
And a composition ratio of AlN of about 0.2 to 3 [mu] m.
AlGaN buffer layer 702 of 15 to 0.5, n-type AlGaN electron supply layer 703 doped with n-type impurity such as Si at a concentration of about 2 × 10 ¹⁸ cm ⁻³ , and film thickness of about 15 to 20
Channel layer 7 made of GaN or InGaN with a thickness of nm
04, AlGaN cap layer 705 having a thickness of about 10 nm
Are sequentially laminated structures. In this field-effect transistor 700, the AlN composition ratio in each AlGaN layer may be the same, but the AlGaN cap layer 705 on the surface
Can be made larger than the AlN composition of the AlGaN buffer layer 702 in consideration of the effect of polarization. As in the field-effect transistor 100 shown in FIG. 1A, the AlGaN cap layer 705 is selectively removed except for the central portion, and the gate electrode 707 is made of AlGaN.
It is formed on the cap layer 705. Source electrode 706
The drain electrode 708 is formed on the channel layer 704 adjacent to the gate electrode 707 after the AlGaN cap layer 705 has been removed. As described above, the surface of each nitride layer is formed by the c-plane of group V atoms (nitrogen).

The growth conditions in the molecular beam epitaxy method in which the surface becomes a group V atom in the heterostructure field effect transistor 700 mainly composed of GaN have already been reported. When the film is formed so that the surface is a group V atom, the direction of polarization generated in each layer is opposite to that in the case where the surface is a group III atom, and therefore, the buffer of the field-effect transistor 100 shown in FIG. Instead of GaN as a material for forming the layer 102, Al is used as the buffer layer 702.
GaN is used. An electron supply layer 703 including AlGaN doped with an n-type impurity such as Si and a channel layer 704 are sequentially formed thereon. Channel layer 704
To the AlGaN under the channel layer 704
This is due to the positive charge induced from the electron supply layer 703 and the polarization difference between the channel layer 704 and the electron supply layer 703. Therefore, a gate electrode is usually formed directly on the channel layer 704. Where AlGa
The N buffer layer 702 is formed sufficiently thick so as to reduce lattice strain, and includes a channel layer 7 containing GaN or InGaN.
Since 04 is subjected to compressive strain, it is formed to be relatively thin with several tens of nm. As the cap layer 705, AlGaN is used instead of GaN.

With such a configuration, the increase in the source resistance can be prevented and the leak current can be reduced for the same reason as described in the first embodiment.

Further, a large number of modifications are conceivable in the present embodiment, and FIGS. 8A to 8E show such modifications as a field effect transistor (FET). However, FIG.
In the field-effect transistors shown in FIGS. 8A to 8E, the surface of each nitride layer is formed by a c-plane of group V atoms (nitrogen).

The field-effect transistor 800 shown in FIG. 8A is the same as the field-effect transistor 40 shown in FIG.
As in the case of No. 0, the portion of the AlGaN cap layer 805 forming the gate electrode 807 is thinned or removed by etching. With such a configuration, the transconductance, which is deteriorated by introducing the AlGaN cap layer 805, can be improved.

The field-effect transistor 810 shown in FIG. 8B is the same as the field-effect transistor 50 shown in FIG.
Corresponds to 0. Field Effect Transistor (FET) 81
0, the gate electrode 807 is formed on the AlGaN cap layer 805,
5 is smaller than the surface area of the gate electrode 807.
Therefore, the AlGaN cap layer 805 is
7 is formed inside the bottom surface. With the structure of the field-effect transistor 810, leakage current can be reduced and breakdown voltage can be improved.

The field-effect transistor 820 shown in FIG. 8C is the same as the field-effect transistor 6 shown in FIG.
Corresponds to 00. The field-effect transistor 820 is the field-effect transistor (FET) 800 shown in FIG. 8A.
And the position of the gate electrode 807 provided on the AlGaN cap layer 805 is different. By arranging the gate electrode 807 on the source electrode 806 side, the area occupied by the AlGaN cap layer 805 between the gate and the drain becomes wider. With such a structure, the depletion layer that extends to the channel layer 804 immediately below the gate electrode 807 can be further expanded to the drain electrode 808 side, and the withstand voltage of the field-effect transistor 820 can be improved.

The field effect transistor 830 shown in FIG. 8D is the same as the field effect transistor 6 shown in FIG.
Corresponds to 10. The field-effect transistor 830 differs from the field-effect transistor 820 shown in FIG. 8C in that a portion of the AlGaN cap layer 805 where the gate electrode 807 is formed is thinned or removed by etching. By introducing the AlGaN cap layer 805 as in the structure of the field-effect transistor 830, the degraded transconductance can be improved.

The field-effect transistor 840 shown in FIG. 8E is the same as the field-effect transistor 6 shown in FIG.
Corresponds to 20. The field-effect transistor 840 has AlGa between the gate electrode 807 and the drain electrode 808.
This is a structure in which an N cap layer 805 is provided. With the structure of the field-effect transistor 840, the leakage current between the gate and the source is not improved, but the withstand voltage between the gate and the drain is improved.

Increasing the thickness of the cap layer 805 is effective in improving the breakdown voltage between the gate and the drain of the FET in the structure of the field effect transistor 840.
However, if the surface is a group V atom, AlGaN
It is not easy to increase the thickness of the cap layer 805 using a material other than the above. This is because the surface of the heterostructure is III
Unlike the case of the group, Ga forming the channel layer 804
This is because N receives compressive stress in the plane, so that the direction of spontaneous polarization and the direction of polarization due to the piezo effect are opposite to each other, and the absolute value of the polarization generated inside the GaN channel layer 804 becomes considerably small as a whole. . No material that lattice-matches with the AlGaN buffer layer 802 can have a polarization value smaller than that of AlGaN. Therefore, doping the cap layer 805 as described in the second embodiment is simpler and more effective than increasing the thickness of the cap layer using a material other than AlGaN.

As described in the second embodiment, the use of a combination of an AlGaN layer and an insulating film formed thereon as the cap layer 805 is also effective in the case of the field-effect transistors 830 and 840. S as insulating film
Although an iO ₂ film or a silicon nitride film can be used, it is preferable to use a silicon nitride film which is said to have a low interface state density.

The GaN buffer layer 10 shown in the present invention
2, 402, 502, 602 and the AlGaN buffer layers 702, 802 are the substrates 101, 401, 50, respectively.
100 nm on 1, 601 and 701, 801
Although a case where the film is formed through a relatively thin AlN layer has been reported in the past, it is needless to say that the present invention can be applied to such a case without any substantial change.

[0061]

According to the semiconductor device of the present invention, the leakage current can be reduced while preventing the source resistance of the gallium nitride based heterostructure from increasing, or the withstand voltage can be improved while preventing the source resistance from increasing. Provided is a semiconductor device (a field effect transistor). As a result, the power characteristics of the gallium nitride based heterostructure semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view illustrating a field-effect transistor according to a first embodiment of the present invention.

FIG. 1B is a top view illustrating the field-effect transistor according to the first embodiment of the present invention.

FIG. 2 is a potential diagram according to the first embodiment of the present invention.

FIG. 3 is a graph showing the dependence of sheet electron concentration and peak potential on the GaN cap layer thickness according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a field-effect transistor according to a modification of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a field-effect transistor according to another modification of the first embodiment of the present invention.

FIG. 6A is a sectional view illustrating a field-effect transistor according to a second embodiment of the present invention.

FIG. 6B is a sectional view illustrating the field-effect transistor according to the second embodiment of the present invention.

FIG. 6C is a sectional view illustrating the field-effect transistor according to the second embodiment of the present invention.

FIG. 6D is a sectional view illustrating the field-effect transistor according to the second embodiment of the present invention.

FIG. 6E is a sectional view illustrating the field-effect transistor according to the second embodiment of the present invention.

FIG. 7 is a sectional view illustrating a field-effect transistor according to a third embodiment of the present invention.

FIG. 8A is a cross-sectional view illustrating a field-effect transistor according to a modification of the third embodiment of the present invention.

FIG. 8B is a cross-sectional view illustrating a field-effect transistor according to a modification of the third embodiment of the present invention.

FIG. 8C is a cross-sectional view illustrating a field-effect transistor according to a modification of the third embodiment of the present invention.

FIG. 8D is a cross-sectional view illustrating a field-effect transistor according to a modification of the third embodiment of the present invention.

FIG. 8E is a cross-sectional view illustrating a field-effect transistor according to a modification of the third embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a conventional field-effect transistor.

[Explanation of symbols]

 101 substrate 102 buffer layer 103 channel layer 104 electron supply layer 105 cap layer 106 source electrode 107 gate electrode 108 drain electrode

Claims (18)

[Claims] A buffer layer including GaN formed on the substrate, wherein the buffer layer has a c-plane of Ga atoms; and a buffer layer formed on the buffer layer. GaN or InGaN
And the surface of the channel layer is Ga
A channel layer, which is a c-plane of In atoms, and an electron supply layer including AlGaN formed on the channel layer, wherein the surface of the electron supply layer is a c-plane of Al or Ga atoms. A supply layer, a source electrode and a drain electrode formed on the electron supply layer, and a Ga formed between the source electrode and the drain electrode.
A cap layer containing N or InGaAlN, wherein the surface of the cap layer is a c-plane of Ga or In atoms;
A semiconductor device comprising: a cap layer in which at least a part of the cap layer is in contact with the electron supply layer; and a gate electrode formed so that at least a part is in contact with the cap layer. 2. The semiconductor device according to claim 1, wherein at least a part of said gate electrode is formed so as to be in contact with said electron supply layer. 3. The semiconductor device according to claim 1, wherein said gate electrode is formed on said cap layer. 4. The cap layer is made of InGaAlN. The composition of the cap layer is substantially matched to the lattice constant of the buffer layer in the c-plane, and the absolute value of the magnitude of polarization generated in the cap layer. 2. The semiconductor device according to claim 1, wherein the electron supply layer is formed such that is smaller than an absolute value of polarization generated in the electron supply layer. 5. The semiconductor device according to claim 1, wherein an n-type impurity is partially or entirely added to said cap layer. 6. The semiconductor device according to claim 1, wherein said gate electrode is located closer to said source electrode than said drain electrode. 7. The semiconductor device according to claim 3, wherein a surface area of said gate electrode is larger than a surface area of said cap layer. 8. The semiconductor device according to claim 1, wherein said gate electrode is located in a region where said cap layer is thinned or removed. 9. The semiconductor device according to claim 1, wherein said gate electrode is formed on said source electrode side of said cap layer, and said cap layer is formed between said gate electrode and said drain electrode. 10. The semiconductor device according to claim 1, wherein said cap layer includes a semiconductor layer formed on said electron supply layer, and an insulating film formed on said semiconductor layer. 11. A substrate, a buffer layer including AlGaN formed on the substrate, wherein the surface of the buffer layer is a c-plane of N atoms, and a buffer layer formed on the buffer layer. An electron supply layer containing AlGaN, wherein the surface of the electron supply layer is a c-plane of N atoms; and GaN or InGaN formed on the electron supply layer.
A channel layer, wherein the surface of the channel layer is a c-plane of N atoms, a source electrode and a drain electrode formed on the channel layer, the source electrode and the drain electrode, Al formed during
A cap layer containing GaN, wherein the surface of the cap layer is a c-plane of N atoms, and at least a part of the cap layer is in contact with the channel layer; And a gate electrode formed as described above. 12. The semiconductor device according to claim 11, wherein at least a part of said gate electrode is formed to be in contact with said channel layer. 13. The semiconductor device according to claim 11, wherein said gate electrode is formed on said cap layer. 14. The semiconductor device according to claim 11, wherein said gate electrode is located closer to said source electrode than said drain electrode. 15. The semiconductor device according to claim 13, wherein a surface area of said gate electrode is larger than a surface area of said cap layer. 16. The semiconductor device according to claim 11, wherein said gate electrode is located in a region where said cap layer is thinned or removed. 17. The semiconductor device according to claim 1, wherein the gate electrode is formed on the source electrode side of the cap layer, and the cap layer is formed between the gate electrode and the drain electrode.
2. The semiconductor device according to 1. 18. The semiconductor device according to claim 11, wherein said cap layer includes a semiconductor layer formed on said electron supply layer, and an insulating film formed on said semiconductor layer.