JP2008235613A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008235613A
JP2008235613A JP2007073804A JP2007073804A JP2008235613A JP 2008235613 A JP2008235613 A JP 2008235613A JP 2007073804 A JP2007073804 A JP 2007073804A JP 2007073804 A JP2007073804 A JP 2007073804A JP 2008235613 A JP2008235613 A JP 2008235613A
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nitride semiconductor
semiconductor layer
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Seiji Yaegashi
誠司 八重樫
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Sumitomo Electric Device Innovations Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing contact resistance between an ohmic electrode and an electron travelling layer. <P>SOLUTION: The semiconductor device comprises a nitride semiconductor layer 24 which is provided on a substrate 10 and comprises an electron travelling layer 18 and an electron supply layer 22, a p-type nitride semiconductor layer 14 provided in the nitride semiconductor layer 24, an n-doping region 26 which is provided in the nitride semiconductor layer 24 to reach the electron travelling layer 18, a gate electrode 44 provided on the electron supply layer 22, and ohmic electrodes 40 and 42 provided to contact the n-type doping region 26. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体装置に関し、特に、窒化物半導体を用いた半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a nitride semiconductor.

窒化ガリウム（ＧａＮ）等の窒化物半導体を用いた半導体装置は、高周波かつ高出力で動作するパワー素子として用いられている。特に、マイクロ波、準ミリ波、ミリ波等の高周波帯域において増幅を行うのに適した半導体装置として、高電子移動度トランジスタ（ＨＥＭＴ）等のＦＥＴの開発が進められている。また、ＨＢＴ（Ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｉｔｏｒ）やＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）等のトランジスタも開発されている。なお、窒化物半導体には、例えば、ＧａＮ、ＡｌＮ（窒化アルミニウム）、ＩｎＮ（窒化インジウム）、ＧａＮとＡｌＮとの混晶であるＡｌＧａＮ、ＧａＮとＩｎＮとの混晶であるＩｎＧａＮ、ＧａＮとＡｌＮとＩｎＮとの混晶であるＡｌＩｎＧａＮ等がある。   A semiconductor device using a nitride semiconductor such as gallium nitride (GaN) is used as a power element that operates at high frequency and high output. In particular, FETs such as high electron mobility transistors (HEMTs) are being developed as semiconductor devices suitable for performing amplification in high frequency bands such as microwaves, quasi-millimeter waves, and millimeter waves. Further, transistors such as HBT (Heterojunction Bipolar Transistor) and IGBT (Insulated Gate Bipolar Transistor) have been developed. The nitride semiconductor includes, for example, GaN, AlN (aluminum nitride), InN (indium nitride), AlGaN that is a mixed crystal of GaN and AlN, InGaN that is a mixed crystal of GaN and InN, GaN and AlN, and the like. Examples include AlInGaN which is a mixed crystal with InN.

ゲート電圧が０Ｖ以上でピンチオフするエンハンスメント・モード（Ｅモード）ＦＥＴは、待機電力を低減できるためスイッチング素子等に用いられている。また、ＥモードＦＥＴは、増幅器として使用する際、負電源が不要なため単一の電源を用い増幅器を形成できる。よって、回路の簡略化が可能となる。例えばＧａ面［０００１］方向に結晶成長されたＧａＮ電子走行層と電子走行層より電子親和力の小さいＡｌＧａＮ電子供給層とからなる窒化物半導体ＦＥＴにおいては、ＡｌＧａＮとＧａＮとの界面の歪みに起因するピエゾ分極及び結晶の対称性に起因する自発分極によりＡｌＧａＮ／ＧａＮ界面のＧａＮ側に２ＤＥＧ（２ Ｄｉｍｅｎｔｉｏｎ Ｅｌｅｃｔｒｏｎ Ｇａｓ：２次元電子ガス）が形成される。このようにして、電子供給層は２次元電子ガスを電子走行層に生成させ、この２ＤＥＧをゲート電極で制御することによりＦＥＴとして機能する。このようなＦＥＴをＥモードとするためには２ＤＥＧ濃度を小さくすることが求められるが、電子供給層を薄膜化してＥモードを形成するとチャネル抵抗が高くなり電気的輸送特性の劣化を招いてしまい、ＥモードＦＥＴを構成すること、つまり、閾値電圧を高くすることが難しくなる。   Enhancement mode (E mode) FETs that pinch off when the gate voltage is 0 V or higher can reduce standby power, and are used for switching elements and the like. Further, since the E mode FET does not require a negative power source when used as an amplifier, the amplifier can be formed using a single power source. Therefore, the circuit can be simplified. For example, in a nitride semiconductor FET comprising a GaN electron transit layer crystal-grown in the Ga plane [0001] direction and an AlGaN electron supply layer having a lower electron affinity than the electron transit layer, this is caused by strain at the interface between AlGaN and GaN. 2DEG (2 Dimension Electron Gas) is formed on the GaN side of the AlGaN / GaN interface by spontaneous polarization resulting from piezo polarization and crystal symmetry. In this way, the electron supply layer functions as an FET by generating a two-dimensional electron gas in the electron transit layer and controlling the 2DEG with the gate electrode. In order to make such an FET in the E mode, it is required to reduce the 2DEG concentration. However, if the E mode is formed by thinning the electron supply layer, the channel resistance increases and the electrical transport characteristics deteriorate. It is difficult to configure an E-mode FET, that is, to increase the threshold voltage.

そこで、特許文献１には、窒化物半導体ＦＥＴにおいて電子供給層にリセスを設けＥモードを実現する技術が開示されている。また、特許文献２にはリセスを有する窒化物半導体ＦＥＴにおいて、電子供給層とゲート電極との間に酸化膜を設けたＭＩＳ（Ｍｅｔａｌ Ｉｎｓｕｌａｔｏｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）構造の技術が開示されている。
特開２００６−３２６５０号公報 特開２００５−１８３７３３号公報 Therefore, Patent Document 1 discloses a technique for realizing an E mode by providing a recess in an electron supply layer in a nitride semiconductor FET. Patent Document 2 discloses a MIS (Metal Insulator Semiconductor) structure technique in which a nitride semiconductor FET having a recess is provided with an oxide film between an electron supply layer and a gate electrode.
JP 2006-32650 A JP 2005-183733 A

リセスを設けるなどして電子供給層を薄膜化すると、トンネリング現象等により電子供給層の見かけ上のショットキバリアが低くなる。このため、リーク電流が増大する。よって、ゲート電圧を大きくした場合、ゲート電流のリーク電流が大きくなってしまう。ＭＩＳ構造を採用することにより、このような課題を解決することができる。   When the electron supply layer is thinned by providing a recess or the like, the apparent Schottky barrier of the electron supply layer is lowered due to a tunneling phenomenon or the like. For this reason, the leakage current increases. Therefore, when the gate voltage is increased, the leakage current of the gate current increases. By adopting the MIS structure, such a problem can be solved.

しかし、ＭＩＳ構造の電子供給層とゲート電極との間の絶縁層は薄いことが好ましい。一方、絶縁層が薄いと、リーク電流が生じる。この結果、閾値電圧を高くすることが難しくなる。   However, the insulating layer between the electron supply layer having the MIS structure and the gate electrode is preferably thin. On the other hand, when the insulating layer is thin, leakage current is generated. As a result, it is difficult to increase the threshold voltage.

そこで、窒化物半導体層の一部をｐ型半導体層とすることにより閾値電圧を高くしＥモードＦＥＴを実現することが考えられる。また、ＦＥＴ、ＨＢＴ及びＩＧＢＴ等の窒化物半導体層を用いたトランジスタにおいては、窒化物半導体層内にｐ型窒化物半導体層が設けられる場合がある。   Thus, it is conceivable to realize an E-mode FET by increasing the threshold voltage by using a part of the nitride semiconductor layer as a p-type semiconductor layer. In a transistor using a nitride semiconductor layer such as FET, HBT, or IGBT, a p-type nitride semiconductor layer may be provided in the nitride semiconductor layer.

ところが、窒化物半導体層内にｐ型窒化物半導体層を設けると、そのｐ型窒化物半導体層のドーパントが電子走行層内に拡散され、窒化物半導体層上に形成したオーミック電極と電子が走行する電子走行層との接触抵抗が大きくなる。このため、トランジスタの電気的輸送特性が悪化する。   However, when the p-type nitride semiconductor layer is provided in the nitride semiconductor layer, the dopant of the p-type nitride semiconductor layer is diffused into the electron transit layer, and the ohmic electrode and electrons formed on the nitride semiconductor layer travel. The contact resistance with the traveling electron layer increases. For this reason, the electrical transport characteristics of the transistor are deteriorated.

本発明は、オーミック電極と電子走行層との接触抵抗を低減することが可能な半導体装置を提供することを目的とする。   An object of this invention is to provide the semiconductor device which can reduce the contact resistance of an ohmic electrode and an electron transit layer.

本発明は、基板上に設けられ電子走行層及び電子供給層を有する窒化物半導体層と、前記窒化物半導体層内に設けられたｐ型窒化物半導体層と、前記窒化物半導体層内に設けられ前記電子走行層に到達するｎ型ドーピング領域と、前記電子供給層上に設けられたゲート電極と、前記ｎ型ドーピング領域に接触して設けられたオーミック電極と、を具備することを特徴とする半導体装置である。本発明によれば、ｎ型ドーピング領域を設けることにより、ｐ型窒化物半導体層に起因したオーミック電極と電子走行層との接触抵抗の悪化を抑制することができる。   The present invention provides a nitride semiconductor layer provided on a substrate and having an electron transit layer and an electron supply layer, a p-type nitride semiconductor layer provided in the nitride semiconductor layer, and provided in the nitride semiconductor layer. And an n-type doping region that reaches the electron transit layer, a gate electrode provided on the electron supply layer, and an ohmic electrode provided in contact with the n-type doping region. It is a semiconductor device. According to the present invention, by providing the n-type doping region, it is possible to suppress the deterioration of the contact resistance between the ohmic electrode and the electron transit layer caused by the p-type nitride semiconductor layer.

上記構成において、前記ｐ型窒化物半導体層は、前記基板と前記電子走行層との間に設けられている構成とすることができる。この構成によれば、基板と電子走行層との間に設けられたｐ型窒化物半導体層により、閾値電圧を高くすることができる。また、ｎ型ドーピング領域により、オーミック電極と電子走行層との接触抵抗を低減することができる。   The said structure WHEREIN: The said p-type nitride semiconductor layer can be set as the structure provided between the said board | substrate and the said electron transit layer. According to this configuration, the threshold voltage can be increased by the p-type nitride semiconductor layer provided between the substrate and the electron transit layer. Further, the contact resistance between the ohmic electrode and the electron transit layer can be reduced by the n-type doping region.

上記構成において、ｐ型窒化物半導体層上にＡｌを含む窒化物半導体からなる拡散防止層を具備する構成とすることができる。この構成によれば、拡散防止層によりｐ型窒化物半導体層上からのｐ型ドーパントの拡散を抑制することができる。よって、オーミック電極と電子走行層との接触抵抗を低減することができる。   In the above configuration, a diffusion prevention layer made of a nitride semiconductor containing Al may be provided on the p-type nitride semiconductor layer. According to this configuration, the diffusion of the p-type dopant from the p-type nitride semiconductor layer can be suppressed by the diffusion preventing layer. Therefore, the contact resistance between the ohmic electrode and the electron transit layer can be reduced.

上記構成において、ｐ型窒化物半導体層はゲート電極の下に選択的に設けられている構成とすることができる。この構成によれば、オーミック電極と電子走行層との接触抵抗をより低減することができる。   In the above structure, the p-type nitride semiconductor layer can be selectively provided below the gate electrode. According to this configuration, the contact resistance between the ohmic electrode and the electron transit layer can be further reduced.

上記構成において、前記電子供給層はリセスを有し、前記ゲート電極は前記リセス上に設けられている構成とすることができる。この構成によれば、より閾値電圧を高く設定することができる。   In the above structure, the electron supply layer may have a recess, and the gate electrode may be provided on the recess. According to this configuration, the threshold voltage can be set higher.

上記構成において、前記電子供給層と前記ゲート電極との間に設けられた絶縁層を具備する構成とすることができる。この構成によれば、ゲート電極のリーク電流を抑制することができる。   In the above structure, an insulating layer provided between the electron supply layer and the gate electrode can be provided. According to this configuration, the leakage current of the gate electrode can be suppressed.

上記構成において、前記電子供給層は前記ｐ型窒化物半導体層を含む構成とすることができる。この構成によれば、電子供給層内がｐ型窒化物半導体層を含むため、閾値電圧を高くすることができる。また、ｎ型ドーピング領域により、オーミック電極と電子走行層との接触抵抗を低減することができる。   The said structure WHEREIN: The said electron supply layer can be set as the structure containing the said p-type nitride semiconductor layer. According to this configuration, since the electron supply layer includes the p-type nitride semiconductor layer, the threshold voltage can be increased. Further, the contact resistance between the ohmic electrode and the electron transit layer can be reduced by the n-type doping region.

上記構成において、前記リセス上に、ｐ型半導体層が設けられている構成とすることができる。また、上記構成において、前記半導体装置はエンハンスメント・モードである構成とすることができる。   In the above structure, a p-type semiconductor layer may be provided on the recess. In the above structure, the semiconductor device may be in an enhancement mode.

本発明は、基板上に設けられた窒化物半導体層と、前記窒化物半導体層内に設けられたｐ型窒化物半導体層及びｐ型窒化物半導体層上に設けられたｎ型コンタクト層と、前記ｎ型コンタクト層に到達するｎ型ドーピング領域と、前記ｎ型ドーピング領域に接触して設けられた第１電極と、前記基板に接続する第２電極と、前記第１電極と前記第２電極との間を流れる電流を制御する制御電極と、を具備することを特徴とする半導体装置である。本発明によれば、ｎ型ドーピング領域を設けることにより、ｐ型窒化物半導体層に起因した第１電極とコンタクト層との接触抵抗の悪化を抑制することができる。   The present invention includes a nitride semiconductor layer provided on a substrate, a p-type nitride semiconductor layer provided in the nitride semiconductor layer, and an n-type contact layer provided on the p-type nitride semiconductor layer, An n-type doping region reaching the n-type contact layer, a first electrode provided in contact with the n-type doping region, a second electrode connected to the substrate, the first electrode and the second electrode And a control electrode for controlling a current flowing between them. According to the present invention, by providing the n-type doping region, it is possible to suppress the deterioration of the contact resistance between the first electrode and the contact layer caused by the p-type nitride semiconductor layer.

本発明によれば、ｎ型ドーピング領域を設けることにより、ｐ型窒化物半導体層に起因したオーミック電極と電子走行層との接触抵抗の悪化を抑制することができる。 According to the present invention, by providing the n-type doping region, it is possible to suppress the deterioration of the contact resistance between the ohmic electrode and the electron transit layer caused by the p-type nitride semiconductor layer.

以下、図面を参照に本発明の実施例について説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１（ａ）から図２（ｂ）を用い実施例１に係るＨＥＭＴの製造工程について説明する。図１（ａ）を参照に、ｃ−サファイア基板１０上にバッファ層１２として膜厚が例えば２．０μｍのｉ−ＧａＮを形成する。バッファ層１２上にｐ型半導体層１４（ｐ型窒化物半導体層）としてＭｇ（マグネシウム）を２×１０２０ｃｍ−３程度ドープしたＧａＮ層を形成する。ｐ型半導体層１４の膜厚は数ｎｍから１００ｎｍ程度が好ましい。ｐ型半導体層１４上に拡散防止層１６として膜厚が１０ｎｍ程度のＡｌＮ層を形成する。拡散防止層１６上に電子走行層１８として膜厚が１０ｎｍのｉ−ＧａＮ層を形成する。電子走行層１８上に電子供給層２２として、膜厚が例えば３０ｎｍのｉ−Ａｌ０．２５Ｇａ０．７５Ｎを形成する。以上により、基板１０上に窒化物半導体層２４が形成される。 A manufacturing process of the HEMT according to the first embodiment will be described with reference to FIGS. Referring to FIG. 1A, i-GaN having a thickness of, for example, 2.0 μm is formed as a buffer layer 12 on a c-sapphire substrate 10. A GaN layer doped with about 2 × 10 20 cm −3 of Mg (magnesium) is formed on the buffer layer 12 as the p-type semiconductor layer 14 (p-type nitride semiconductor layer). The thickness of the p-type semiconductor layer 14 is preferably about several nm to 100 nm. An AlN layer having a thickness of about 10 nm is formed on the p-type semiconductor layer 14 as the diffusion preventing layer 16. An i-GaN layer having a thickness of 10 nm is formed on the diffusion prevention layer 16 as the electron transit layer 18. As the electron supply layer 22, for example, i-Al 0.25 Ga 0.75 N having a thickness of 30 nm is formed on the electron transit layer 18. Thus, the nitride semiconductor layer 24 is formed on the substrate 10.

窒化物半導体層２４の形成は、ＭＯＶＰＥ（Ｍｅｔａｌ Ｏｒｇａｎｉｃ Ｖａｐｏｒ Ｐｈａｓｅ Eｐｉｔａｘｙ）法またはＭＯＣＶＤ（Ｍｅｔａｌ Ｏｒｇａｎｉｃ Ｃｈｅｍｉｃａｌ ＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）法を用いＧａ面［０００１］方向に成膜する。基板１０は、窒化物半導体層２４が形成できる基板であればよく、例えばＳｉＣ（炭化シリコン）基板、（１１１）面のＳｉ（シリコン）基板でもよい。電子走行層１８と電子供給層２２との分極率の差及び電子親和力の差に起因し電子走行層１８の電子供給層２２との界面には２ＤＥＧ２０が形成される。   The nitride semiconductor layer 24 is formed in the Ga plane [0001] direction using a MOVPE (Metal Organic Vapor Phase Epitaxy) method or a MOCVD (Metal Organic Chemical Vapor Deposition) method. The substrate 10 may be any substrate on which the nitride semiconductor layer 24 can be formed. For example, the substrate 10 may be a SiC (silicon carbide) substrate or a (111) plane Si (silicon) substrate. Due to the difference in polarizability between the electron transit layer 18 and the electron supply layer 22 and the difference in electron affinity, 2DEG 20 is formed at the interface between the electron transit layer 18 and the electron supply layer 22.

図１（ｂ）を参照に、フォトレジストまたは絶縁膜をマスクにＳｉをイオン注入し、熱処理を行う。これにより、窒化物半導体層２４に少なくとも２ＤＥＧ２０まで達するｎ型注入領域２６（ｎ型ドーピング領域）を形成する。Ｓｉの注入条件は、電子供給層２２の膜厚等を考慮し適宜設定することができる。例えば、注入エネルギーが５０ｋｅＶから１００ｋｅＶ、ドーズ量が１０１５ｃｍ−２から１０１６ｃｍ−２程度が好ましい。熱処理の温度はＳｉが活性化するように適宜設定することができる。例えば１２００℃とすることができる。 Referring to FIG. 1B, Si is ion-implanted using a photoresist or an insulating film as a mask, and heat treatment is performed. As a result, an n-type implantation region 26 (n-type doping region) reaching at least 2 DEG 20 is formed in the nitride semiconductor layer 24. The Si implantation conditions can be appropriately set in consideration of the thickness of the electron supply layer 22 and the like. For example, the implantation energy is preferably about 50 keV to 100 keV and the dose amount is about 10 15 cm −2 to 10 16 cm −2 . The temperature of the heat treatment can be appropriately set so that Si is activated. For example, it can be 1200 degreeC.

図１（ｃ）を参照に、電子供給層２２及び電子走行層１８を例えばＢＣｌ３／Ｃｌ２等の塩素系ガスを用いドライエッチングする。これにより素子分離領域３１を形成する。なお、イオン注入法を用い素子分離領域を形成してもよい。電子供給層２２を例えば塩素系ガスを用いドライエッチングし、電子供給層２２（膜厚が３０ｎｍ）に深さ約２０ｎｍのリセス３０を形成する。電子供給層２２の膜厚は例えば１０ｎｍから５０ｎｍ、リセス３０下の電子供給層の膜厚は例えば３から１０ｎｍとすることが好ましい。 Referring to FIG. 1C, the electron supply layer 22 and the electron transit layer 18 are dry-etched using a chlorine-based gas such as BCl 3 / Cl 2 . Thereby, the element isolation region 31 is formed. Note that an element isolation region may be formed using an ion implantation method. The electron supply layer 22 is dry-etched using, for example, chlorine-based gas to form a recess 30 having a depth of about 20 nm in the electron supply layer 22 (film thickness is 30 nm). The film thickness of the electron supply layer 22 is preferably 10 nm to 50 nm, for example, and the film thickness of the electron supply layer under the recess 30 is preferably 3 nm to 10 nm, for example.

図１（ｄ）を参照に、リセス３０の底面及び側面並びに電子供給層２２上に絶縁膜３２として１００ｎｍの厚さの酸化シリコン膜をＣＶＤ法またはスパッタ法を用い形成する。絶縁膜３２の膜厚は１００ｎｍ以上であることが好ましい。また、絶縁膜３２として、窒化シリコン膜、酸化アルミニウム膜、窒化アルミニウム膜等を用いることもできる。   Referring to FIG. 1D, a silicon oxide film having a thickness of 100 nm is formed as an insulating film 32 on the bottom and side surfaces of the recess 30 and the electron supply layer 22 by a CVD method or a sputtering method. The thickness of the insulating film 32 is preferably 100 nm or more. As the insulating film 32, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, or the like can be used.

図２（ａ）を参照に、リセス３０の絶縁膜３２をエッチングし絶縁膜３４を形成する。絶縁膜３４の膜厚は１０ｎｍから２０ｎｍとすることが好ましい。リセス３０とエッチングマスクの合わせマージンを確保するため、絶縁膜３４となる領域５６はリセス３０より広くすることが好ましい。   Referring to FIG. 2A, the insulating film 32 of the recess 30 is etched to form an insulating film 34. The thickness of the insulating film 34 is preferably 10 nm to 20 nm. In order to secure an alignment margin between the recess 30 and the etching mask, the region 56 to be the insulating film 34 is preferably wider than the recess 30.

図２（ｂ）を参照に、リセス３０の絶縁膜３４上にゲート電極４４としてＮｉ（ニッケル）／Ａｕ（金）を蒸着法及びリフトオフ法を用い形成する。ゲート電極４４としてはＮｉ／Ａｌ（アルミニウム）やＴａ（タンタル）／Ａｕ等を用いることもできる。ソース電極４０及びドレイン電極４２を形成すべき絶縁膜３２及び電子供給層２２の一部を除去し、電子供給層２２上にソース電極４０及びドレイン電極４２としてＴｉ／Ａｕを蒸着法及びリフトオフ法を用い形成する。ソース電極４０及びドレイン電流４２としてはＴｉ／Ａｌ等を用いることもできる。以上により実施例１に係るＦＥＴが完成する。   Referring to FIG. 2B, Ni (nickel) / Au (gold) is formed on the insulating film 34 of the recess 30 as a gate electrode 44 by vapor deposition and lift-off. As the gate electrode 44, Ni / Al (aluminum), Ta (tantalum) / Au, or the like can be used. A part of the insulating film 32 and the electron supply layer 22 on which the source electrode 40 and the drain electrode 42 are to be formed is removed, and Ti / Au is vapor deposited and lifted off as the source electrode 40 and the drain electrode 42 on the electron supply layer 22. Use to form. Ti / Al or the like can also be used as the source electrode 40 and the drain current 42. Thus, the FET according to Example 1 is completed.

実施例１によれば、基板１０と電子走行層１８との間にｐ型半導体層１４（ｐ型窒化物半導体層）が設けられている。これにより、電子走行層１８に形成された２ＤＥＧ２０のエネルギーレベルがフェルミレベルに対し高く持ち上がる。よって、２ＤＥＧ２０の電子濃度が低下し、Ｅモードを簡単に実現することができる。なお、ｐ型半導体層１４のキャリア濃度及び膜厚は目標とする閾値電圧に応じ適宜選択することができる。   According to Example 1, the p-type semiconductor layer 14 (p-type nitride semiconductor layer) is provided between the substrate 10 and the electron transit layer 18. As a result, the energy level of 2DEG 20 formed in the electron transit layer 18 is raised higher than the Fermi level. Therefore, the electron density of 2DEG 20 is reduced, and the E mode can be easily realized. The carrier concentration and the film thickness of the p-type semiconductor layer 14 can be appropriately selected according to the target threshold voltage.

しかしながら、ｐ型半導体層１４のドーパントであるＭｇは拡散し易い。また、Ｍｇが例えばＭＯＣＶＤ装置のチャンバ内に付着し、電子走行層１８を形成する際に電子走行層１８内にドープされてしまう。これにより、電子走行層１８がｐ型となってしまう。このため、ソース電極４０及びドレイン電極４２と電子走行層１８内の２ＤＥＧ２０との接触抵抗が高くなりトランジスタの電気的輸送特性が悪化してしまう。実施例１によれば、電子供給層２２に電子走行層１８に到達し、電気的に接続するｎ型注入領域２６が設けられている。これにより、ソース電極４０及びドレイン電極４２（つまりオーミック電極）と電子走行層１８内の２ＤＥＧ２０との接触抵抗を低減し、電気的輸送特性を向上させることができる。   However, Mg which is a dopant of the p-type semiconductor layer 14 is easily diffused. Further, Mg is deposited in the chamber of the MOCVD apparatus, for example, and is doped into the electron transit layer 18 when the electron transit layer 18 is formed. Thereby, the electron transit layer 18 becomes p-type. For this reason, the contact resistance between the source electrode 40 and the drain electrode 42 and the 2DEG 20 in the electron transit layer 18 is increased, and the electrical transport characteristics of the transistor are deteriorated. According to the first embodiment, the n-type injection region 26 that reaches the electron transit layer 18 and is electrically connected to the electron supply layer 22 is provided. As a result, the contact resistance between the source electrode 40 and the drain electrode 42 (that is, the ohmic electrode) and the 2DEG 20 in the electron transit layer 18 can be reduced, and the electrical transport characteristics can be improved.

また、ｐ型半導体層１４上にＡｌＮからなる拡散防止層１６を設けることが好ましい。これにより、ｐ型半導体層１４のドーパントであるＭｇが電子走行層１８に拡散することを抑制することができる。よって、ソース電極４０及びドレイン電極４２と２ＤＥＧ２０との接触抵抗を低減し、電気的輸送特性を向上させることができる。   Further, it is preferable to provide a diffusion prevention layer 16 made of AlN on the p-type semiconductor layer 14. Thereby, Mg which is a dopant of the p-type semiconductor layer 14 can be prevented from diffusing into the electron transit layer 18. Therefore, the contact resistance between the source electrode 40 and the drain electrode 42 and the 2DEG 20 can be reduced, and the electrical transport characteristics can be improved.

実施例２は絶縁膜として第１絶縁膜３６と第２絶縁膜３８とを形成する例である。図３（ａ）を参照に、実施例１の図１（ｃ）の後、リセス３０の底面及び側面並びに電子供給層２２上に第１絶縁膜３６として例えば１０ｎｍの厚さの窒化アルミニウム膜をスパッタ法を用い形成する。第１絶縁膜３６上に第２絶縁膜３８として例えば１００ｎｍの厚さの酸化シリコン膜をＣＶＤ法またはスパッタ法を用い形成する。これにより、第１絶縁膜３６と第２絶縁膜３８とからなる絶縁膜が形成される。   The second embodiment is an example in which a first insulating film 36 and a second insulating film 38 are formed as insulating films. Referring to FIG. 3A, after FIG. 1C of the first embodiment, an aluminum nitride film having a thickness of, for example, 10 nm is formed as the first insulating film 36 on the bottom and side surfaces of the recess 30 and the electron supply layer 22. It is formed using a sputtering method. A silicon oxide film having a thickness of, for example, 100 nm is formed on the first insulating film 36 as the second insulating film 38 by using a CVD method or a sputtering method. Thereby, an insulating film composed of the first insulating film 36 and the second insulating film 38 is formed.

図３（ｂ）を参照に、リセス３０内の第２絶縁膜３８を第１絶縁膜３６に対し選択的にエッチングし第１絶縁膜３６を残存させる。リセス３０とエッチングマスクとの合わせマージンを確保するため、第２絶縁膜３８をエッチングする領域５６はリセス３０より広くすることが好ましい。   Referring to FIG. 3B, the second insulating film 38 in the recess 30 is selectively etched with respect to the first insulating film 36 to leave the first insulating film 36. In order to secure an alignment margin between the recess 30 and the etching mask, the region 56 for etching the second insulating film 38 is preferably wider than the recess 30.

図３（ｃ）を参照に、実施例１の図２（ｂ）と同様に、ゲート電極４４、ソース電極４０及びドレイン電極４２を形成する。以上により実施例２に係るＦＥＴが完成する。   Referring to FIG. 3C, the gate electrode 44, the source electrode 40, and the drain electrode 42 are formed as in FIG. 2B of the first embodiment. Thus, the FET according to Example 2 is completed.

実施例２のように絶縁膜を第１絶縁膜３６及び第２絶縁膜３８で形成することもできる。ＦＥＴの閾値電圧を高くするため、第１絶縁膜３６の誘電率は高い方が好ましい。一方、寄生容量を小さくするため、第２絶縁膜３８の誘電率は小さいことが好ましい。よって、第１絶縁膜３６は第２絶縁膜３８より誘電率が大きいことが好ましい。窒化シリコン膜や窒化アルミニウム膜は、酸化シリコン膜や酸化アルミニウム膜より誘電率が大きい。よって、第１絶縁膜３６として窒化シリコン膜や窒化アルミニウム膜、第２絶縁膜３８として、酸化シリコン膜や酸化アルミニウム膜を用いることが好ましい。さらに、第１絶縁膜３６としては誘電率の大きい酸化ハフニウムや酸化ジルコニウムを用いることもできる。   As in Embodiment 2, the insulating film can be formed of the first insulating film 36 and the second insulating film 38. In order to increase the threshold voltage of the FET, the first insulating film 36 preferably has a high dielectric constant. On the other hand, the dielectric constant of the second insulating film 38 is preferably small in order to reduce the parasitic capacitance. Therefore, the first insulating film 36 preferably has a dielectric constant larger than that of the second insulating film 38. A silicon nitride film or an aluminum nitride film has a higher dielectric constant than a silicon oxide film or an aluminum oxide film. Therefore, it is preferable to use a silicon nitride film or an aluminum nitride film as the first insulating film 36 and a silicon oxide film or an aluminum oxide film as the second insulating film 38. Further, hafnium oxide or zirconium oxide having a large dielectric constant can be used as the first insulating film 36.

図４を参照に、実施例３に係るＦＥＴは、実施例１の図２（ｂ）に対し、ｐ型半導体層１４及び拡散防止層１６が設けられておらず、基板１０上に直接電子走行層１３として約２μｍの膜厚のｉ−ＧａＮが設けられている。また、電子走行層１３上に電子供給層２３としてＭｇを１×１０１９ｃｍ−３程度ドープし膜厚が３０ｎｍのｐ型のＡｌＧａＮ層が設けられている。電子供給層２３には深さが約２０ｎｍのリセス３０が設けられている。その他の構成は実施例１の図２（ｂ）と同じであり説明を省略する。 Referring to FIG. 4, the FET according to Example 3 is not provided with the p-type semiconductor layer 14 and the diffusion prevention layer 16 as compared with FIG. As the layer 13, i-GaN having a thickness of about 2 μm is provided. On the electron transit layer 13, a p-type AlGaN layer having a film thickness of 30 nm doped with about 1 × 10 19 cm −3 of Mg is provided as the electron supply layer 23. The electron supply layer 23 is provided with a recess 30 having a depth of about 20 nm. Other configurations are the same as those of the first embodiment shown in FIG.

実施例３では、窒化物半導体層２４は、基板１０上に設けられた電子走行層１３と、電子走行層１３上に設けられたｐ型の電子供給層２３と、を有している。ｐ型の電子供給層２３が設けられているため、２ＤＥＧ２０のエネルギーレベルをフェルミレベルに対し高く持ち上げることができる。よって、２ＤＥＧ２０の電子濃度が低下し、Ｅモードを簡単に実現することができる。   In Example 3, the nitride semiconductor layer 24 includes an electron transit layer 13 provided on the substrate 10 and a p-type electron supply layer 23 provided on the electron transit layer 13. Since the p-type electron supply layer 23 is provided, the energy level of 2DEG 20 can be raised higher than the Fermi level. Therefore, the electron density of 2DEG 20 is reduced, and the E mode can be easily realized.

また、ｎ型注入領域２６は、電子供給層２３から電子走行層１３の２ＤＥＧ２０に達するように設けられている。これにより、ソース電極４０及びドレイン電極４２と電子走行層１３内の２ＤＥＧ２０との接触抵抗を低減し、電気的輸送特性を向上させることができる。   The n-type injection region 26 is provided so as to reach the 2DEG 20 of the electron transit layer 13 from the electron supply layer 23. Thereby, the contact resistance between the source electrode 40 and the drain electrode 42 and the 2DEG 20 in the electron transit layer 13 can be reduced, and the electrical transport characteristics can be improved.

実施例３では、電子供給層２３がｐ型窒化物半導体層である例を示したが、電子供給層２３の少なくとも一部がｐ型窒化物半導体層であればよい。   Although the example in which the electron supply layer 23 is a p-type nitride semiconductor layer has been described in the third embodiment, at least a part of the electron supply layer 23 may be a p-type nitride semiconductor layer.

図５を参照に、実施例４に係るＦＥＴは、実施例１の図２（ｂ）に対し、ｐ型半導体層１５としてｐ型ＧａＮ層及び拡散防止層１７としてｉ−ＡｌＮ層が電子走行層１３のゲート電極４４下に選択的に設けられている。製造方法を以下に説明する。ＧａＮ電子走行層１３のうち下部層を成長した後、酸化シリコン等をマスク層としｐ型半導体層１５及び拡散防止層１７を選択的に形成する。マスク層を除去する。その後、電子走行層１３のうち上部層を成長する。または、電子走行層１３のうち下部層、ｐ型半導体層１５及び拡散防止層１７を積層した後、ｐ型半導体層１５及び拡散防止層１７の所定領域を除去する。その後、電子走行層１３のうち上部層を成長する。実施例４においても、実施例１の図２（ｂ）と同様に、ＥモードＦＥＴを実現することができる。   Referring to FIG. 5, the FET according to Example 4 is different from FIG. 2B of Example 1 in that the p-type GaN layer as the p-type semiconductor layer 15 and the i-AlN layer as the diffusion prevention layer 17 are the electron transit layer. 13 gate electrodes 44 are selectively provided. The manufacturing method will be described below. After the lower layer of the GaN electron transit layer 13 is grown, the p-type semiconductor layer 15 and the diffusion prevention layer 17 are selectively formed using silicon oxide or the like as a mask layer. The mask layer is removed. Thereafter, the upper layer of the electron transit layer 13 is grown. Alternatively, after the lower layer of the electron transit layer 13, the p-type semiconductor layer 15 and the diffusion prevention layer 17 are stacked, predetermined regions of the p-type semiconductor layer 15 and the diffusion prevention layer 17 are removed. Thereafter, the upper layer of the electron transit layer 13 is grown. Also in the fourth embodiment, an E-mode FET can be realized as in FIG. 2B of the first embodiment.

図６を参照に、実施例５に係るＦＥＴは、実施例１の図２（ｂ）に示したｐ型半導体層１４及び拡散防止層１６と実施例３の図４に示したｐ型の電子供給層２３とを有する。実施例５によれば、ｐ型半導体層１４と電子供給層２３とが２ＤＥＧ２０のエネルギーレベルをフェルミレベルに対し高く持ち上げるため、ＥモードＦＥＴをより実現することができる。   Referring to FIG. 6, the FET according to Example 5 includes the p-type semiconductor layer 14 and the diffusion prevention layer 16 shown in FIG. 2B of Example 1 and the p-type electron shown in FIG. 4 of Example 3. And a supply layer 23. According to the fifth embodiment, since the p-type semiconductor layer 14 and the electron supply layer 23 raise the energy level of 2DEG 20 higher than the Fermi level, an E-mode FET can be realized more.

図７を参照に、実施例６に係るＦＥＴは、実施例４の図５に示したゲート電極４４下に選択的に設けられたｐ型半導体層１５及び拡散防止層１７と実施例３の図４に示したｐ型の電子供給層２３とを有する構造である。実施例６においても、実施例５と同様に、ＥモードＦＥＴをより容易に実現することができる。   Referring to FIG. 7, the FET according to Example 6 shows the p-type semiconductor layer 15 and the diffusion prevention layer 17 selectively provided below the gate electrode 44 shown in FIG. 4 is a structure having the p-type electron supply layer 23 shown in FIG. In the sixth embodiment, as in the fifth embodiment, an E mode FET can be realized more easily.

図８を参照に、実施例７に係るＦＥＴは、実施例１の図２（ｂ）に対し、基板１０上にＡｌＮ層５０が設けられ、ＡｌＮ層５０上にｐ型半導体層５２としてｐ型のＡｌＧａＮ層及び拡散防止層１７としてｉ−ＡｌＮ層が設けられている。   Referring to FIG. 8, the FET according to Example 7 is different from FIG. 2B of Example 1 in that an AlN layer 50 is provided on the substrate 10 and a p-type semiconductor layer 52 is formed on the AlN layer 50 as a p-type semiconductor layer 52. An i-AlN layer is provided as the AlGaN layer and the diffusion preventing layer 17.

実施例７によれば、２ＤＥＧ２０は電子供給層２２とＡｌＧａＮ層のｐ型半導体層５２とで挟まれており、いわゆるダブルヘテロ接合型となっている。このように、電子走行層１８をそれより電子親和力の小さいＡｌＧａＮ層で挟むことにより、２ＤＥＧ２０のエネルギーレベルが高くなり、ＥモードＦＥＴを簡単に実現することができる。さらに、ｐ型半導体層５２下に電子走行層１８より電子親和力の小さいＡｌＮ層５０が設けられていることにより、２ＤＥＧ２０のエネルギーレベルはさらに高くなり、ＥモードＦＥＴをより簡単に実現することができる。   According to the seventh embodiment, the 2DEG 20 is sandwiched between the electron supply layer 22 and the p-type semiconductor layer 52 of the AlGaN layer, and is a so-called double heterojunction type. Thus, by sandwiching the electron transit layer 18 with an AlGaN layer having a smaller electron affinity, the energy level of 2DEG 20 is increased, and an E-mode FET can be easily realized. Furthermore, since the AlN layer 50 having a lower electron affinity than the electron transit layer 18 is provided under the p-type semiconductor layer 52, the energy level of the 2DEG 20 is further increased, and an E-mode FET can be realized more easily. .

図９を参照に、実施例８に係るＦＥＴは，実施例４の図５に対し、リセス３０内に選択的にｐ型半導体層５４としてｐ型ＧａＮ層が形成されている。製造方法は以下である。実施例１の図１（ｂ）の後に、リセス３０を形成するためのマスク層３９として酸化シリコン膜を形成する。リセス３０内にキャリア濃度が例えば３×１０１８ｃｍ−３のｐ型ＧａＮ層からなるｐ型半導体層５４を選択成長する。その後、実施例１の図１（ｄ）以降を行う。以上により実施例８に係るＦＥＴが完成する。 Referring to FIG. 9, in the FET according to the eighth embodiment, a p-type GaN layer is selectively formed as a p-type semiconductor layer 54 in the recess 30 with respect to FIG. 5 of the fourth embodiment. The manufacturing method is as follows. After FIG. 1B of the first embodiment, a silicon oxide film is formed as a mask layer 39 for forming the recess 30. A p-type semiconductor layer 54 made of a p-type GaN layer having a carrier concentration of, for example, 3 × 10 18 cm −3 is selectively grown in the recess 30. After that, FIG. Thus, the FET according to Example 8 is completed.

実施例８に係るＦＥＴは、ｐ型半導体層１５及び５４により、ゲート電極４４の直下の２ＤＥＧ２０の濃度が低下し、Ｅモードを簡単に実現することができる。また、ゲート電極４４直下以外の電子供給層２２や電子走行層１３にはｐ型領域が形成されていないため、ゲート電極４４直下以外の２ＤＥＧ２０の濃度は低下することがない。よって、相互コンダクタンス（ｇｍ）等の電気的輸送特性を劣化させることなくＥモードを実現することができる。   In the FET according to the eighth embodiment, the p-type semiconductor layers 15 and 54 reduce the concentration of 2DEG 20 immediately below the gate electrode 44, and can easily realize the E mode. In addition, since the p-type region is not formed in the electron supply layer 22 and the electron transit layer 13 other than directly below the gate electrode 44, the concentration of 2DEG 20 other than directly below the gate electrode 44 does not decrease. Therefore, the E mode can be realized without deteriorating electrical transport characteristics such as mutual conductance (gm).

図１０を参照に、実施例９に係るＦＥＴは、実施例８の図９に対し、基板１０上にＡｌＮ層５０が設けられ、ＡｌＮ層５０上のゲート電極４４下に選択的にｐ型半導体層５８としてｐ型のＡｌＧａＮ層及び拡散防止層１７としてｉ−ＡｌＮ層が設けられている。   Referring to FIG. 10, in the FET according to the ninth embodiment, an AlN layer 50 is provided on the substrate 10 with respect to FIG. 9 of the eighth embodiment, and a p-type semiconductor is selectively formed below the gate electrode 44 on the AlN layer 50. A p-type AlGaN layer is provided as the layer 58 and an i-AlN layer is provided as the diffusion preventing layer 17.

実施例９によれば、ｐ型半導体層５８がバンドギャップの大きいＡｌＧａＮ層であり、ｐ型半導体層５８下にバンドギャップの大きいＡｌＮ層５０が設けられている。これにより、実施例８よりさらに２ＤＥＧ２０のエネルギーレベルをフェルミレベルに対し高く持ち上げることができ、ＥモードＦＥＴをより実現することができる。   According to the ninth embodiment, the p-type semiconductor layer 58 is an AlGaN layer having a large band gap, and the AlN layer 50 having a large band gap is provided below the p-type semiconductor layer 58. As a result, the energy level of 2DEG 20 can be raised higher than the Fermi level as compared with the eighth embodiment, and an E-mode FET can be realized more.

ＥモードＦＥＴを実現するためには、２ＤＥＧ１３のエネルギーレベルをフェルミレベルに対し高く持ち上げることが求められる。そこで、実施例１から実施例９のように、窒化膜半導体層２４の一部をｐ型窒化物半導体層とすることにより、２ＤＥＧ２０のエネルギーレベルをフェルミレベルに対し高く持ち上げることができ、ＥモードＦＥＴを実現することができる。   In order to realize an E-mode FET, it is required to raise the energy level of 2DEG 13 higher than the Fermi level. Therefore, as in the first to ninth embodiments, by making a part of the nitride semiconductor layer 24 a p-type nitride semiconductor layer, the energy level of the 2DEG 20 can be raised higher than the Fermi level, and the E mode An FET can be realized.

また、実施例４、実施例６、実施例８及び実施例９のように、窒化物半導体層２４内のｐ型半導体層１５、５４または５８をゲート電極４４下に局所的選択的に配置することが好ましい。これにより、ｐ型層半導体層がソース電極４０及びドレイン電極４２下まで延在する場合に比べソース電極４０及びドレイン電極４２と２ＤＥＧ２０との接触抵抗を低減することができる。実施例８及び実施例９のように、リセス３０上にｐ型半導体層５４が設けられていることが好ましい。これにより、ｐ型半導体層５４をゲート電極４４下に局所的選択的に配置することができる。   Further, the p-type semiconductor layer 15, 54, or 58 in the nitride semiconductor layer 24 is locally and selectively disposed under the gate electrode 44 as in the fourth, sixth, eighth, and ninth embodiments. It is preferable. Thereby, the contact resistance between the source electrode 40 and the drain electrode 42 and the 2DEG 20 can be reduced as compared with the case where the p-type layer semiconductor layer extends below the source electrode 40 and the drain electrode 42. As in the eighth and ninth embodiments, the p-type semiconductor layer 54 is preferably provided on the recess 30. Thereby, the p-type semiconductor layer 54 can be locally and selectively disposed under the gate electrode 44.

実施例１から実施例９に係るＦＥＴは、電子供給層２２または２３のゲート電極４４が形成されるべき領域にリセス３０が設けられ、リセス３０上に絶縁膜３４、絶縁膜３４上にゲート電極４４が順に設けられている。このようにリセス構造を有することにより、電子供給層２２を薄く形成した場合もチャネル抵抗や電気的輸送特性の劣化を抑制することができる。よって、ＥモードＦＥＴを形成した場合、特に有利である。   In the FETs according to the first to ninth embodiments, the recess 30 is provided in the region where the gate electrode 44 of the electron supply layer 22 or 23 is to be formed, the insulating film 34 on the recess 30, and the gate electrode on the insulating film 34. 44 are provided in order. By having the recess structure in this manner, it is possible to suppress deterioration of channel resistance and electrical transport characteristics even when the electron supply layer 22 is formed thin. Therefore, it is particularly advantageous when an E mode FET is formed.

図１１を参照に、実施例１０は、電子供給層２２にリセス３０が設けられていない。その他の構成は実施例１と同じであり説明を省略する。実施例１０のように、リセス構造を有さない平面構造であってもよい。しかしながら、より閾値電圧を高く設定するためには、電子供給層２２または２３はリセス３０を有し、ゲート電極４４はリセス３０上に設けられていることが好ましい。   Referring to FIG. 11, in Example 10, the electron supply layer 22 is not provided with the recess 30. Other configurations are the same as those of the first embodiment, and the description thereof is omitted. As in Example 10, a planar structure without a recess structure may be used. However, in order to set the threshold voltage higher, it is preferable that the electron supply layer 22 or 23 has the recess 30 and the gate electrode 44 is provided on the recess 30.

また、実施例１から実施例１０において、ゲート電極４４は絶縁膜３４または３６を介さず、電子供給層２２若しくは２３またはｐ型半導体層５４上に直接設けられていてもよい。しかしながら、ゲート電極４４のリーク電流を抑制するためには、電子供給層２２または２３とゲート電極４４との間に絶縁膜３４または３６が設けられていることが好ましい。   In the first to tenth embodiments, the gate electrode 44 may be provided directly on the electron supply layer 22 or 23 or the p-type semiconductor layer 54 without the insulating film 34 or 36 interposed therebetween. However, in order to suppress the leakage current of the gate electrode 44, it is preferable that the insulating film 34 or 36 is provided between the electron supply layer 22 or 23 and the gate electrode 44.

実施例３から実施例１０は、実施例２のように、絶縁膜が第１絶縁膜３６と第２絶縁膜３８とから構成される場合であってもよい。   In the third to tenth embodiments, as in the second embodiment, the insulating film may be composed of the first insulating film 36 and the second insulating film 38.

実施例１から実施例１０において、拡散防止層１６または１７がＡｌＮ層からなる例を説明したが、拡散防止層１６または１７はＡｌを含む窒化物半導体層であればよい。例えばＡｌＧａＮのようにＡｌを含むことによりｐ型半導体層のドーパントの拡散を抑制することができる。ｐ型ドーパントの拡散を抑制するためには、拡散防止層１６または１７のＡｌの組成比は大きい方が好ましい。また、拡散防止層１６はＡｌＮ層であることがより好ましい。   In Examples 1 to 10, the example in which the diffusion prevention layer 16 or 17 is made of an AlN layer has been described. However, the diffusion prevention layer 16 or 17 may be a nitride semiconductor layer containing Al. For example, the diffusion of the dopant in the p-type semiconductor layer can be suppressed by including Al, such as AlGaN. In order to suppress the diffusion of the p-type dopant, it is preferable that the Al composition ratio of the diffusion preventing layer 16 or 17 is large. The diffusion preventing layer 16 is more preferably an AlN layer.

実施例１から実施例１０において、電子走行層１８または１３はＧａＮ層、電子供給層２２または２３はＡｌＧａＮ層を例に説明した。電子走行層１８または１３は窒化物半導体、電子供給層２２または２３は電子走行層１８または１３より電子親和力が小さい窒化物半導体であればよい。電子供給層２２または２３が電子走行層１８または１３より電子親和力が小さいことにより電子走行層１８または１３内にＤＥＧ２０を形成することができる。   In Examples 1 to 10, the electron transit layer 18 or 13 is described as an example of a GaN layer, and the electron supply layer 22 or 23 is described as an AlGaN layer. The electron transit layer 18 or 13 may be a nitride semiconductor, and the electron supply layer 22 or 23 may be a nitride semiconductor having an electron affinity smaller than that of the electron transit layer 18 or 13. Since the electron supply layer 22 or 23 has a lower electron affinity than the electron transit layer 18 or 13, the DEG 20 can be formed in the electron transit layer 18 or 13.

実施例１１は縦型のＦＥＴの例である。図１２（ａ）から図１３（ｃ）は実施例１１に係るＦＥＴの製造工程を示す断面図である。図１２（ａ）を参照に、立方晶（１１１）面を主面とするｎ型の３Ｃ−ＳｉＣ基板６０上に、窒化物半導体層７２ａとして、ｎ型のＧａＮドリフト層６２、ｐ型ＡｌＧａＮ電子制御層６４及びｎ型ＧａＮキャップ層６６をＭＯＣＶＤ法を用い六方晶（０００１）面を主面に形成する。基板６０は、Ｓｉをドーパントとし１０１８ｃｍ−３以上のキャリア濃度を有している。ドリフト層６２は、膜厚が例えば３μｍ以上でありＳｉを用い１０１５ｃｍ−３から１０１６ｃｍ−３のキャリア濃度を有している。電子制御層６４（ｐ型窒化物半導体層）は、膜厚が例えば２００ｎｍでありＭｇを用い１０１８ｃｍ−３程度のキャリア濃度を有し、組成比は例えばＡｌ０．２５Ｇａ０．７５Ｎである。キャップ層６６（コンタクト層）は、膜厚が例えば５００ｎｍでありＳｉを用い１０１８ｃｍ−３から１０１９ｃｍ−３のキャリア濃度を有している。 Example 11 is an example of a vertical FET. FIG. 12A to FIG. 13C are cross-sectional views illustrating the manufacturing steps of the FET according to the eleventh embodiment. Referring to FIG. 12A, an n-type GaN drift layer 62, p-type AlGaN electrons are formed as a nitride semiconductor layer 72a on an n-type 3C-SiC substrate 60 having a cubic (111) plane as a main surface. The control layer 64 and the n-type GaN cap layer 66 are formed by using the MOCVD method with the hexagonal (0001) plane as the main surface. The substrate 60 uses Si as a dopant and has a carrier concentration of 10 18 cm −3 or more. The drift layer 62 has a thickness of, for example, 3 μm or more, and has a carrier concentration of 10 15 cm −3 to 10 16 cm −3 using Si. The electron control layer 64 (p-type nitride semiconductor layer) has a thickness of, for example, 200 nm, has a carrier concentration of about 10 18 cm −3 using Mg, and has a composition ratio of, for example, Al 0.25 Ga 0.75 N. It is. The cap layer 66 (contact layer) has a film thickness of 500 nm, for example, and has a carrier concentration of 10 18 cm −3 to 10 19 cm −3 using Si.

図１２（ｂ）を参照に、キャップ層６６にＳｉをイオン注入しｎ型注入領域７４（ｎ型ドーパント領域）を形成する。図１２（ｃ）を参照に、例えば塩素系のドライエッチングを行うことにより窒化物半導体層７２ａにドリフト層６２に達する溝部７６を形成する。図１２（ｄ）を参照に、溝部７６内の側面、底面及びキャップ層６６上にｉ−ＧａＮ電子走行層６８及びｉ−ＡｌＮバリア層７０を形成する。これにより、電子制御層６４の側面に電子走行層６８及びバリア層７０が形成される。電子走行層６８及びバリア層７０の膜厚は例えば１０ｎｍから１００ｎｍとすることができる。これにより窒化物半導体層７２が形成される。   Referring to FIG. 12B, Si is ion-implanted into the cap layer 66 to form an n-type implantation region 74 (n-type dopant region). Referring to FIG. 12C, a groove 76 reaching the drift layer 62 is formed in the nitride semiconductor layer 72a by performing, for example, chlorine-based dry etching. Referring to FIG. 12D, the i-GaN electron transit layer 68 and the i-AlN barrier layer 70 are formed on the side surface, the bottom surface, and the cap layer 66 in the groove 76. Thereby, the electron transit layer 68 and the barrier layer 70 are formed on the side surface of the electron control layer 64. The film thickness of the electron transit layer 68 and the barrier layer 70 can be set to, for example, 10 nm to 100 nm. Thereby, the nitride semiconductor layer 72 is formed.

図１３（ａ）を参照に、ソース電極８０を形成すべき領域の電子走行層６８及びバリア層７０を除去する。キャップ層６６上にＴｉ／ＡｌまたはＴｉ／Ａｕからなるソース電極８０（第１電極）を蒸着法及びリフトオフ法を用い形成する。これにより、ソース電極８０はｎ型注入領域７４に接触して設けられる。図１３（ｂ）を参照に、溝部７６内にＮｉ／ＡｌまたはＮｉ／Ａｕからなるゲート電極８２（制御電極）を例えば蒸着法及びリフトオフ法を用い形成する。これにより、バリア層７０の電子走行層６８に対向する側面にゲート電極８２が形成される。図１３（ｃ）を参照に、基板６０を例えば２００μｍ以下の厚さとなるように研磨する。基板６０の下に基板６０に接続するようにＴｉ／ＡｌまたはＴｉ／Ａｕからなるドレイン電極８４（第２電極）を蒸着法及びリフトオフ法を用い形成する。   Referring to FIG. 13A, the electron transit layer 68 and the barrier layer 70 in the region where the source electrode 80 is to be formed are removed. A source electrode 80 (first electrode) made of Ti / Al or Ti / Au is formed on the cap layer 66 by vapor deposition and lift-off. Thereby, the source electrode 80 is provided in contact with the n-type implantation region 74. Referring to FIG. 13B, a gate electrode 82 (control electrode) made of Ni / Al or Ni / Au is formed in the groove 76 using, for example, a vapor deposition method and a lift-off method. Thereby, the gate electrode 82 is formed on the side surface of the barrier layer 70 facing the electron transit layer 68. Referring to FIG. 13C, the substrate 60 is polished so as to have a thickness of 200 μm or less, for example. A drain electrode 84 (second electrode) made of Ti / Al or Ti / Au is formed below the substrate 60 so as to be connected to the substrate 60 by using a vapor deposition method and a lift-off method.

図１３（ｃ）の矢印のように、実施例１１に係るＦＥＴにおいて、ソース電極８０からキャップ層６６に注入された電子は、電子制御層６４がＰ型でバリアとなるため電子走行層６８を通り、ドリフト層６２、基板６０を通りドレイン電極８４に至る。ゲート電極８２はソース電極８０とドレイン電極８４との間を流れる電流を制御する。言い換えれば、ゲート電極８２は窒化物半導体層７２上に設けられ、窒化物半導体層７２に流れる電流を制御する。このようにして、ＦＥＴとして動作する。ドリフト層６２及び基板６０によりドレイン耐圧を向上させることができる。   As indicated by the arrow in FIG. 13C, in the FET according to the example 11, the electrons injected from the source electrode 80 into the cap layer 66 are formed in the electron traveling layer 68 because the electron control layer 64 serves as a P-type barrier. To the drain electrode 84 through the drift layer 62 and the substrate 60. The gate electrode 82 controls the current flowing between the source electrode 80 and the drain electrode 84. In other words, the gate electrode 82 is provided on the nitride semiconductor layer 72 and controls the current flowing through the nitride semiconductor layer 72. In this way, it operates as an FET. The drain breakdown voltage can be improved by the drift layer 62 and the substrate 60.

実施例１１によれば、電子制御層６４中のＭｇがキャップ層６６を成長する際にキャップ層６６内に拡散する。また、ＭＯＣＶＤのチャンバ内に残留したＭｇがキャップ層６６に混入する。このため、キャップ層６６の電子が補償されキャップ層６６が高抵抗となってしまう。そこで、ｎ型注入領域７４を設けることにより、キャップ層６６の電子濃度を向上させることができる。よって、ソース電極８０と電子走行層６８との接触抵抗を低減することができる。   According to the eleventh embodiment, Mg in the electronic control layer 64 diffuses into the cap layer 66 when the cap layer 66 is grown. Further, Mg remaining in the MOCVD chamber is mixed into the cap layer 66. For this reason, electrons in the cap layer 66 are compensated, and the cap layer 66 becomes high resistance. Therefore, by providing the n-type injection region 74, the electron concentration of the cap layer 66 can be improved. Therefore, the contact resistance between the source electrode 80 and the electron transit layer 68 can be reduced.

実施例１２はＳｉＣドリフト層６３を有する例である。図１４を参照に、実施例１１のＧａＮドリフト層６２の代わりにＳｉＣドリフト層６３設けられている。ＳｉＣドリフト層６３上に窒化物半導体層７２ｂとしてＡｌＧａＮ電子制御層６４及びキャップ層６６をＭＯＣＶＤ法を用いに形成する。その他の構成は実施例１１と同じであり説明を省略する。このように、基板６０と窒化物半導体層７２ｂとの間にＳｉＣドリフト層６３を設けることができる。   Example 12 is an example having a SiC drift layer 63. Referring to FIG. 14, an SiC drift layer 63 is provided instead of the GaN drift layer 62 of the eleventh embodiment. On the SiC drift layer 63, an AlGaN electron control layer 64 and a cap layer 66 are formed as a nitride semiconductor layer 72b using the MOCVD method. Other configurations are the same as those of the eleventh embodiment, and a description thereof will be omitted. Thus, the SiC drift layer 63 can be provided between the substrate 60 and the nitride semiconductor layer 72b.

実施例１１及び実施例１２は縦型のＦＥＴの例であったが、窒化物半導体層７２内にｐ型窒化物半導体層が設けられていれば、同様の効果を奏することができる。縦型のトランジスタとして、窒化物半導体層７２上に設けられた第１電極と基板６０に設けられた第２電極との間を電流が流れるトランジスタでもよい。例えば、第１電極がエミッタ電極、第２電極がコレクタ電極、制御電極がベース電極であるバイポーラトランジスタ、第１電極がエミッタ電極、第２電極がコレクタ電極、制御電極がゲート電極であるＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）とすることもできる。なお、ＨＢＴ及びＩＧＢＴにおいては、オーミック電極はエミッタ電極またはコレクタ電極であり、電子走行層はベース電極またはコレクタ電極が電気的に接触するｎ型のベース層またはコレクタ層である。   Although Example 11 and Example 12 are examples of vertical FETs, the same effect can be obtained if a p-type nitride semiconductor layer is provided in the nitride semiconductor layer 72. The vertical transistor may be a transistor in which current flows between a first electrode provided on the nitride semiconductor layer 72 and a second electrode provided on the substrate 60. For example, a bipolar transistor in which the first electrode is an emitter electrode, the second electrode is a collector electrode, and the control electrode is a base electrode, the first electrode is an emitter electrode, the second electrode is a collector electrode, and the control electrode is an IGBT (insulation) Gate type bipolar transistor). In the HBT and IGBT, the ohmic electrode is an emitter electrode or a collector electrode, and the electron transit layer is an n-type base layer or collector layer with which the base electrode or collector electrode is in electrical contact.

実施例１から実施例１２においては、電子走行層１８、１３または６８と電気的に接続するｎ型注入領域２６または７４が設けられ、ｎ型注入領域２６または７４に接触して設けられたオーミック電極（ソース電極４０若しくは８０またはドレイン電極４２）が設けられている。これにより、窒化物半導体層２４または７２内に設けられたｐ型半導体層１４、１５、５２、５４、５８、ｐ型電子供給層２３または電子制御層６４に起因したオーミック電極と電子走行層１３、１８または６８との接触抵抗の悪化を抑制することができる。   In Example 1 to Example 12, an n-type injection region 26 or 74 that is electrically connected to the electron transit layer 18, 13, or 68 is provided, and an ohmic provided in contact with the n-type injection region 26 or 74 is provided. An electrode (source electrode 40 or 80 or drain electrode 42) is provided. Thereby, the ohmic electrode and the electron transit layer 13 caused by the p-type semiconductor layers 14, 15, 52, 54, 58, the p-type electron supply layer 23 or the electron control layer 64 provided in the nitride semiconductor layer 24 or 72. , 18 or 68 can be prevented from deteriorating contact resistance.

ｐ型半導体層１４、１５、５２、５４、５８、ｐ型電子供給層２３及び電子制御層６４のドーパントとしてＭｇを例に説明したが、ｐ型のドーパントは、Ｂｅ（ベリリウム）、Ｚｎ（亜鉛）またはＣ(炭素）等でもよい。しかしながら、Ｍｇは窒化物半導体層に拡散し易く、ＭＯＣＶＤ装置のチャンバ内に付着しやすいため、Ｍｇをドーパントとした半導体装置に本発明の構成を適用することが特に有効である。   As the dopant of the p-type semiconductor layers 14, 15, 52, 54, 58, the p-type electron supply layer 23 and the electron control layer 64, Mg has been described as an example, but the p-type dopant is Be (beryllium), Zn (zinc) ) Or C (carbon). However, since Mg easily diffuses into the nitride semiconductor layer and easily adheres to the chamber of the MOCVD apparatus, it is particularly effective to apply the configuration of the present invention to a semiconductor device using Mg as a dopant.

以上、発明の好ましい実施形態について詳述したが、本発明は係る特定の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。
The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

図１（ａ）から図１（ｄ）は実施例１に係るＦＥＴの製造工程を示し断面図（その１）である。FIG. 1A to FIG. 1D are cross-sectional views (part 1) showing the manufacturing process of the FET according to the first embodiment. 図２（ａ）及び図２（ｂ）は実施例１に係るＦＥＴの製造工程を示す断面図（その２）である。2A and 2B are cross-sectional views (part 2) illustrating the manufacturing process of the FET according to the first embodiment. 図３（ａ）から図３（ｃ）は実施例２に係るＦＥＴの製造工程を示す断面図である。FIG. 3A to FIG. 3C are cross-sectional views illustrating the manufacturing process of the FET according to the second embodiment. 図４は実施例３に係るＦＥＴの断面図である。FIG. 4 is a cross-sectional view of the FET according to the third embodiment. 図５は実施例４に係るＦＥＴの断面図である。FIG. 5 is a cross-sectional view of the FET according to the fourth embodiment. 図６は実施例５に係るＦＥＴの断面図である。FIG. 6 is a cross-sectional view of the FET according to the fifth embodiment. 図７は実施例６に係るＦＥＴの断面図である。FIG. 7 is a cross-sectional view of the FET according to the sixth embodiment. 図８は実施例７に係るＦＥＴの断面図である。FIG. 8 is a cross-sectional view of the FET according to the seventh embodiment. 図９は実施例８に係るＦＥＴの断面図である。FIG. 9 is a cross-sectional view of the FET according to the eighth embodiment. 図１０は実施例９に係るＦＥＴの断面図である。FIG. 10 is a cross-sectional view of the FET according to the ninth embodiment. 図１１は実施例１０に係るＦＥＴの断面図である。FIG. 11 is a cross-sectional view of the FET according to the tenth embodiment. 図１２（ａ）から図１２（ｄ）は実施例１１に係るＦＥＴの製造方法を示す断面図（その１）である。12A to 12D are cross-sectional views (part 1) illustrating the method for manufacturing the FET according to the eleventh embodiment. 図１３（ａ）から図１３（ｃ）は実施例１１に係るＦＥＴの製造方法を示す断面図（その２）である。FIG. 13A to FIG. 13C are sectional views (No. 2) showing the method for manufacturing the FET according to the eleventh embodiment. 図１４は実施例１２に係るＦＥＴの断面図である。14 is a cross-sectional view of an FET according to Example 12. FIG.

符号の説明Explanation of symbols

１０ 基板
１２ バッファ層
１３ 電子走行層
１４、１５ ｐ型半導体層
１６、１７ 拡散防止層
１８ 電子走行層
２０ ２ＤＥＧ
２２ 電子供給層
２３ ｐ型電子供給層
２４ 窒化物半導体層
２６ ｎ型注入領域
３０ リセス
３２、３４ 絶縁膜
３６ 第１絶縁膜
３８ 第２絶縁膜
３９ マスク層
４０ ソース電極
４２ ドレイン電極
４４ ゲート電極
５０ ＡｌＮ層
５２、５４、５８ ｐ型半導体層
６０ 基板
６２、６３ ドリフト層
６４ 電子制御層
６６ キャップ層
６８ 電子走行層
７０ バリア層
７２ 窒化物半導体層
７６ 溝部
７８ ｎ型注入領域
８０ ソース電極
８２ ゲート電極
８４ ドレイン電極 DESCRIPTION OF SYMBOLS 10 Substrate 12 Buffer layer 13 Electron travel layer 14, 15 p-type semiconductor layer 16, 17 Diffusion prevention layer 18 Electron travel layer 20 2DEG
22 Electron supply layer 23 P-type electron supply layer 24 Nitride semiconductor layer 26 N-type injection region 30 Recess 32, 34 Insulating film 36 First insulating film 38 Second insulating film 39 Mask layer 40 Source electrode 42 Drain electrode 44 Gate electrode 50 AlN layer 52, 54, 58 p-type semiconductor layer 60 substrate 62, 63 drift layer 64 electron control layer 66 cap layer 68 electron transit layer 70 barrier layer 72 nitride semiconductor layer 76 groove 78 n-type injection region 80 source electrode 82 gate electrode 84 Drain electrode

Claims (10)

基板上に設けられ電子走行層及び電子供給層を有する窒化物半導体層と、
前記窒化物半導体層内に設けられたｐ型窒化物半導体層と、
前記窒化物半導体層内に設けられ前記電子走行層に到達するｎ型ドーピング領域と、
前記電子供給層上に設けられたゲート電極と、
前記ｎ型ドーピング領域に接触して設けられたオーミック電極と、
を具備することを特徴とする半導体装置。 A nitride semiconductor layer provided on a substrate and having an electron transit layer and an electron supply layer;
A p-type nitride semiconductor layer provided in the nitride semiconductor layer;
An n-type doping region provided in the nitride semiconductor layer and reaching the electron transit layer;
A gate electrode provided on the electron supply layer;
An ohmic electrode provided in contact with the n-type doping region;
A semiconductor device comprising: 前記ｐ型窒化物半導体層は、前記基板と前記電子走行層との間に設けられていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the p-type nitride semiconductor layer is provided between the substrate and the electron transit layer. 前記ｐ型窒化物半導体層上にＡｌを含む窒化物半導体からなる拡散防止層を具備することを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, further comprising a diffusion prevention layer made of a nitride semiconductor containing Al on the p-type nitride semiconductor layer. 前記ｐ型窒化物半導体層は前記ゲート電極の下に選択的に設けられていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the p-type nitride semiconductor layer is selectively provided under the gate electrode. 前記電子供給層はリセスを有し、前記ゲート電極は前記リセス上に設けられていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the electron supply layer has a recess, and the gate electrode is provided on the recess. 前記電子供給層と前記ゲート電極との間に設けられた絶縁層を具備することを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, further comprising an insulating layer provided between the electron supply layer and the gate electrode. 前記電子供給層は前記ｐ型窒化物半導体層を含むことを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the electron supply layer includes the p-type nitride semiconductor layer. 前記リセス上に、ｐ型半導体層が設けられていることを特徴とする請求項５記載の半導体装置。   6. The semiconductor device according to claim 5, wherein a p-type semiconductor layer is provided on the recess. 前記半導体装置はエンハンスメント・モードであることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the semiconductor device is in an enhancement mode. 基板上に設けられた窒化物半導体層と、
前記窒化物半導体層内に設けられたｐ型窒化物半導体層及びｐ型窒化物半導体層上に設けられたｎ型コンタクト層と、
前記ｎ型コンタクト層に到達するｎ型ドーピング領域と、
前記ｎ型ドーピング領域に接触して設けられた第１電極と、
前記基板に接続された第２電極と、
前記第１電極と前記第２電極との間を流れる電流を制御する制御電極と、
を具備することを特徴とする半導体装置。 A nitride semiconductor layer provided on the substrate;
A p-type nitride semiconductor layer provided in the nitride semiconductor layer and an n-type contact layer provided on the p-type nitride semiconductor layer;
An n-type doping region reaching the n-type contact layer;
A first electrode provided in contact with the n-type doping region;
A second electrode connected to the substrate;
A control electrode for controlling a current flowing between the first electrode and the second electrode;
A semiconductor device comprising:
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