JP2011108712A - Nitride semiconductor device - Google Patents

Nitride semiconductor device Download PDF

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JP2011108712A
JP2011108712A JP2009259587A JP2009259587A JP2011108712A JP 2011108712 A JP2011108712 A JP 2011108712A JP 2009259587 A JP2009259587 A JP 2009259587A JP 2009259587 A JP2009259587 A JP 2009259587A JP 2011108712 A JP2011108712 A JP 2011108712A
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nitride semiconductor
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Yoshimichi Fukazawa
義道 深澤
Hiroshi Fushimi
浩 伏見
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New Japan Radio Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a normally-off type nitride semiconductor device with a small gate leakage current that is promising as a high-output high-frequency device semiconductor and is for practical use of a high electron mobility transistor (HEMT). <P>SOLUTION: An electron supply layer 3 which is made of an n-type or undoped first nitride semiconductor, and an electron transit layer 4 which forms a heterojunction with the electron supply layer 3, produces a two-dimensional electron gas through by the heterojunction, and has a smaller band gap than the electron supply layer 3, and is made of an undoped second nitride semiconductor are laminated on a substrate 1 with a buffer layer 2 interposed therebetween, and a surface of the electron transit layer 4 laminated on the electron supply layer 3 or a surface of the electron supply layer 4 laminated on the electron transit layer 4 is coated with a cap layer 5 comprising a p-type third nitride semiconductor. A gate electrode 8 is formed on the cap layer 5. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、窒化物半導体装置に関し、特にノーマリオフ型の高電子移動度トランジスタを構成する窒化物半導体装置に関する。   The present invention relates to a nitride semiconductor device, and more particularly to a nitride semiconductor device constituting a normally-off type high electron mobility transistor.

ＧａＮ、ＡｌＧａＮ、ＩｎＧａＮ、ＩｎＡｌＮ、ＩｎＡｌＧａＮなどの窒化物半導体は、絶縁破壊電界および電子飽和速度が高いという優れた特性を有している。この優れた特性により、高出力の高周波デバイスを実現できる半導体材料として有望であり、近年、高電子移動度トランジスタ（ＨＥＭＴ）の実用化開発が進められている。   Nitride semiconductors such as GaN, AlGaN, InGaN, InAlN, and InAlGaN have excellent characteristics such as a high breakdown electric field and a high electron saturation rate. Due to this excellent characteristic, it is promising as a semiconductor material capable of realizing a high-output high-frequency device, and in recent years, practical development of a high electron mobility transistor (HEMT) has been advanced.

図５に、従来のＨＥＭＴ構造の窒化物半導体装置の断面図を示す。図５に示すように、サファイア（Ａｌ2Ｏ3）、炭化ケイ素（ＳｉＣ）またはシリコン（Ｓｉ）等からなる基板１上に、バッファ層２を介してアンドープのＧａＮ等からなる電子走行層４と、ｎ型不純物がドープされた、あるいはアンドープのＡｌＧａＮ等からなる電子供給層３とが形成されている。そして、電子供給層３上には、オーミック接触するソース電極６、ドレイン電極７と、ソース電極６とドレイン電極７間に流れる電流を制御するゲート電極８が形成されている。電子供給層３のバンドギャップは電子走行層４のバンドギャップより大きく、電子供給層３の格子定数は電子走行層４の格子定数よりも小さくなるような材料で、電子供給層３および電子走行層４を構成されている。その結果、電子供給層３に引っ張り応力によるピエゾ分極および自発分極が生じ、ヘテロ接合近傍の電子走行層４側に、電子移動度が極めて大きい二次元電子ガス１０が発生する。二次元電子ガス１０は、チャネルとなり、ゲート電極８に印加されるバイアス電圧を制御することで、ソース電極６、ドレイン電極７間に流れる電流を制御することができる。 FIG. 5 shows a cross-sectional view of a conventional nitride semiconductor device having a HEMT structure. As shown in FIG. 5, an electron transit layer 4 made of undoped GaN or the like is formed on a substrate 1 made of sapphire (Al 2 O 3 ), silicon carbide (SiC), silicon (Si) or the like via a buffer layer 2. An electron supply layer 3 doped with n-type impurities or made of undoped AlGaN or the like is formed. On the electron supply layer 3, a source electrode 6 and a drain electrode 7 that are in ohmic contact, and a gate electrode 8 that controls a current flowing between the source electrode 6 and the drain electrode 7 are formed. The electron supply layer 3 is made of a material whose band gap is larger than that of the electron transit layer 4 and whose lattice constant is smaller than that of the electron transit layer 4. 4 is configured. As a result, piezoelectric polarization and spontaneous polarization are generated in the electron supply layer 3 due to tensile stress, and a two-dimensional electron gas 10 having extremely high electron mobility is generated on the electron transit layer 4 side near the heterojunction. The two-dimensional electron gas 10 becomes a channel, and the current flowing between the source electrode 6 and the drain electrode 7 can be controlled by controlling the bias voltage applied to the gate electrode 8.

ところで、このような構造の窒化物半導体装置は、ゲート電極８にバイアス電圧を印加しない状態で、ソース電極６、ドレイン電極７間に電流が流れるノーマリオン（ディプレッション）型となっている。このようなノーマルオン型の窒化物半導体装置をオフ状態（チャネルにキャリアが流れない状態）に保つためには、ゲート電極８に負のバイアス電圧を印加する必要がある。そのため、ゲート電極８にバイアス電圧を印加しない状態で、ソース電極６、ドレイン電極７間に電流が流れないノーマリオフ（エンハンスメント）型の窒化物半導体装置の開発が進められている。   By the way, the nitride semiconductor device having such a structure is a normally-on (depletion) type in which a current flows between the source electrode 6 and the drain electrode 7 without applying a bias voltage to the gate electrode 8. In order to keep such a normally-on type nitride semiconductor device in an off state (a state where carriers do not flow through the channel), it is necessary to apply a negative bias voltage to the gate electrode 8. Therefore, development of a normally-off (enhancement) type nitride semiconductor device in which a current does not flow between the source electrode 6 and the drain electrode 7 without applying a bias voltage to the gate electrode 8 is underway.

ノーマリオフ型の窒化物半導体装置を実現する方法が、特許文献１に開示されている。この方法によれば、電子供給層３の一部をエッチング除去してゲートリセス構造とし、ゲート電極とチャネルとなる二次元電子ガスとの距離を短くすることにより、ショットキー障壁に基づく電界がヘテロ接合に対して作用しやすくし、ゲート電極８にバイアス電圧を印加しない状態で、ゲート電極８直下の二次元電子ガス１０を消失させ、ノーマリオフ型の窒化物半導体装置を実現している。   A method for realizing a normally-off type nitride semiconductor device is disclosed in Patent Document 1. According to this method, a part of the electron supply layer 3 is etched away to form a gate recess structure, and the distance between the gate electrode and the two-dimensional electron gas serving as the channel is shortened, so that the electric field based on the Schottky barrier is heterojunction. The two-dimensional electron gas 10 immediately below the gate electrode 8 is eliminated in a state where no bias voltage is applied to the gate electrode 8 to realize a normally-off type nitride semiconductor device.

また別の方法として、基板１上にバッファ層２を介して、ｎ型またはアンドープのＡｌＧａＮからなる電子供給層３と、アンドープのＧａＮからなる電子走行層４とを順に積層し、電子走行層４上にソース電極６、ドレイン電極７およびゲート電極８を形成する方法がある。これは、電子供給層３と電子走行層４を一般的な構成のＨＥＭＴ構造とは逆側に積層させることで、二次元電子ガス１０がヘテロ接合近傍のゲート電極８側に生成し、電子走行層４の膜厚の制御を行うことで、ノーマリオフ型とする方法である。   As another method, an electron supply layer 3 made of n-type or undoped AlGaN and an electron transit layer 4 made of undoped GaN are sequentially laminated on the substrate 1 with a buffer layer 2 interposed therebetween. There is a method of forming the source electrode 6, the drain electrode 7 and the gate electrode 8 thereon. This is because the electron supply layer 3 and the electron transit layer 4 are stacked on the opposite side of the HEMT structure having a general configuration, so that a two-dimensional electron gas 10 is generated on the gate electrode 8 side near the heterojunction, and the electron transit In this method, the film thickness of the layer 4 is controlled so as to be a normally-off type.

特開２００８−１４１０４０号公報JP 2008-144104 A

上記のような従来のノーマリオフ型の窒化物半導体装置は、ノーマリオフ動作は実現しているが、しきい値電圧が比較的低く、ノイズによって誤動作しやすいという問題点があった。また、ゲート電極に正のバイアス電圧を印加するとゲートリーク電流が増大するという問題点があった。   The conventional normally-off type nitride semiconductor device as described above realizes the normally-off operation, but has a problem that it has a relatively low threshold voltage and is likely to malfunction due to noise. Further, when a positive bias voltage is applied to the gate electrode, there is a problem that the gate leakage current increases.

本発明は、上記問題点を解消し、ゲートリーク電流の少ないノーマリオフ型の窒化物半導体装置を提供することを目的とする。   An object of the present invention is to solve the above-described problems and provide a normally-off type nitride semiconductor device with a small gate leakage current.

上記目的を達成するため本願発明の窒化物半導体装置は、基板上に、バッファ層を介して、ｎ型もしくはアンドープの第一の窒化物半導体からなる電子供給層と、前記電子供給層とヘテロ接合し、かつ該ヘテロ接合によって二次元電子ガスを形成する、前記電子供給層よりバンドギャップが小さいアンドープの第二の窒化物半導体からなる電子走行層とが積層し、前記電子走行層に電気的に接続するソース電極およびドレイン電極と、該ソース電極およびドレイン電極間の電流を制御するゲート電極を備えた窒化物半導体装置において、
前記電子供給層上に積層した前記電子走行層表面を、あるいは前記電子走行層上に積層した前記電子供給層表面を、ｐ型の第三の窒化物半導体からなるキャップ層で被覆し、該キャップ層に前記ゲート電極が接触していることを特徴とする。 In order to achieve the above object, a nitride semiconductor device of the present invention includes an electron supply layer made of an n-type or undoped first nitride semiconductor and a heterojunction with the electron supply layer on a substrate via a buffer layer. And an electron transit layer made of an undoped second nitride semiconductor having a band gap smaller than that of the electron supply layer, which forms a two-dimensional electron gas by the heterojunction, and is electrically stacked on the electron transit layer. In a nitride semiconductor device including a source electrode and a drain electrode to be connected and a gate electrode for controlling a current between the source electrode and the drain electrode,
The surface of the electron transit layer stacked on the electron supply layer or the surface of the electron supply layer laminated on the electron transit layer is covered with a cap layer made of a p-type third nitride semiconductor, and the cap The gate electrode is in contact with the layer.

本発明によれば、ゲート電極をｐ型の窒化物半導体からなるキャップ層に接触するように構成することで、ショットキー障壁を高くすることができ、ゲートリーク電流を少なくすることができる。また、ｐ型の窒化物半導体は、正孔が多数キャリアであるため、ゲート−ソース間電圧は逆バイアスとなり、ゲート電極に正のバイアス電圧を印加しても、ゲートリーク電流が増加することがないという利点がある。   According to the present invention, by configuring the gate electrode so as to be in contact with the cap layer made of the p-type nitride semiconductor, the Schottky barrier can be increased and the gate leakage current can be reduced. In addition, since the p-type nitride semiconductor has a majority of holes, the gate-source voltage is reverse-biased, and even if a positive bias voltage is applied to the gate electrode, the gate leakage current may increase. There is no advantage.

本発明の第１の実施例の窒化物半導体装置の断面図である。1 is a cross-sectional view of a nitride semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施例の窒化物半導体装置の伝達特性である。It is a transfer characteristic of the nitride semiconductor device of the 1st example of the present invention. 本発明の第１の実施例の窒化物半導体装置のゲートリーク電流特性である。It is the gate leakage current characteristic of the nitride semiconductor device of the 1st Example of this invention. 本発明の第２の実施例の窒化物半導体装置の断面図である。It is sectional drawing of the nitride semiconductor device of the 2nd Example of this invention. 従来のＨＥＭＴ構造の窒化物半導体装置の断面図である。It is sectional drawing of the nitride semiconductor device of the conventional HEMT structure.

本発明は、ゲート電極をｐ型の窒化物半導体層に接触するように形成することを大きな特徴としている。以下、本発明の実施例について、ＨＥＭＴ構造の窒化物半導体装置を例にとり、詳細に説明する。   The present invention is characterized in that the gate electrode is formed so as to be in contact with the p-type nitride semiconductor layer. Hereinafter, embodiments of the present invention will be described in detail by taking a nitride semiconductor device having a HEMT structure as an example.

図１は、本発明の第１の実施例の窒化物半導体装置の断面図である。図１に示すように、基板１上に、ＭＯＣＶＤ（有機金属気相エピタキシャル成長）法もしくはＭＢＥ（分子線エピタキシャル成長）法等により、バッファ層２を介して、第一の窒化物半導体からなる電子供給層３、第二の窒化物半導体からなる電子走行層４、ｐ型不純物をドープした（第三の窒化物半導体に相当）キャップ層５が順に積層されている。キャップ層５上には、ソース電極６、ドレイン電極７およびゲート電極８が形成されている。   FIG. 1 is a sectional view of a nitride semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, an electron supply layer made of a first nitride semiconductor is formed on a substrate 1 via a buffer layer 2 by MOCVD (metal organic vapor phase epitaxy) or MBE (molecular beam epitaxy). 3. An electron transit layer 4 made of a second nitride semiconductor, and a cap layer 5 doped with a p-type impurity (corresponding to a third nitride semiconductor) are sequentially laminated. A source electrode 6, a drain electrode 7, and a gate electrode 8 are formed on the cap layer 5.

基板１は、窒化物半導体層をエピタキシャル成長させるための成長基板として機能し、機械的に支持するための支持基板としても機能する。基板１は、一般にサファイア（Ａｌ2Ｏ3）、炭化ケイ素（ＳｉＣ）あるいはシリコン（Ｓｉ）が用いられ、格子定数の整合性、熱伝導率、熱膨張係数等を考慮し、基板１上に成長させる窒化物半導体層に応じて選択することができる。本実施例では、後述する窒化物半導体層との格子定数の整合性等を考慮し、サファイアを使用した。 The substrate 1 functions as a growth substrate for epitaxially growing the nitride semiconductor layer and also functions as a support substrate for mechanical support. The substrate 1 is generally made of sapphire (Al 2 O 3 ), silicon carbide (SiC), or silicon (Si), and is grown on the substrate 1 in consideration of lattice constant matching, thermal conductivity, thermal expansion coefficient, and the like. It can be selected according to the nitride semiconductor layer to be formed. In this example, sapphire was used in consideration of the lattice constant matching with the nitride semiconductor layer described later.

バッファ層２は、基板１とその上にエピタキシャル成長される第一の窒化物半導体との緩衝層として用いられる。本実施例では、基板１として用いるサファイアと窒化物半導体との格子不整合が大きいため、バッファ層２として、サファイア上に窒化アルミニウム（ＡｌＮ）層をエピタキシャル成長させた後、アンドープ窒化ガリウム（ＧａＮ）層を２μｍ程度の厚さまで厚く成長させ、さらにｎ型ＧａＮ層を成長させる。ｎ型ＧａＮ層は、その上に成長させる第一の窒化物半導体からなる電子供給層３とのヘテロ接合界面に二次元電子ガスが発生するのを抑制するために導入している。なお、このバッファ層２はＨＥＭＴの動作に直接に関係しないので、バッファ層２の半導体材料をＡｌＮ、ＧａＮ以外の窒化物半導体またはIII−Ｖ族化合物半導体に置き換えるたり、単層構造のバッファ層とすることもできる。   The buffer layer 2 is used as a buffer layer between the substrate 1 and the first nitride semiconductor epitaxially grown thereon. In this embodiment, since the lattice mismatch between the sapphire used as the substrate 1 and the nitride semiconductor is large, an aluminum nitride (AlN) layer is epitaxially grown on the sapphire as the buffer layer 2 and then an undoped gallium nitride (GaN) layer. Is grown to a thickness of about 2 μm, and an n-type GaN layer is further grown. The n-type GaN layer is introduced to suppress the generation of a two-dimensional electron gas at the heterojunction interface with the electron supply layer 3 made of the first nitride semiconductor grown on the n-type GaN layer. Since the buffer layer 2 is not directly related to the operation of the HEMT, the semiconductor material of the buffer layer 2 is replaced with a nitride semiconductor other than AlN or GaN or a III-V group compound semiconductor, or a buffer layer having a single layer structure is used. You can also

電子供給層３は、厚さ２０ｎｍ、ｎ型あるいはアンドープのＡｌ0.25Ｇａ0.75Ｎ層で構成する。また、電子供給層３は、ｎ型あるいはアンドープのＡｌxＩｎyＧａ1-x-yＮで構成することもできる。ここで、ｘは０＜ｘ≦１、ｙは０≦ｙ＜１、およびｘ＋ｙはｘ＋ｙ≦１を満足する数値であり、ｘの好ましい値は０.１〜０.４である。 The electron supply layer 3 is composed of a 20 nm thick, n-type or undoped Al 0.25 Ga 0.75 N layer. Further, the electron supply layer 3 can be composed of n-type or undoped Al x In y Ga 1 -xy N. Here, x is 0 <x ≦ 1, y is 0 ≦ y <1, and x + y is a numerical value satisfying x + y ≦ 1, and a preferable value of x is 0.1 to 0.4.

電子走行層４は、厚さ２０ｎｍ、アンドープのＧａＮ層で構成する。この電子走行層４は、電子供給層３で用いた窒化物半導体（第一の窒化物半導体に相当）よりも小さいバンドギャップと格子定数を有する窒化物半導体で構成され、この電子走行層４と電子供給層３とのヘテロ接合近傍には、チャネルとなる二次元電子ガス１０が生成する。また、アンドープのＧａＮ層とすることで、イオン不純物散乱による二次元電子ガス１０の移動度低下を防ぐことができる。なお、電子走行層４はＧａＮ以外に、例えば、ＩｎaＧａ1-aＮで構成することもできる。ここで、ａは０≦ａ＜１を満足する数値である。 The electron transit layer 4 is composed of an undoped GaN layer having a thickness of 20 nm. The electron transit layer 4 is composed of a nitride semiconductor having a smaller band gap and lattice constant than the nitride semiconductor (corresponding to the first nitride semiconductor) used in the electron supply layer 3. In the vicinity of the heterojunction with the electron supply layer 3, a two-dimensional electron gas 10 serving as a channel is generated. Moreover, by using an undoped GaN layer, it is possible to prevent a decrease in mobility of the two-dimensional electron gas 10 due to ion impurity scattering. Note that the electron transit layer 4 may be composed of, for example, In a Ga 1-a N in addition to GaN. Here, a is a numerical value satisfying 0 ≦ a <1.

ノーマリオフ型の窒化物半導体装置を形成するため、電子走行層４の厚さは、ゲート電極８にバイアス電圧を印加しない状態で、ゲート電極８直下に２次元電子ガス１０が存在せず、ゲート電極８に正のバイアス電圧を印加することで、２次元電子ガス１０が生成する厚さに設定する必要がある。   In order to form a normally-off type nitride semiconductor device, the thickness of the electron transit layer 4 is such that the two-dimensional electron gas 10 does not exist immediately below the gate electrode 8 without applying a bias voltage to the gate electrode 8. It is necessary to set the thickness to be generated by the two-dimensional electron gas 10 by applying a positive bias voltage to 8.

キャップ層５は、厚さ５ｎｍ、ｐ型ＧａＮ層で構成する。ｐ型不純物としては、例えばマグネシウム（Ｍｇ）炭素（Ｃ）、ベリリウム（Ｂｅ）、亜鉛（Ｚｎ）、カドミウム（Ｃｄ）等を用いることができる。キャップ層５のホールキャリア濃度としては１×１０16〜５×１０19ｃｍ-3が、窒化物半導体装置の特性上望ましい。 The cap layer 5 is composed of a p-type GaN layer having a thickness of 5 nm. As the p-type impurity, for example, magnesium (Mg) carbon (C), beryllium (Be), zinc (Zn), cadmium (Cd), or the like can be used. The hole carrier concentration of the cap layer 5 is preferably 1 × 10 16 to 5 × 10 19 cm −3 in terms of the characteristics of the nitride semiconductor device.

ソース電極６およびドレイン電極７は、キャップ層５にオーミック接触し、ゲート電極８は、キャップ層５にショットキー接触する。なお、ソース電極６およびドレイン電極７は、図１のように、電極を形成する部分のキャップ層５および電子走行層４の一部もしくは全部をドライエッチングなどにより除去し、オーミックリセス構造とした後に、電極を形成することもできる。オーミックリセス構造とすることにより、キャリアとなる二次元電子ガス１０に対するコンタクト抵抗が低いオーミック接触を形成することが可能となる。   The source electrode 6 and the drain electrode 7 are in ohmic contact with the cap layer 5, and the gate electrode 8 is in Schottky contact with the cap layer 5. As shown in FIG. 1, the source electrode 6 and the drain electrode 7 are formed after removing part or all of the cap layer 5 and the electron transit layer 4 where the electrodes are to be formed by dry etching or the like to form an ohmic recess structure. Electrodes can also be formed. By adopting an ohmic recess structure, it is possible to form an ohmic contact having a low contact resistance with respect to the two-dimensional electron gas 10 serving as a carrier.

以上のように形成した本実施例の窒化物半導体装置の特性を、図５に示す従来の窒化物半導体装置の特性と比較した結果が、図２および図３となる。図２は、窒化物半導体装置の伝達特性を示している。本実施例の窒化物半導体装置では、電子供給層３と電子走行層４とのヘテロ接合近傍の二次元電子ガス１０が、ゲート電極８側に生じていること、および電子走行層４の薄膜化が可能であることから、ゲート電極８とチャネルとなる二次元電子ガス１０との距離が短くなる。この結果、ゲート電極８に制御電圧を印加しない状態でソース電極６とドレイン電極７間に電圧を印加しても、ゲート電極８直下に二次元電子ガス１０が存在しないため、ノーマリオフ型となっている。   2 and 3 show the results of comparing the characteristics of the nitride semiconductor device of this example formed as described above with the characteristics of the conventional nitride semiconductor device shown in FIG. FIG. 2 shows the transfer characteristics of the nitride semiconductor device. In the nitride semiconductor device of this example, the two-dimensional electron gas 10 near the heterojunction between the electron supply layer 3 and the electron transit layer 4 is generated on the gate electrode 8 side, and the electron transit layer 4 is thinned. Therefore, the distance between the gate electrode 8 and the two-dimensional electron gas 10 serving as a channel is shortened. As a result, even if a voltage is applied between the source electrode 6 and the drain electrode 7 without applying a control voltage to the gate electrode 8, the two-dimensional electron gas 10 does not exist immediately below the gate electrode 8. Yes.

次に、ゲートリーク電流特性を図３に示す。従来の窒化物半導体装置は、ゲート電極８に正のバイアス電圧を印加するとゲートリーク電流が増加するのに対して、本発明の窒化物半導体装置は、ゲートリーク電流が減少していることがわかる。これは、ｐ型の窒化物半導体層で構成したキャップ層５を導入することで、ゲート電極８とキャップ層５との間のショットキー障壁が増加することとなること、ｐ型窒化物半導体の多数キャリアは正孔であるため、ゲート電極に正のバイアス電圧を印加した場合、キャップ層５に対して逆バイアスとなることから、ゲートリーク電流を抑制することができることがわかる。   Next, the gate leakage current characteristic is shown in FIG. In the conventional nitride semiconductor device, the gate leakage current increases when a positive bias voltage is applied to the gate electrode 8, whereas in the nitride semiconductor device of the present invention, the gate leakage current decreases. . This is because the introduction of the cap layer 5 composed of a p-type nitride semiconductor layer increases the Schottky barrier between the gate electrode 8 and the cap layer 5. Since majority carriers are holes, when a positive bias voltage is applied to the gate electrode, it becomes a reverse bias with respect to the cap layer 5, and it can be seen that the gate leakage current can be suppressed.

次に第２の実施例について説明する。図４は、本発明の第２の実施例の窒化物半導体装置の断面図である。第１の実施例同様、ＭＯＣＶＤ法もしくはＭＢＥ法等により、バッファ層２を介して、第二の窒化物半導体からなる電子走行層、第一の窒化物半導体からなる電子供給層３および第二の窒化物半導体と同じ窒化物半導体であって、ｐ型不純物をドープした（第三の窒化物半導体に相当）キャップ層５が順に積層されている。キャップ層５上には、ソース電極６、ドレイン電極７およびゲート電極８が形成されている。   Next, a second embodiment will be described. FIG. 4 is a cross-sectional view of the nitride semiconductor device according to the second embodiment of the present invention. As in the first embodiment, the electron transit layer made of the second nitride semiconductor, the electron supply layer 3 made of the first nitride semiconductor and the second supply layer are formed via the buffer layer 2 by the MOCVD method or the MBE method. A cap layer 5 which is the same nitride semiconductor as the nitride semiconductor and is doped with a p-type impurity (corresponding to a third nitride semiconductor) is sequentially stacked. A source electrode 6, a drain electrode 7, and a gate electrode 8 are formed on the cap layer 5.

前述の第１の実施例と比較して、電子走行層４と電子供給層３の積層が逆となっている点が相違している。この場合も電子供給層３の厚さ、不純物濃度を適宜設定することで、ゲート電極８にバイアス電圧を印加しない状態で、ゲート電極８直下に２次元電子ガス１０が存在せず、ゲート電極８に正のバイアス電圧を印加することで、２次元電子ガス１０が生成する厚さと不純物濃度に設定する必要がある。   Compared to the first embodiment described above, the difference is that the stack of the electron transit layer 4 and the electron supply layer 3 is reversed. Also in this case, by appropriately setting the thickness and impurity concentration of the electron supply layer 3, the two-dimensional electron gas 10 does not exist immediately below the gate electrode 8 without applying a bias voltage to the gate electrode 8. It is necessary to set the thickness and impurity concentration to be generated by the two-dimensional electron gas 10 by applying a positive bias voltage.

このように構成しても、第１の実施例同様、ゲート電極８はｐ型キャップ層５上に形成されるため、ゲート電極８とキャップ層５との間のショットキー障壁が増加することとなること、ｐ型窒化物半導体の多数キャリアは正孔であるため、ゲート電極に正のバイアス電圧を印加した場合、キャップ層５に対して逆バイアスとなることから、ゲートリーク電流を抑制することができる。   Even in this configuration, the gate electrode 8 is formed on the p-type cap layer 5 as in the first embodiment, and therefore the Schottky barrier between the gate electrode 8 and the cap layer 5 is increased. Since the majority carrier of the p-type nitride semiconductor is a hole, when a positive bias voltage is applied to the gate electrode, it becomes a reverse bias with respect to the cap layer 5, thereby suppressing the gate leakage current. Can do.

１：基板、２：バッファ層、３：電子供給層（第一の窒化物半導体）、４：電子走行層（第二の窒化物半導体）、５：キャップ層（ｐ型不純物ドープ窒化物半導体）、６：ソース電極、７：ドレイン電極、８：ゲート電極、９：表面保護膜、１０：二次元電子ガス   1: substrate, 2: buffer layer, 3: electron supply layer (first nitride semiconductor), 4: electron transit layer (second nitride semiconductor), 5: cap layer (p-type impurity-doped nitride semiconductor) , 6: source electrode, 7: drain electrode, 8: gate electrode, 9: surface protective film, 10: two-dimensional electron gas

Claims (1)

基板上に、バッファ層を介して、ｎ型もしくはアンドープの第一の窒化物半導体からなる電子供給層と、前記電子供給層とヘテロ接合し、かつ該ヘテロ接合によって二次元電子ガスを形成する、前記電子供給層よりバンドギャップが小さいアンドープの第二の窒化物半導体からなる電子走行層とが積層し、前記電子走行層に電気的に接続するソース電極およびドレイン電極と、該ソース電極およびドレイン電極間の電流を制御するゲート電極を備えた窒化物半導体装置において、
前記電子供給層上に積層した前記電子走行層表面を、あるいは前記電子走行層上に積層した前記電子供給層表面を、ｐ型の第三の窒化物半導体からなるキャップ層で被覆し、該キャップ層に前記ゲート電極が接触していることを特徴とする窒化物半導体装置。 An electron supply layer made of an n-type or undoped first nitride semiconductor, a heterojunction with the electron supply layer, and a two-dimensional electron gas is formed by the heterojunction on the substrate via a buffer layer. A source electrode and a drain electrode that are laminated with an electron transit layer made of an undoped second nitride semiconductor having a smaller band gap than the electron supply layer, and are electrically connected to the electron transit layer; and the source electrode and the drain electrode In a nitride semiconductor device having a gate electrode for controlling the current between
The surface of the electron transit layer stacked on the electron supply layer or the surface of the electron supply layer laminated on the electron transit layer is covered with a cap layer made of a p-type third nitride semiconductor, and the cap A nitride semiconductor device, wherein the gate electrode is in contact with a layer.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715084A (en) * 2012-09-28 2014-04-09 富士通株式会社 Method of manufacturing a semiconductor device and semiconductor device
JP2014072426A (en) * 2012-09-28 2014-04-21 Fujitsu Ltd Semiconductor device and semiconductor device manufacturing method
US8907377B2 (en) 2012-07-17 2014-12-09 Samsung Electronics Co., Ltd. High electron mobility transistor and method of manufacturing the same
KR101473577B1 (en) 2012-09-28 2014-12-16 트랜스폼 재팬 가부시키가이샤 Semiconductor device and method for manufacturing a semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005244072A (en) * 2004-02-27 2005-09-08 Toshiba Corp Semiconductor device
JP2006269534A (en) * 2005-03-22 2006-10-05 Eudyna Devices Inc Semiconductor device and its manufacturing method, substrate for manufacturing semiconductor device and its manufacturing method, and substrate for semiconductor growth
JP2007109830A (en) * 2005-10-12 2007-04-26 Univ Nagoya Field effect transistor
JP2008010461A (en) * 2006-06-27 2008-01-17 Sharp Corp Hetero-junction field effect transistor, and manufacturing method of hetero-junction field effect transistor
JP2009231508A (en) * 2008-03-21 2009-10-08 Panasonic Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005244072A (en) * 2004-02-27 2005-09-08 Toshiba Corp Semiconductor device
JP2006269534A (en) * 2005-03-22 2006-10-05 Eudyna Devices Inc Semiconductor device and its manufacturing method, substrate for manufacturing semiconductor device and its manufacturing method, and substrate for semiconductor growth
JP2007109830A (en) * 2005-10-12 2007-04-26 Univ Nagoya Field effect transistor
JP2008010461A (en) * 2006-06-27 2008-01-17 Sharp Corp Hetero-junction field effect transistor, and manufacturing method of hetero-junction field effect transistor
JP2009231508A (en) * 2008-03-21 2009-10-08 Panasonic Corp Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8907377B2 (en) 2012-07-17 2014-12-09 Samsung Electronics Co., Ltd. High electron mobility transistor and method of manufacturing the same
CN103715084A (en) * 2012-09-28 2014-04-09 富士通株式会社 Method of manufacturing a semiconductor device and semiconductor device
JP2014072426A (en) * 2012-09-28 2014-04-21 Fujitsu Ltd Semiconductor device and semiconductor device manufacturing method
KR101465889B1 (en) * 2012-09-28 2014-11-26 트랜스폼 재팬 가부시키가이샤 Semiconductor device and manufacturing method of semiconductor device
KR101473577B1 (en) 2012-09-28 2014-12-16 트랜스폼 재팬 가부시키가이샤 Semiconductor device and method for manufacturing a semiconductor device
KR101514140B1 (en) 2012-09-28 2015-04-21 트랜스폼 재팬 가부시키가이샤 Method of manufacturing a semiconductor device and semiconductor device

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