JP2009071061A - Semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus in which normally-off operation can be obtained. <P>SOLUTION: The semiconductor apparatus includes a first nitride semiconductor layer, a second nitride semiconductor layer which is provided on the first nitride semiconductor layer and has a larger band gap than the first nitride semiconductor layer, a source electrode provided on the second nitride semiconductor layer, a drain electrode provided on the second nitride semiconductor layer, an insulating layer provided between the source electrode and the drain electrode on the surface of the second nitride semiconductor layer, a p-type third nitride semiconductor layer provided on the insulating layer, and a gate electrode provided on the third nitride semiconductor layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an insulated gate semiconductor device using a nitride semiconductor.

  Gallium nitride (GaN) -based semiconductors have a high energy band gap of 3 eV or more, and are being developed mainly for application to light devices such as blue (LEDs) and short-wavelength LEDs (Light Emitting Diodes) and LDs (Laser Diodes). I came. However, in recent years, LEDs and LDs have shifted to the commercialization phase, and the focus of research and development is shifting to electronic devices for power electronics applications that take advantage of the high breakdown voltage.

  One such electronic device is a field effect transistor (FET) using a heterojunction. In general, a heterojunction in which an AlGaN layer is an electron supply layer (barrier layer) and a GaN layer is a channel layer is often used. Such a structure is called a high electron mobility transistor (HEMT) or a heterojunction field effect transistor (HFET) and is used in a region requiring high frequency operation and high breakdown voltage. It is done.

  One problem with such a GaN-based FET structure is that it is difficult to produce a normally-off type device. Further, if it is produced simply for the purpose of being normally-off type, it is contrary to the reduction in resistance (on-resistance) during energization, which is a feature of this material system. That is, in order to make a normally-off type device, it cannot be realized without suppressing carriers, but this increases the on-resistance of the device.

  Therefore, normally-off operation must be realized without impairing the low on-resistance. For that purpose, it is necessary to cut off the current only at the controllable gate portion, and to ensure low resistance in the other source-gate channel and the gate-drain channel.

There is a technique for achieving a normally-off by substantially reducing the thickness of a barrier layer under a gate by re-growing a contact layer in a source region and a drain region (for example, Patent Document 1). In addition, there is a technique for achieving normally-off by injecting p-type carriers under the gate (for example, Patent Document 2).
JP 2006-228891 A JP 2006-339561 A

  The present invention provides a semiconductor device capable of realizing a normally-off operation.

  According to one aspect of the present invention, a first nitride semiconductor layer and a second nitride provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer. An oxide semiconductor layer, a source electrode provided on the second nitride semiconductor layer, a drain electrode provided on the second nitride semiconductor layer, and a second nitride semiconductor layer An insulating layer provided between the source electrode and the drain electrode on the surface, a p-type third nitride semiconductor layer provided on the insulating layer, and the third nitride semiconductor layer And a gate electrode provided on the semiconductor device.

  According to the present invention, a semiconductor device capable of realizing a normally-off operation is provided.

  When the contact layer is regrowth in the source region and the drain region and the barrier layer thickness under the gate is substantially reduced to achieve normally-off, a regrowth step is included. It must be taken out of the furnace, and there is a possibility that characteristic deterioration will occur due to oxidation of the regrowth interface. In addition, after providing the barrier layer with a thickness sufficient to obtain the necessary low resistance, when the recess gate structure is intended to be removed normally by etching away only the portion under the gate, problems of etching controllability, There is a problem that the surface of the electron supply layer is damaged during etching.

In addition, when normally-off is achieved by injecting p-type carriers (holes) under the gate, carriers (holes) having a conductivity type opposite to that of the two-dimensional electron gas are injected into the channel layer. As a result, there is a concern that the overall mobility decreases and the resistance increases.
Alternatively, by turning on the gate, reverse injection of carriers (electrons) into the p-type layer occurs. In particular, when there is an insulating layer between the p-type layer and the gate electrode, carriers accumulate in the p-type layer. There is also concern that the breakdown voltage will decrease.

  As a result of the simulation conducted by the present inventors, a p-type layer is provided under the gate electrode in a HEMT having a heterojunction structure of an AlGaN layer (barrier layer) and a GaN layer (channel layer). It was confirmed that the two-dimensional electron gas region was not depleted only by raising the energy of the conduction band. This is because the formation of the two-dimensional electron gas by the GaN-based material is not only due to impurities such as FETs composed of other material systems such as Si and GaAs, but also in the electron supply layer (AlGaN layer) This is because there is an influence of carriers generated by polarization.

  One cause of polarization in the AlGaN layer is distortion of the AlGaN layer due to a difference in lattice constant between the AlGaN layer as a barrier layer and the GaN layer as a channel layer. In order to cancel the strain due to the difference in lattice constant, it is conceivable to form the same GaN layer (strain canceling layer) as the channel layer on the electron supply layer (AlGaN layer), but the GaN layer on the AlGaN layer is If the layer thickness is not the same as that of the channel layer, the strain of the AlGaN layer is not canceled out. A GaN layer formed as a channel layer generally has a thickness of several μm. However, providing a GaN layer having a thickness similar to this thickness on the gate electrode portion can cause a large voltage when the gate is turned ON / OFF. Is unrealistic. Further, the amount of carriers generated by the polarization of the AlGaN layer itself is not offset by the effect of the strain canceling layer, and in the case of a gate insulation type structure, carriers generated by strain applied from the insulating layer to the AlGaN layer Minutes are not offset.

  Therefore, in the embodiment of the present invention, by providing a p-type nitride semiconductor layer under the gate electrode, the energy of the conduction band is raised only under the gate electrode, and the p-type nitride semiconductor layer becomes a gate in the electron supply layer. A strain that cancels polarization (charge) generated in the lower portion of the electrode is applied to the electron supply layer.

  However, when the p-type nitride semiconductor layer is provided simply in contact with the electron supply layer, holes are injected from the p-type nitride semiconductor layer into the channel layer, particularly in power electronics applications where a high voltage is applied, and the on-resistance increases. There is a concern that operation instability, a decrease in operating frequency, and the like may occur. There is also concern about reverse injection of carriers when the gate is turned on. In order to suppress these, it is necessary to electrically insulate and separate the p-type nitride semiconductor layer and the channel layer.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. In the present embodiment, a GaN HEMT (High Electron Mobility Transistor) will be described as an example of a semiconductor device.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

  A heterojunction between a channel layer 3 as a first nitride semiconductor layer and an electron supply layer (barrier layer) 4 as a second nitride semiconductor layer on the main surface of the substrate 1 via a buffer layer 2 A structure is provided. As the substrate 1 and the buffer layer 2, a material suitable for epitaxial growth of a GaN-based nitride semiconductor is used. The channel layer 3 is, for example, an undoped (intentionally doped impurity) GaN layer. The electron supply layer 4 is, for example, an undoped or n-type AlGaN layer having a band gap larger than that of the channel layer 3.

  On the surface of the electron supply layer 4, the source electrode 7 and the drain electrode 8 are provided so as to be separated from each other. The source electrode 7 and the drain electrode 8 are in ohmic contact with the surface of the electron supply layer 4.

  An insulating layer 5 is provided on the surface of the electron supply layer 4 between the source electrode 7 and the drain electrode 8. The insulating layer 5 is an AlN layer, for example. On the insulating layer 5, a p-type nitride semiconductor layer 6 is provided as a third nitride semiconductor layer. The p-type nitride semiconductor layer 6 is, for example, a p-type GaN layer. A gate electrode 9 is provided on the p-type nitride semiconductor layer 6.

  In these heterojunction structures using a GaN layer as the channel layer 3 and an AlGaN layer as the electron supply layer 4, the AlGaN layer has a smaller lattice constant than the GaN layer, so that the AlGaN layer is distorted. The AlGaN layer is also strained by the insulating layer 5. Due to the polarization caused by these strains and the polarization of the AlGaN layer itself, a two-dimensional electron gas is accumulated in the vicinity of the interface of the GaN layer with the AlGaN layer. By controlling the gate voltage applied to the gate electrode 9, the two-dimensional electron gas concentration at the heterojunction interface between the electron supply layer 4 and the channel layer 3 thereunder increases or decreases and flows between the source electrode 7 and the drain electrode 8. The main current can be controlled.

  In this embodiment, since the p-type nitride semiconductor layer 6 is provided under the gate electrode 9, the energy of the conduction band under the gate electrode 9 is raised, and the two-dimensional structure under the gate electrode 9 when the gate voltage is 0V. Electron gas can be suppressed.

  Further, by using a p-type GaN layer as the p-type nitride semiconductor layer 6, this p-type GaN layer supplies an electron with a strain that cancels polarization (charge) generated in a portion under the gate electrode 9 in the electron supply layer 4. It is possible to suppress the two-dimensional electron gas that is applied to the layer 4 and is thereby induced by the strain generated in the electron supply layer 4.

  By these synergistic effects, it is possible to eliminate the two-dimensional electron gas under the gate electrode 9 when the gate voltage is 0 V, and realize a normally-off in which no current flows between the drain electrode 8 and the source electrode 7. Moreover, since the insulating layer 5 is provided between the p-type nitride semiconductor layer 6 and the electron supply layer 4, no injection of holes from the p-type nitride semiconductor layer 6 to the channel layer 3 occurs. It is possible to prevent an increase in on-resistance due to a decrease in mobility in the channel, an unstable operation, and a decrease in operating frequency.

  Since the insulating layer 5 and the p-type nitride semiconductor layer 6 are not provided under the source electrode 7 and the drain electrode 8, the electron supply layer 4 and the channel layer between the source electrode 7 and the gate electrode 9 are provided. 3, and the interface between the electron supply layer 4 and the channel layer 3 between the gate electrode 9 and the drain electrode 8, two-dimensional electron gas accumulates, and does not increase the on-resistance.

  As described above, the p-type nitride semiconductor layer 6 gives strain to the electron supply layer 4 to cancel polarization (charge) generated in a portion of the electron supply layer 4 below the gate electrode 9, and is generated in the electron supply layer 4. Suppresses the two-dimensional electron gas induced by strain. In order to reliably obtain this effect, it is desirable that the thickness of the p-type nitride semiconductor layer 6 be equal to or greater than the sum of the thickness of the insulating layer 5 and the thickness of the electron supply layer 4. Further, since the p-type nitride semiconductor layer 6 is provided under the gate electrode 9, there is a concern that if the p-type nitride semiconductor layer 6 becomes too thick, the controllability of the two-dimensional electron gas by the gate voltage is impaired. From this viewpoint, it is desirable that the p-type nitride semiconductor layer 6 has a thickness of 200 nm or less.

  The thickness of the channel layer 3 is 3 to 5 μm. Further, as a result of examination by the present inventors, it has been found that even if the sum of the thickness of the insulating layer 5 and the thickness of the electron supply layer 4 is larger than 60 nm, no further increase in two-dimensional electron gas can be expected. . Therefore, the sum of the thickness of the insulating layer 5 and the thickness of the electron supply layer 4 is desirably 60 nm or less. Among them, the thickness of the electron supply layer 4 is 20 to 30 nm.

  Next, with reference to FIG. 2, the manufacturing method of the semiconductor device which concerns on embodiment of this invention is demonstrated.

  First, a buffer layer 2, a channel layer 3, an electron are formed on the main surface of the substrate 1 by a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. The supply layer 4, the insulating layer 5, and the p-type nitride semiconductor layer 6 are sequentially formed to obtain a stacked structure shown in FIG.

  Next, as shown in FIG. 2B, the p-type nitride semiconductor layer 6 is selectively removed by photolithography and vapor phase etching. The dimensions of the p-type nitride semiconductor layer 6 left on the insulating layer 5 determine the gate length and gate width.

  Next, as shown in FIG. 2C, the insulating layer 5 in the portion where the source electrode and the drain electrode are formed is selectively removed by photolithography and vapor phase etching. A wet etching method can be used depending on the material of the insulating layer 5.

  Next, as shown in FIG. 1, a source electrode 7 and a drain electrode 8 are formed on the surface of the electron supply layer 4 exposed by removing the insulating layer 5, and a gate is formed on the p-type nitride semiconductor layer 6. Electrode 9 is formed. Thereafter, a final product can be obtained through a passivation film forming process and a wiring process for protecting the surface.

  When a heterojunction structure of an AlGaN layer as the electron supply layer 4 and a GaN layer as the channel layer 3 is used, if an AlN layer is used as the insulating layer 5, a growth reactor is formed in the epitaxial growth step of FIG. Therefore, oxidation of the surface of the electron supply layer (AlGaN layer) 4 immediately below the gate can be suppressed, and a drain current reduction phenomenon (current collapse) can be suppressed.

In addition, as the insulating layer 5, an Al ₂ O ₃ layer can be used. When an Al ₂ O ₃ layer is used as the insulating layer 5, the crystal structure is close to that of GaN. Therefore, it is possible to grow a p-type GaN layer as the p-type nitride semiconductor layer 6 formed thereon with high quality. is there. Further, since Al ₂ O ₃ is an oxide, the oxide can be taken in after being taken out from the growth furnace, and surface degradation can be suppressed.

  It is also possible to use a SiN layer as the insulating layer 5. In this case, since it can be easily formed at a low temperature and wet etching is possible, there is an advantage that the process can be easily performed.

When a GaN layer is used as the channel layer 3, an AlGaN layer is used as the electron supply layer 4, and an AlN layer is used as the insulating layer 5, if a p-type GaN layer is used as the p-type nitride semiconductor layer 6, the formation of these stacked structures is the same. It can be done easily in the growth furnace. As a p-type impurity to be introduced into the GaN-based semiconductor, magnesium (Mg) is generally used. In order to obtain the above-described effect by the p-type nitride semiconductor layer 6, for example, a carrier concentration of 1 × 10 ¹⁷ / cm ³ or more is required. If there is enough.

  As the p-type nitride semiconductor layer 6, a p-type InGaN layer can also be used. When a p-type InGaN layer is used as the p-type nitride semiconductor layer 6, the activation rate of p-type carriers (holes) can be increased. Further, the p-type InGaN layer has a higher effect of canceling polarization (charge) generated in the electron supply layer (AlGaN layer) 4 than the p-type GaN layer. In addition, since the InGaN layer grows at a low temperature in a nitrogen atmosphere, it is possible to suppress a thermal adverse effect on the device.

  As the p-type nitride semiconductor layer 6, not only a single layer but also a laminated structure can be used. In particular, when an AlN layer is used as the insulating layer 5 under the p-type nitride semiconductor layer 6, the AlN / InGaN junction has an optimum growth temperature, so that the buffer layer is between the AlN layer and the InGaN layer. For example, the quality of the grown crystal can be improved by inserting a GaN layer of about several nm.

When a p-type InGaN layer is used as the p-type nitride semiconductor layer 6, the channel layer 3 is not limited to a GaN layer, and an InGaN layer having a lower In composition ratio than the p-type InGaN layer is used as the channel layer 3. It is also possible to use it. This can be explained by considering the magnitude relationship of strain applied to the electron supply layer 4 by the channel layer 3 and the p-type nitride semiconductor layer 6 (p-type InGaN layer).
In other words, this is because the strain effect with the larger In composition ratio of the p-type nitride semiconductor layer 6 and the channel layer 3 wins.

  In addition, as the p-type nitride semiconductor layer 6, diamond or polycrystalline silicon can be used. Diamond is likely to be p-type without being doped with impurities, and since the band gap energy is large, the degree of conduction band lift is large and carrier accumulation can be suppressed more efficiently. Further, since polycrystalline silicon can be easily formed, there is a process advantage.

1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the same semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Buffer layer, 3 ... 1st nitride semiconductor layer (channel layer), 4 ... 2nd nitride semiconductor layer (electron supply layer), 5 ... Insulating layer, 6 ... p-type nitride semiconductor Layer, 7 ... Source electrode, 8 ... Drain electrode, 9 ... Gate electrode

Claims (5)

A first nitride semiconductor layer;
A second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer;
A source electrode provided on the second nitride semiconductor layer;
A drain electrode provided on the second nitride semiconductor layer;
An insulating layer provided between the source electrode and the drain electrode on the surface of the second nitride semiconductor layer;
A p-type third nitride semiconductor layer provided on the insulating layer;
A gate electrode provided on the third nitride semiconductor layer;
A semiconductor device comprising:   The third nitride semiconductor layer imparts strain to the second nitride semiconductor layer to cancel polarization generated in a portion under the gate electrode in the second nitride semiconductor layer. 1. The semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the third nitride semiconductor layer includes a p-type GaN layer or a p-type InGaN layer.   The semiconductor device according to claim 1, wherein the insulating layer includes an AlN layer.   5. The thickness of the third nitride semiconductor layer is equal to or greater than a sum of a thickness of the insulating layer and a thickness of the second nitride semiconductor layer. A semiconductor device according to 1.

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