JP2010258313A - Field-effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor having a high carrier concentration, a high mobility and a low resistance, and a manufacturing method thereof. <P>SOLUTION: The present invention relates to a field-effect transistor comprising a first nitride semiconductor layer 11, a second nitride semiconductor layer 12 including an Al-contained nitride semiconductor layer, and a gate contact layer 14. A third nitride semiconductor layer 13 is provided in a part on the second nitride semiconductor layer 12, and the gate contact layer 14 is provided on the third nitride semiconductor layer 13. In the second nitride semiconductor layer 12, a side of the first nitride semiconductor layer 11 is Al<SB>a</SB>Ga<SB>1-a</SB>N (0<a≤1) and a side of the third nitride semiconductor layer 13 is Al<SB>b</SB>Ga<SB>1-b</SB>N (0≤b<1, b<a) or InGaN. The third nitride semiconductor layer 13 is comprised of an Al contained nitride semiconductor of which the Al composition ratio is greater than that at the side of the third nitride semiconductor layer 13 in the second nitride semiconductor layer 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a field effect transistor, and more particularly to a normally-off type field effect transistor using a nitride semiconductor.

  A semiconductor device using GaN is a wide gap semiconductor and has a high saturation electron velocity. For this reason, compared with the conventional Si-type and GaAs-type elements, high-temperature operation, high-output operation, and high-speed operation are possible, and application in the millimeter wave and power electronics fields is expected. In particular, since the on-resistance can be reduced by two orders of magnitude or more compared to Si-based devices, the loss of switching devices such as inverters and converters can be greatly reduced. Such a GaN-based field effect transistor (FET) is normally a normally-on type in which a current flows between the source electrode and the drain electrode when no voltage is applied to the gate electrode. In order to ensure this, it is necessary to provide a separate protection circuit. On the other hand, in the normally-off type, no current flows between the source electrode and the drain electrode when no gate voltage is applied, which is desirable from the viewpoint of safety and does not require a protection circuit.

  In order to obtain a normally-off type FET, several methods have been proposed. For example, a structure in which a p-type layer or an InGaN layer is provided under a gate electrode has been proposed (see Patent Documents 1 to 6). For example, in the case of a structure in which a p-type GaN layer is provided under the gate electrode in an AlGaN / GaN heterostructure, the threshold voltage can be raised to the maximum pn internal potential (approximately 3 V). The threshold voltage value can be adjusted by adjusting the composition ratio and film thickness of the AlGaN layer that is the barrier layer.

  A structure for changing the Al composition ratio of the AlGaN layer has been proposed (see Patent Documents 7 and 8). In particular, when an intervening layer such as a p-type layer is provided under the gate electrode, a layer having a large Al composition ratio is used. A structure has been proposed in which an etching stop layer is provided (see Patent Document 9).

JP-A-11-261053 JP 2003-209124 A JP2002-16087 JP-A-2005-244072 JP2007-109830 JP2008-91394 JP 2000-252458 A JP2003-151996 JP2007-201279

  In a conventional FET in which an intervening layer such as a p-type GaN layer is provided under the gate electrode, the threshold voltage increases when the internal barrier of the AlGaN layer is reduced, that is, when the composition ratio or the film thickness is reduced. For this reason, the portion other than the gate electrode portion from which the p-type GaN layer has been removed has a high resistance due to a decrease in carrier concentration. Thus, there is a trade-off relationship between the threshold voltage and the resistance, and there is a problem that when the threshold voltage is increased to 2 V or more, which is easy to handle in power applications, the resistance increases rapidly.

  Further, in order to remove the p-type GaN layer other than under the gate electrode, for example, selective etching is performed using an AlGaN layer having a large Al composition ratio as an etching stop layer, but it is considered that etching damage is accumulated in the etching stop layer. After the selective etching, the carrier gas and mobility are improved by changing the etching gas and removing the surface of the AlGaN layer used as the etching stop layer.

  However, as shown in FIG. 7, when the thickness of the AlGaN layer is reduced, the interface state concentration is reduced accordingly, and the carrier concentration is also reduced. FIG. 7 is a diagram showing changes in the band diagram and the carrier concentration Ns with respect to the film thickness l of the AlGaN layer. If the AlGaN layer is a single layer with a constant Al composition ratio, assuming that the interface state distribution does not change before and after etching, the deeper the etching, the higher the positively charged interface state with higher energy than the Fermi level. Will decrease. Along with this, the carrier concentration of the GaN layer, which is a compensation charge, also decreases, causing a decrease in mobility and an increase in resistance.

The field effect transistor of the present invention includes a first nitride semiconductor layer and an Al-containing nitride semiconductor that is provided on the first nitride semiconductor layer and has a larger band gap energy than the first nitride semiconductor layer. A field effect transistor comprising a second nitride semiconductor layer and a gate contact layer provided on the second nitride semiconductor layer, wherein a part of the second nitride semiconductor layer includes Al A third nitride semiconductor layer made of a contained nitride semiconductor is provided; a gate contact layer is provided on the third nitride semiconductor layer; a gate electrode is provided on a surface of the gate contact layer; A source electrode and a drain electrode are provided across a contact layer and the third nitride semiconductor layer, and the second nitride semiconductor layer has an Al side on the first nitride semiconductor layer side. _a Ga _1-a N (0 <a ≦ 1), the third nitride semiconductor layer side is Al _b Ga _1-b N (0 ≦ b <1, b <a) or InGaN, and the third nitride The semiconductor layer is made of an Al-containing nitride semiconductor having an Al composition ratio larger than that of the second nitride semiconductor layer on the third nitride semiconductor layer side.

The following structures can be combined with the field effect transistor of the present invention.
The second nitride semiconductor layer includes a first layer made of Al _a Ga _1-a N (0 <a ≦ 1) provided on the first nitride semiconductor layer side, and the third nitride semiconductor layer side And a second layer made of InGaN and Al _b Ga _1-b N (0 ≦ b <1, b <a).
The second nitride semiconductor layer is composed of a composition gradient layer in which the Al composition ratio decreases as the distance from the first nitride semiconductor layer side increases.
The second nitride semiconductor layer is the third nitride semiconductor layer side is _{Al b Ga 1-b N (} 0 <b <1, b <a), the third nitride semiconductor layer is _Al c _{Ga 1- cN} (0 <c ≦ 1, c> b).
The source electrode and the drain electrode are provided in the third nitride semiconductor layer, and the third nitride semiconductor layer has a film thickness in a region where the source electrode and the drain electrode are provided. The thickness can be made smaller than the thickness of the region where the gate electrode is provided.
The source electrode and the drain electrode may be provided in the second semiconductor layer.
Furthermore, the fourth nitride semiconductor layer is made of Al _c Ga _1-c N (0 <c ≦ 1, b <c <a). The gate contact layer is InGaN or GaN.

The field effect transistor manufacturing method of the present invention includes a first nitride semiconductor layer, a second nitride semiconductor layer including an Al-containing nitride semiconductor having a band gap energy larger than that of the first nitride semiconductor layer, and a gate contact. A semiconductor layer stacking step of sequentially stacking layers, and a semiconductor layer removing step of removing the gate contact layer leaving a gate electrode formation region, wherein a gate electrode is formed on the gate contact layer, and the gate A method of manufacturing a field effect transistor in which a source electrode and a drain electrode are formed with a contact layer interposed therebetween, wherein in the semiconductor layer stacking step, the first nitride semiconductor layer side is Al _a as the second nitride semiconductor layer. Ga _1-a N (0 <a ≦ 1), and the side facing the first nitride semiconductor layer is Al _b Ga _1-b N (0 ≦ b <1, b < a) or a nitride semiconductor layer of InGaN is formed, and the Al composition ratio is higher on the second nitride semiconductor layer than on the side of the second nitride semiconductor layer facing the first nitride semiconductor layer. Forming a third nitride semiconductor layer made of a large Al-containing nitride semiconductor, and in the semiconductor layer removing step, after removing the gate contact layer by first etching using the third nitride semiconductor layer as an etching stop layer; The third nitride semiconductor layer is removed by a second etching different from the first etching, and the damaged layer by the first etching is removed.

The second etching is performed at a lower output than the first etching. At least a part of the third nitride semiconductor layer is removed by the second etching.
The second nitride semiconductor layer includes a first layer made of Al _a Ga _1-a N (0 <a ≦ 1) provided on the first nitride semiconductor layer side, and the third nitride semiconductor layer side And a second layer made of Al _b Ga _1-b N (0 ≦ b <1, b <a) or InGaN, and at least a part of the second layer is formed by the second etching. It may be removed.

  According to the FET of the present invention, a transistor with high carrier concentration, high mobility, and low resistance can be realized. In addition, an FET having a desired carrier concentration can be manufactured with high accuracy.

FIG. 1 is a schematic cross-sectional view showing an FET according to an embodiment. FIG. 2 is a schematic cross-sectional view for explaining a method of manufacturing the FET shown in FIG. FIG. 3 is a diagram showing a band diagram and a change in carrier concentration with respect to the film thicknesses of the second nitride semiconductor layer and the third nitride semiconductor layer in the FET shown in FIG. FIG. 4 is a schematic cross-sectional view showing the HEMT of Example 1. FIG. 5 is a graph showing the relationship between RIE processing time, mobility, and carrier concentration in the HEMT of Reference Example 1. FIG. 6 is a graph showing the relationship between the RIE processing time, mobility, and carrier concentration in the HEMT of Example 2. FIG. 7 is a diagram showing a band diagram and a carrier concentration change with respect to the AlGaN layer thickness in the prior art.

  FIG. 1 shows an example in which a high electron mobility transistor (HEMT) is configured as an FET according to an embodiment of the present invention. The HEMT 10 shown in this figure includes a first nitride semiconductor layer 11, a second nitride semiconductor layer 12, a third nitride semiconductor layer 13, and a gate contact layer formed in this order on a substrate 18. 14, a source electrode 15 and a drain electrode 16 formed on the surface of the second nitride semiconductor layer 12, and a gate electrode 17 formed on the surface of the gate contact layer 14. In the HEMT 10 having this structure, a channel is formed in the first nitride semiconductor layer 11 in the vicinity of the interface between the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12, and carriers such as electrons move highly in this channel. You can run at a degree. The second nitride semiconductor layer 12 includes a first layer 101 and a second layer 102.

(First Nitride Semiconductor Layer 11)
The first nitride semiconductor layer 11 is preferably an undoped layer. Note that undoped in this specification refers to a material in which impurities are not intentionally added during formation. In the example of FIG. 1, an undoped GaN layer is used as the first nitride semiconductor layer 11, and an undoped Al _a Ga _1-a N layer (0 <a ≦ 1) is used as the first layer 101. The FET in this example is a HEMT of a unipolar element that uses electrons as carriers. However, when holes are used as carriers, the impurities and conductivity types of each layer are reversed.

(Second nitride semiconductor layer 12)
The second nitride semiconductor layer 12 crystal-grown on the first nitride semiconductor layer 11 is an Al-containing nitride semiconductor having a band gap energy larger than that of the first nitride semiconductor layer 11 on the first nitride semiconductor layer 11 side. Consists of. The second nitride semiconductor layer 12 is preferably an undoped layer. Further, a p-type impurity can be doped to such an extent that nitrogen depletion of the nitride semiconductor can be compensated.

The second nitride semiconductor layer 12 is made of Al _a Ga _1-a N (0 <a ≦ 1) on the first nitride semiconductor layer 11 side, and Al _b Ga _1-b N on the third nitride semiconductor layer 13 side. (0 ≦ b <1, b <a) or InGaN. In the example of FIG. 1, the first nitride semiconductor layer 12 includes a first layer 101 made of Al _a Ga _1-a N (0 <a ≦ 1) and Al _b Ga ₁ from the first nitride semiconductor layer 11 side. _−b N (0 ≦ b <1, b <a) or the second layer 102 made of InGaN.

The first layer 101 is made of Al _a Ga _1-a N (0 <a ≦ 1), and is preferably Al _a Ga _1-a N (0 <a <1) in order to form a thick film. In this case, the carrier mobility in the channel is improved by providing an AlN layer having a larger band gap energy between the Al _a Ga _1-a N layer and the GaN layer that is the first nitride semiconductor layer 11. Can do. Since it is difficult to form the AlN layer as a thick film with good crystallinity, the AlN layer is made thinner than the second nitride semiconductor layer 12. If the AlN layer has a thickness of 2 nm or less, it can be formed with good crystallinity, and it is particularly preferable that the thickness be about 0.5 to 1 nm. The first layer 101 is preferably Al _a Ga _1-a N (0 <a <0.4). If the Al composition ratio a is less than 0.4, an AlGaN layer with good crystallinity can be formed, and the mobility can be increased. The Al composition ratio a is particularly preferably 0.1 or more.

  Further, the mobility increases as the film thickness of the first layer 101 increases, and starts to saturate when reaching a specific film thickness. For example, when the Al composition ratio a is 0.3, saturation starts from around 7 nm. On the other hand, the carrier concentration when the threshold voltage is constant decreases as the film thickness increases. Accordingly, the sheet resistance is minimized at a film thickness at which the mobility starts to be saturated under a constant threshold voltage, and the first layer 101 is preferably set to such a film thickness from the viewpoint of reducing resistance.

The second layer 102 is made of Al _b Ga _1-b N (0 ≦ b <1, b <a) or InGaN. In the example of FIG. 1, the second layer 102 has a film thickness under the gate contact layer 14 larger than the other film thicknesses. As will be described later, in order to increase the interface state, it is ideal not to provide the second layer 102 in a region other than under the gate electrode 17, but it is difficult in terms of etching accuracy. A structure in which a part of the second layer 102 in the depth direction is removed as shown in FIG. Alternatively, the structure may be such that the second layer 102 except under the gate electrode 17 is completely removed, and a part of the first layer 101 in the depth direction is removed.

The second layer 102 needs to be as thin as possible or reduce the Al composition ratio so as to suppress a decrease in threshold voltage. The second layer is preferably thick enough to protect the first layer from etching damage, slightly thicker than the etching damage penetration depth, and the Al composition ratio is lowered so as not to lower the threshold voltage. Therefore, the Al composition ratio b is made smaller than the Al composition ratio a of the first layer 101 and the Al composition ratio c of the third nitride semiconductor layer 13. In addition, since the third nitride semiconductor layer 13 having a large Al composition ratio is provided on the second layer 102 and the second layer 102 does not need to function as an etching stop layer, the Al composition ratio of the second layer 102 Can be reduced. To suppress a decrease in the carrier concentration, the second layer 102 is preferably made of _{Al b Ga 1-b N (} 0 <b <1, b <a). The second layer 102 is preferably AlGaN because the third nitride semiconductor layer 13 stacked thereon is an Al-containing layer.

  On the other hand, the second layer 102 may be composed of GaN or InGaN. Since polarization of GaN or InGaN is weaker than that of AlGaN, the threshold voltage drop when the Al composition ratio of the first layer is increased can be suppressed, and the Al composition ratio of the first layer is increased while maintaining the threshold voltage. Thus, the carrier concentration can be increased. Since the contact layer of the source electrode 15 and the drain electrode 16 is preferably an Al-containing nitride semiconductor layer, when the second layer 102 is made of GaN or InGaN, which is a nitride semiconductor not containing Al, the source electrode 15 and the drain electrode The film thickness of the second layer 102 under 16 is preferably smaller than the film thickness of the second layer 102 under the gate electrode 17. More preferably, the second layer under the source and drain electrodes is completely removed, and the source and drain electrodes are provided on the surface of the first layer.

  In the example of FIG. 1, two layers of the first layer 101 and the second layer 102 are provided as the second nitride semiconductor layer 12. The second nitride semiconductor layer 12 may be a laminated or single layer of a plurality of layers whose Al composition ratio increases as it approaches the first nitride semiconductor layer 11. At this time, the configuration of the first layer 101 described above can be adopted as the first nitride semiconductor layer 11 side, and the configuration of the second layer 102 can be adopted as the third nitride semiconductor layer 13 side. By configuring with two layers as in the example of FIG. 1, the charge is likely to increase when the second layer 102 is partially removed. In the case of two layers, since the carrier concentration is maximized at the interface between the two layers as described later, the amount of the second nitride semiconductor layer to be removed can be easily designed according to the maximum carrier position.

(Third nitride semiconductor layer 13)
The third nitride semiconductor layer 13 is made of Al _c Ga _1-c N (0 <c ≦ 1, c> b). The third nitride semiconductor layer 13 is preferably selected from a material that functions as an etching stop layer for accurately controlling the thickness of the semiconductor multilayer structure. The nitride semiconductor layer containing Al has a lower etching rate than a nitride semiconductor layer having another composition or a nitride semiconductor layer having a smaller Al composition ratio, that is, the higher the Al composition ratio, the higher the etching rate. Get smaller. Utilizing this property, a nitride semiconductor layer (Al high mixed crystal layer) containing Al such as AlGaN, AlN, etc., a nitride semiconductor layer having a smaller Al composition ratio, or a nitride semiconductor layer containing no Al The nitride semiconductor layer containing Al (Al high mixed crystal layer) can function as an etching stop layer. Further, a nitride semiconductor layer containing Al (Al high mixed crystal layer) is disposed on a nitride semiconductor layer having a smaller Al mixed crystal ratio or another nitride semiconductor layer having a smaller Al mixed crystal ratio. Thus, it can function as a layer that suppresses adverse effects on etching during etching.

  The third nitride semiconductor layer 13 having a large Al composition ratio has a strong polarization and has an effect of reducing the threshold voltage. Therefore, the third nitride semiconductor layer 13 needs to be thin. However, the third nitride semiconductor layer 13 is not completely removed in the step of removing the gate contact layer 14 and is slightly removed. It is preferable to secure the film thickness to the extent that it remains, that is, the film thickness that acts as an etching stop layer. Specifically, the film thickness is 0.5 nm or more and 2 nm or less. Since the second nitride semiconductor layer on the third nitride semiconductor layer 13 side has a small Al composition ratio or does not contain Al, even if the film thickness of the third nitride semiconductor layer 13 is small, the second nitride semiconductor layer 12 is moved to the second nitride semiconductor layer 12. The influence of etching can be suppressed.

  The film thickness and composition ratio of the second nitride semiconductor layer 12 and the third nitride semiconductor layer 13 can be set so as to obtain a desired threshold voltage. Specifically, a flat band is obtained by applying a gate bias from the internal potential of the layer having a set threshold voltage between the first nitride semiconductor layer 11 serving as the carrier traveling layer and the gate electrode 17 in a thermal equilibrium state. The film thickness and the composition ratio are designed so as to correspond to a value obtained by subtracting the internal potential at that time. For example, when the gate contact layer includes a p-type layer, the value obtained by subtracting the set threshold voltage from the pn junction internal potential is a flat band of a layer between the first nitride semiconductor layer 11 and the p-type layer. Design to correspond to the internal potential. For example, if the set threshold voltage is 2 V, a flat band of a layer in which 1 V obtained by subtracting 2 V of the set threshold voltage from 3 V of the pn junction internal potential is between the first nitride semiconductor layer 11 and the p-type layer. It corresponds to the internal potential of the hour.

(Gate contact layer 14)
The gate contact layer 14 is provided between the gate electrode 17 and the third nitride semiconductor layer 13. The gate contact layer 14 may be a single layer or a plurality of layers made of In _x Ga _1-x N (0 ≦ x <1), thereby increasing the threshold voltage of the FET. If the gate contact layer 14 is present in a region other than the region where the gate electrode 17 is formed, it affects the carrier concentration and deteriorates the resistance. Therefore, the gate contact layer 14 is preferably provided only in the region where the gate electrode 17 is formed. When the gate contact layer 14 is a nitride semiconductor layer having an Al composition ratio smaller than that of the third nitride semiconductor layer or a nitride semiconductor layer not containing Al, the third nitride semiconductor layer is selectively used as an etching stop layer. This is preferable when etching is performed.

  The gate contact layer 14 may include an InGaN layer. Since the InGaN layer has a function of causing lattice relaxation, the film thickness is preferably equal to or greater than the critical film thickness, and more preferably 5 nm to 10 nm. As a result, the threshold voltage can be suitably increased, so that a normally-off transistor can be realized. At this time, an increase in on-resistance can also be suppressed, so that power consumption and heat generation can be suppressed.

  The gate contact layer 14 is preferably a p-type layer, and further preferably has a p-type layer on the side in contact with the gate electrode 17 and an InGaN layer thereunder. By adding a p-type layer directly below the gate electrode 17, the depletion layer expands even when no bias is applied to the gate electrode 17. Therefore, the effect of increasing the bias necessary to obtain a flat band, in other words, the threshold voltage is increased. An even greater effect can be obtained. When the gate contact layer 14 includes a p-type layer, if the gate contact layer 14 is stacked other than the region where the gate electrode 17 is formed, a depletion layer is formed and current is inhibited, so that only the gate electrode 17 remains. The p-type layer is preferably a p-type GaN layer.

  The gate contact layer 14 is preferably a stack of a p-type GaN layer and an InGaN layer in order from the gate electrode 17 side. In order to prevent diffusion of In into the p-type GaN layer, a GaN layer can be further provided between the p-type GaN layer and the InGaN layer. This GaN layer is typically undoped. Here, p-type GaN refers to GaN containing p-type impurities such as Be, Zn, Mn, Cr, Mg, and Ca. Preferably, Mg is contained.

(Electrodes 15, 16, 17)
A gate electrode 17 is formed on the surface of the gate contact layer 14, and a source electrode 15 and a drain electrode 16 are formed with the gate electrode 17 interposed therebetween. The source electrode 15 and the drain electrode 16 are formed on the surface of the second nitride semiconductor layer 12 or the third nitride semiconductor layer 13, and ohmic electrodes are used to supply current. As the gate electrode 17, a Schottky electrode is used so that a depletion layer can be formed with good controllability and carriers can be controlled. When the gate contact layer is a p layer, an ohmic electrode for the gate contact layer is used. Moreover, although not shown in figure, these electrodes can use suitably the metal layer and alloy layer which consist of several layers, and those combination.

(Nitride semiconductor layer, substrate 18)
The GaN-based FET is composed of a gallium nitride-based compound semiconductor. The gallium nitride compound semiconductor layer forms a buffer layer on the substrate 18 as necessary, and further includes a first nitride semiconductor layer 11, a second nitride semiconductor layer 12, a third nitride semiconductor layer 13, and a gate contact layer. 14 can be epitaxially grown in order, and further electrodes can be stacked. The buffer layer is not necessarily required when a substrate lattice-matched with an epitaxial layer such as GaN is used. As the crystal growth method, for example, metal-organic chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), hydride CVD, MBE (molecular beam epitaxy) and the like can be used. N-type impurities and p-type impurities can be appropriately contained in the gallium nitride compound semiconductor.

  As the growth substrate 18 forming the semiconductor structure, a sapphire substrate, a GaN substrate or the like can be used. The buffer layer and the base layer in the early stage of growth tend to have poor crystallinity, and the portion may become a leak path. For this reason, it is preferable to reduce leakage by adding impurities such as Mg, Zn, and Fe. Further, after growth on a growth substrate, it can be transferred to a SiC substrate, a CuW substrate or the like having high thermal conductivity and excellent heat dissipation.

  The stacked structure of the nitride semiconductor layers may be a mesa structure having a step portion having a side surface exposing the end portion of the first nitride semiconductor layer on at least one side, preferably both sides, of the gate electrode. At least one of the source electrode and the drain electrode, preferably both, connected to at least the end portion of the first nitride semiconductor layer is provided on the side surface of the stepped portion. That is, it is provided on the surface of the second nitride semiconductor layer. Thereby, the source electrode and the drain electrode can be suitably reduced in contact resistance, and the resistance can be further reduced.

(Method for producing field effect transistor)
A method for manufacturing the FET shown in FIG. 1 will be described with reference to FIGS. 2A to 2C are schematic cross-sectional views for explaining a method of manufacturing the FET shown in FIG.

  First, as shown in FIG. 2A, a first nitride semiconductor layer 11, a second nitride semiconductor layer 12, a third nitride semiconductor layer 13, and a gate contact layer 14 are sequentially stacked. A gate electrode 17 is formed on the surface of the gate contact layer 14.

Next, as shown in FIG. 2B, the gate contact layer 14 is removed leaving the region where the gate electrode 17 is formed. In order not to etch deeper than the gate contact layer 14, the first nitride is selectively etched so that the third nitride semiconductor layer 13 serves as an etching stop layer. As the etching at which the third nitride semiconductor layer has a higher etching rate than the gate contact layer, for example, a halogen-based gas having a different etching rate depending on the Al composition ratio, specifically, hydrogen iodide gas, Cl ₂ , or SiCl ₄ is used. be able to.

As shown in FIG. 2C, the second etching is performed to remove the damaged layer due to the first etching. In the second etching, it is preferable to use an etching gas different from the first etching in order to improve the etching rate for the third nitride semiconductor layer 13. For example, a mixed gas of Cl ₂ and methane is used. Further, in order to perform etching without damaging the first etching, it is effective to perform the second etching with a lower output than the first etching or with an etching gas having a lower selectivity than the first etching. It is thought that. Since the etching rate can be suppressed if the output is low, it is also preferable from the viewpoint of preventing the semiconductor layer from being excessively cut. The second nitride semiconductor layer 12 on the third nitride semiconductor layer 13 side has a smaller Al composition ratio than the third nitride semiconductor layer 13 or does not contain Al, and therefore cannot be used as an etching stop layer. In order to sufficiently remove the damaged layer, the third nitride semiconductor layer 13 is completely removed. Typically, dry etching is used for the first etching and the second etching.

  Then, a source electrode and a drain electrode are provided on the surface of the semiconductor layer after the third nitride semiconductor layer 13 is removed. Note that the gate electrode 17 may be provided after etching.

  FIG. 3 shows a band diagram and a change in the carrier concentration Ns with respect to the film thickness l of the second nitride semiconductor layer 12 composed of the first layer 101 and the second layer 102. As shown in FIG. 3, since the second layer 102 has a small Al composition ratio and weak polarization, the band is lowered toward the surface. Accordingly, in the process of cutting the second layer 102, the interface level that becomes higher energy than the Fermi level and becomes positively activated increases, so the carrier concentration also increases. On the other hand, since the first layer 101 has a large Al composition ratio and strong polarization, the band rises toward the surface. Therefore, when etching reaches the first layer 101, the interface state that is activated positively decreases. The carrier concentration starts to decrease.

  The maximum carrier concentration is obtained when the second layer 102 is completely removed. Since the same carrier concentration can be obtained before and after this, the same carrier concentration can be obtained even when the etching accuracy is not sufficient. An FET having a carrier concentration can be obtained stably. Further, under the etching conditions that reduce scattering from the surface, scattering is suppressed, so that mobility is improved. Low resistance can be expected by increasing the carrier concentration and improving the mobility. Further, if the etching conditions are set so that the interface state concentration is higher than that before etching, the carrier concentration is further increased and the resistance can be reduced.

  As described above, it is ideal to completely remove only the second layer 102 in order to increase the carrier concentration. However, since it is difficult in terms of etching accuracy, it is preferable to remove at least part of the second layer 102 so that the thickness of the second layer 102 is different between the gate contact layer 14 and the other portions. The second layer 102 may be completely removed, and a part of the first layer 101 may be removed. Since the carrier concentration decreases if the first layer 101 is excessively etched, the etching depth is aimed to remove only the second layer 102 or remove a part of the second layer 102. It is preferable to set. When the second nitride semiconductor layer 12 is a composition gradient layer, the Al composition ratio of the surface increases as the second nitride semiconductor layer 12 is cut, whereas the film thickness decreases as the cut is reduced. The change becomes a gentler mountain shape than FIG.

As the FET of Example 1, the HEMT 20 shown in FIG. The HEMT 20 shown in FIG. 4 has an undoped i-type GaN layer 22 with a thickness of 3 μm and an undoped i with a thickness of 0.9 nm as a first nitride semiconductor layer on a sapphire substrate 21 via a buffer layer (not shown). 6 nm-thick undoped i-type Al _0.3 Ga _0.7 N layer 24 as the first layer of the second nitride semiconductor layer, and 1 nm-thick undoped i-type Al _0.1 as the second layer. A Ga _0.9 N layer 25, an undoped i-type Al _0.2 Ga _0.8 N layer 26 having a thickness of 1 nm as a third nitride semiconductor layer, and a p-type GaN layer 27 having a thickness of 20 nm as a gate contact layer are sequentially stacked. The gate electrode 33 is provided on the surface of the p-type GaN layer 27. In a region other than under the gate electrode 33, the Al _0.1 Ga _0.9 N layer 25, the Al _0.2 Ga _0.8 N layer 26, and the p-type GaN layer 27 are removed, and the source electrode 31 and the drain electrode 32 are formed. The side surface and the surface of the semiconductor layer exposed from each electrode are covered with the SiO ₂ protective film 34. Further, a stepped portion is formed in which the side surface of the upper portion of the GaN layer 22 that becomes the channel is exposed, and the source electrode 31 and the drain electrode 32 are provided in contact with the side surface of the stepped portion.

The removal of the Al _0.1 Ga _0.9 N layer 25, the Al _0.2 Ga _0.8 N layer 26, and the p-type GaN layer 27 is performed by two-stage etching. First, reactive ion etching (RIE) using hydrogen iodide gas, in which the etching rate of the p-type GaN layer 27 is higher than the etching rate of the Al _0.2 Ga _0.8 N layer 26, is performed. Next, the Al _0.2 Ga _0.8 N layer 26 and the Al _0.1 Ga _0.9 N layer 25 are removed by RIE using a mixed gas of Cl ₂ and methane with the W number lowered.

By removing the Al _0.2 Ga _0.8 N layer 26 and the Al _0.1 Ga _0.9 N layer 25, the HEMT 20 with improved carrier concentration and mobility can be obtained.

(Reference Example 1)
As Reference Example 1, a HEMT different from Example 1 is manufactured in that the Al _0.1 Ga _0.9 N layer 25 and the Al _0.2 Ga _0.8 N layer 26 are omitted. An AlN layer having a thickness of 0.9 nm, an Al _0.3 Ga _0.7 N layer having a thickness of 7 nm, and a p-type GaN layer having a thickness of 20 nm are sequentially formed on the GaN layer as the carrier traveling layer _{. Using the 3} Ga _0.7 N layer as an etching stop layer, the p-type GaN layer other than the gate electrode formation region is removed by selective etching as in the first embodiment. Thereafter, in order to remove the damaged layer by selective etching, a part of the Al _0.3 Ga _0.7 N layer is removed by RIE using a mixed gas of Cl ₂ and methane with the W number lowered. FIG. 5 shows the relationship between the RIE processing time when removing the damaged layer, the mobility and carrier concentration by hole measurement. As shown in FIG. 5, by performing the damage removal process after selective etching, both the carrier concentration and the mobility were increased, and the resistance could be reduced. It is considered that the positively charged interface state concentration is increased by the damage removing step, the carriers as compensation charges are increased, and the improvement of the surface state by removing the damaged layer is linked to the increase in mobility.

As Example 2, instead of the Al _0.3 Ga _0.7 N layer 24 and the Al _0.1 Ga _0.9 N layer 25, an AlGaN layer having a changed Al composition ratio was formed with a film thickness of 7 nm. Instead of the _0.2 Ga _0.8 N layer 26, a HEMT different from that in Example 1 is manufactured in that an Al _0.3 Ga _0.7 N layer is formed with a film thickness of 1 nm. The AlGaN layer is continuously changed by setting the Al composition ratio on the AlN layer side to 0.3 and the Al composition ratio on the Al _0.3 Ga _0.7 N layer side to 0.05.

  FIG. 6 shows the relationship between the RIE processing time when removing the damaged layer after etching the p-type GaN layer, and the mobility and carrier concentration by hole measurement. By the RIE process, both the carrier concentration and the mobility increase, the resistance can be lowered most when the RIE process time is 20 seconds, and the resistance can be greatly reduced from 1000Ω / sq before etching to 600Ω / sq. It was.

DESCRIPTION OF SYMBOLS 10 Field effect transistor 11 1st nitride semiconductor layer 12 2nd nitride semiconductor layer 101 1st layer, 102 2nd layer 13 3rd nitride semiconductor layer 14 Gate contact layer 15 Source electrode, 16 Drain electrode, 17 Gate electrode 18 Substrate 20 High electron mobility transistor 21 Sapphire substrate 22 GaN layer, 23 AlN layer, 24 Al _0.3 Ga _0.7 N layer, 25 Al _0.1 Ga _0.9 N layer, 26 Al _0.2 Ga _{0. 8} N layer, 27 p-type GaN layer 31 Source electrode, 32 Drain electrode, 33 Gate electrode 34 Protective film

Claims (11)

A first nitride semiconductor layer;
A second nitride semiconductor layer including an Al-containing nitride semiconductor provided on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer;
A field effect transistor comprising: a gate contact layer provided on the second nitride semiconductor layer;
A third nitride semiconductor layer made of an Al-containing nitride semiconductor is provided on a part of the second nitride semiconductor layer, and a gate contact layer is provided on the third nitride semiconductor layer;
A gate electrode is provided on the surface of the gate contact layer, and a source electrode and a drain electrode are provided across the gate contact layer and the third nitride semiconductor layer;
The second nitride semiconductor layer has Al _a Ga _1-a N (0 <a ≦ 1) on the side of the _first nitride semiconductor layer and Al _b Ga _1-b N (0 ≦ a) on the side of the third nitride semiconductor layer. b <1, b <a) or InGaN, and the third nitride semiconductor layer is made of an Al-containing nitride semiconductor having an Al composition ratio larger than that of the second nitride semiconductor layer on the third nitride semiconductor layer side. A field effect transistor. The second nitride semiconductor layer includes a first layer made of Al _a Ga _1-a N (0 <a ≦ 1) provided on the first nitride semiconductor layer side, and the third nitride semiconductor layer side 2. The field effect transistor according to claim 1, further comprising: a second layer made of Al _b Ga _1-b N (0 ≦ b <1, b <a) or InGaN provided on the substrate.   2. The field effect transistor according to claim 1, wherein the second nitride semiconductor layer includes a composition gradient layer in which an Al composition ratio decreases with increasing distance from the first nitride semiconductor layer side. The second nitride semiconductor layer is the third nitride semiconductor layer side is _{Al b Ga 1-b N (} 0 <b <1, b <a), the third nitride semiconductor layer is _Al c _{Ga 1-} The field effect transistor according to claim 1, wherein _c N (0 <c ≦ 1, c> b). The source electrode and the drain electrode are provided in the third nitride semiconductor layer,
5. The third nitride semiconductor layer according to claim 1, wherein a thickness of a region where the source electrode and the drain electrode are provided is smaller than a thickness of a region where the gate electrode is provided. The field effect transistor according to 1.   The field effect transistor according to claim 1, wherein the source electrode and the drain electrode are provided in the second semiconductor layer. The field effect transistor according to claim 1, wherein the fourth nitride semiconductor layer is made of Al _c Ga _1-c N (0 <c ≦ 1, b <c <a).   The field effect transistor according to claim 1, wherein the gate contact layer is InGaN or GaN. Semiconductor layer laminating step of sequentially laminating a first nitride semiconductor layer, a second nitride semiconductor layer containing an Al-containing nitride semiconductor having a band gap energy larger than that of the first nitride semiconductor layer, and a gate contact layer When,
A semiconductor layer removing step of removing the gate contact layer leaving a gate electrode formation region,
A method of manufacturing a field effect transistor in which a gate electrode is formed in the gate contact layer, and a source electrode and a drain electrode are formed with the gate contact layer interposed therebetween,
In the semiconductor layer stacking step, as the second nitride semiconductor layer, the first nitride semiconductor layer side is Al _a Ga _1-a N (0 <a ≦ 1) and is opposed to the first nitride semiconductor layer. A nitride semiconductor layer whose side is Al _b Ga _1-b N (0 ≦ b <1, b <a) or InGaN is formed, and the second nitride semiconductor layer is formed on the second nitride semiconductor layer Forming a third nitride semiconductor layer made of an Al-containing nitride semiconductor having an Al composition ratio larger than that of the side facing the first nitride semiconductor layer;
In the semiconductor layer removing step, after the gate contact layer is removed by the first etching using the third nitride semiconductor layer as an etching stop layer, the third nitride semiconductor layer is removed by a second etching different from the first etching. A method of manufacturing a field effect transistor, which is removed to remove a damaged layer by the first etching.   The method of manufacturing a field effect transistor according to claim 9, wherein the second etching is performed at a lower output than the first etching. The second nitride semiconductor layer includes a first layer made of Al _a Ga _1-a N (0 <a ≦ 1) provided on the first nitride semiconductor layer side, and the third nitride semiconductor layer side And a second layer made of InGaN and Al _b Ga _1-b N (0 ≦ b <1, b <a),
The method of manufacturing a field effect transistor according to claim 9 or 10, wherein at least part of the second layer is removed by the second etching.

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