JP2011066464A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor comprising a normally-off type nitride semiconductor capable of obtaining a large enough current density, and a manufacturing method of the same. <P>SOLUTION: On a substrate 101, an AIN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type GaN layer 105 and a high concentration p-type GaN layer 106 are formed sequentially, and a gate electrode 111 has an ohmic junction to the high concentration p-type GaN layer 106. A source electrode 109 and a drain electrode 110 are provided on the undoped AlGaN layer 104. The pn-junction generated by the two-dimensional electron gas generated at the interface between the undoped AlGaN layer 104 and the undoped GaN layer and by the p-type GaN layer 105 is formed at a gate region to be capable of enlarging the gate voltage. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a field effect transistor using a nitride semiconductor that can be applied to a power transistor used in a power circuit of a consumer device such as a television, and a method for manufacturing the same.

Nitride semiconductors, such as GaN (gallium nitride) and AlN (aluminum nitride), which are examples of wide gap semiconductors with large band gaps of 3.4 eV and 6.2 eV at room temperature, have a large dielectric breakdown electric field. The electron saturation drift velocity is higher than that of a compound semiconductor such as GaAs (gallium arsenide) or Si semiconductor. Further, in an AlGaN / GaN heterostructure formed on a substrate having a (0001) plane as a main surface, charges are generated at the heterointerface due to spontaneous polarization and piezoelectric polarization, and 1 × 10 ¹³ cm ⁻² even when undoped. The above sheet carrier concentration is obtained. Therefore, if a two-dimensional electron gas (2DEG) at the heterointerface is used, a heterojunction field effect transistor (HFET) with a large current density can be realized. For this reason, research and development of power transistors using nitride semiconductors, which are advantageous for high output and high breakdown voltage, are now being actively conducted.

  FIG. 15 is a cross-sectional view showing a field effect transistor using an AlGaN / GaN heterostructure according to a conventional example. In the conventional field effect transistor shown in the figure, a low-temperature GaN buffer layer 5502, an undoped GaN layer 5503, and an n-type AlGaN layer 5504 are formed in this order on a sapphire substrate 5501, and a source electrode 5505 composed of a Ti layer and an Al layer. A drain electrode 5506 made of a Ti layer and an Al layer is formed on the n-type AlGaN layer 5504. A gate electrode 5507 made of a Ni layer, a Pt layer, and an Au layer is formed between the source electrode 5505 and the drain electrode 5506. For element isolation, the n-type AlGaN layer 5504 other than the element formation region is removed by, for example, dry etching. This field effect transistor is a so-called normally-on type in which a drain current flows when the gate voltage is 0 V because of the high concentration two-dimensional electron gas generated at the heterointerface between the n-type AlGaN layer 5503 and the undoped GaN layer 5504 described above. It is.

  However, when a GaN-based HFET is applied as a power transistor, a normally-on device may cause a safety problem, for example, the circuit may be destroyed during a power failure. Therefore, in order to put it into practical use as a power transistor, it is necessary to be a so-called normally-off type in which no current flows when the gate voltage is 0V. As a device structure that can satisfy the above requirements, a junction field effect transistor (JFET) using a pn junction as a gate has been proposed and put into practical use in a conventional GaAs-based compound semiconductor (non-patent document). 1). In the JFET structure, by using a pn junction having a larger built-in potential than the Schottky junction for the gate, the gate rising voltage (voltage at which the gate current starts to flow) can be increased, and the gate leakage current can be reduced. Recently, an example in which the adoption of a JFET structure has been studied also in a nitride semiconductor has been reported (see Non-Patent Document 2 and Patent Document 1).

JP 2004-273486 A

J. K. Abrokwah et al., IEEE Transactions on Electron Devices, vol.37, no.6, pp.1529-1531, 1990. L. Zhang et al., IEEE Transactions on Electron Devices, vol.47, no.3, pp.507-511, 2000.

  However, in order to make a conventional GaN-based HFET normally-off type, it is necessary to reduce the Al composition ratio in the n-type AlGaN layer or to reduce the polarization charge amount by thinning the n-type AlGaN layer. It is difficult to achieve both of obtaining a normally-off type.

  In view of the above problems, an object of the present invention is to provide a field effect transistor made of a normally-off type nitride semiconductor that can be applied to a power transistor and can obtain a sufficiently large current density, and a method for manufacturing the same.

  In order to solve the above problems, a field effect transistor of the present invention is provided on a substrate, a first nitride semiconductor layer provided above the substrate, and the first nitride semiconductor layer, A second nitride semiconductor layer having a larger band gap energy than the first nitride semiconductor and generating a two-dimensional electron gas at the interface with the first nitride semiconductor layer during operation; A p-type third nitride semiconductor layer; a gate electrode provided on or above the third nitride semiconductor layer; and the second nitride semiconductor. Alternatively, a source electrode and a drain electrode provided on both sides of the gate electrode as viewed in a plan view are provided.

  According to this configuration, the third nitride semiconductor layer is p-type, and a two-dimensional electron gas is formed during operation at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A pn junction is formed in the gate region. For this reason, even if a high gate voltage is applied as compared with the conventional field effect transistor, it is difficult for the gate leakage current to flow, and a large drain current can be obtained. In this case, the gate electrode is preferably an ohmic electrode.

  The field effect transistor of the present invention can also be a normally-off type. In particular, when the second nitride semiconductor layer is an undoped layer, a normally-off type HFET can be easily realized.

  Further, in the second nitride semiconductor layer, the portion where the electric field concentrates during operation because the thickness of the portion located immediately below the gate electrode is larger than the thickness of the portion located below the source electrode and the drain electrode. In the second nitride semiconductor layer having a large band gap, the pressure resistance can be greatly improved.

  The field effect transistor manufacturing method of the present invention includes a step (a) of sequentially epitaxially growing a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer above a substrate. , Selectively removing the first nitride semiconductor layer and a part of the upper portion of the second nitride semiconductor layer, the first nitride semiconductor layer and the second nitride semiconductor layer A step (b) of generating a two-dimensional electron gas in a region located immediately below the removed portion of the interface, and a region of the second nitride semiconductor layer in which the upper portion is removed in the step (b) A step (c) of forming a source electrode and a drain electrode thereon, and a step (d) of forming a gate electrode on or above the third nitride semiconductor layer.

  By this method, a two-dimensional electron gas is formed in a portion of the interface between the first nitride semiconductor layer and the second nitride semiconductor layer located below the source electrode and the drain electrode, and below the gate electrode. It is possible to manufacture a field effect transistor in which a two-dimensional electron gas is not formed in the portion that is positioned. That is, according to the method of the present invention, a large current can be obtained during operation, and a normally-off type field effect transistor can be manufactured. Further, since a pn junction is formed in the gate region of the field effect transistor manufactured by the method of the present invention, it is difficult for gate leakage current to occur even when the voltage applied to the gate electrode is increased. Therefore, it is possible to obtain a larger on-current than before.

  As described above, according to the field effect transistor of the present invention, the gate rising voltage can be set to a large value corresponding to the band gap of the semiconductor, so that a large drain current can be obtained. In addition, a field effect transistor with a small gate leakage current can be realized. Furthermore, by selectively introducing an n-type impurity into the nitride semiconductor layer immediately below the source electrode and the drain electrode, the source resistance and the drain resistance can be reduced, and a field effect transistor with a smaller series resistance can be realized. Is possible. Further, by forming two or more n-type regions having different concentrations between the gate electrode and the drain electrode, when a high voltage is applied to the drain electrode, a depletion layer is formed in the n-type region having a lower impurity concentration. The pressure resistance is improved by extending.

It is sectional drawing which shows the field effect transistor which concerns on the 1st Embodiment of this invention. (A) is an energy band diagram in the longitudinal section of the gate region of the field effect transistor according to the first embodiment, (b) is an energy band diagram in the longitudinal section between the gate region and the source region. is there. (A), (b) is the figure which shows the relationship between a gate voltage and a drain current in the field effect transistor which concerns on 1st Embodiment, respectively, and the figure which shows the relationship between a drain current and a drain voltage. It is sectional drawing which shows the field effect transistor which concerns on the 2nd Embodiment of this invention. It is an energy band figure in the longitudinal section of the gate field of the field effect transistor concerning a 2nd embodiment. (A), (b) is the figure which shows the relationship between a gate voltage and a drain current in the field effect transistor which concerns on 2nd Embodiment, respectively, and the figure which shows the relationship between a drain current and a drain voltage. It is a figure which shows the forward current-voltage characteristic between gate-sources of the field effect transistor which concerns on the 1st and 2nd embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on 2nd Embodiment. It is sectional drawing which shows the field effect transistor which concerns on the 3rd Embodiment of this invention. It is an energy band figure in the longitudinal section of the gate region of the field effect transistor concerning a 3rd embodiment. (A)-(g) is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on 3rd Embodiment. It is sectional drawing which shows the field effect transistor which concerns on the 4th Embodiment of this invention. It is an energy band figure in the longitudinal section of the gate region of the field effect transistor concerning a 4th embodiment. It is sectional drawing which shows the field effect transistor which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows the conventional field effect transistor using an AlGaN / GaN heterostructure.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a sectional view showing a field effect transistor according to the first embodiment of the present invention.

As shown in the figure, the field effect transistor of this embodiment includes a sapphire substrate 101, a 100 nm thick AlN buffer layer 102 provided on the sapphire substrate 101, and a thickness provided on the AlN buffer layer 102. An undoped GaN layer 103 having a thickness of 2 μm, an undoped AlGaN layer 104 having a thickness of 25 nm provided on the undoped GaN layer 103, and a p-type GaN layer having a thickness of 100 nm provided on a part of the undoped AlGaN layer 104 105 and a high-concentration p-type GaN layer 106 having a thickness of 5 nm, which is provided on the p-type GaN layer 105 and contains a higher concentration of p-type impurities than the p-type GaN layer 105. Here, “undoped” means that impurities are not intentionally introduced. In the field effect transistor of this embodiment, the undoped AlGaN layer 104 is made of, for example, undoped Al _0.25 Ga _0.75 N.

  On the high-concentration p-type GaN layer 106, a gate electrode 111 made of Pd (palladium) that is in ohmic contact with the high-concentration p-type GaN layer 106 is provided. In addition, a SiN film 108 that is partially opened is provided on the undoped AlGaN layer 104, the side surface of the p-type GaN layer 105, and the side surface and upper surface of the high-concentration p-type GaN layer 106. A source electrode 109 and a drain electrode 110 made of a Ti layer and an Al layer are provided on the undoped AlGaN layer 104 so as to sandwich the p-type GaN layer 105, which is an opening of the SiN film 108. . Further, if a region where a field effect transistor is formed in the substrate is referred to as an “element formation region”, the element isolation region 107 is provided so as to surround the element formation region.

  The high-concentration p-type GaN layer 106 and the p-type GaN layer 105 other than the gate region are removed by selective etching. A part of the undoped AlGaN layer 104 is also removed by selective etching, and the thickness of the gate region in the undoped AlGaN layer 104 is larger than the thickness of other regions. The source electrode 109 and the drain electrode 110 described above are formed on the undoped AlGaN layer 104 that is partially etched. As described above, the contact surface between the source and drain electrodes and the undoped AlGaN layer 104 is positioned below the heterointerface between the p-type GaN layer 105 and the undoped AlGaN layer 104 in the gate region, so that a high drain voltage is obtained. When the voltage is applied, the corner around the lower end of the gate step where the electric field strength becomes maximum is located in the AlGaN layer having a large band gap. Therefore, the breakdown voltage between the gate and drain electrodes can be improved as compared with the case where the entire upper surface of the undoped AlGaN layer 104 is flat. However, even if the upper surface of the undoped AlGaN layer 104 is flat and the thin p-type GaN layer 105 is sandwiched between the undoped AlGaN layer 104 and the source electrode 109 and the drain electrode 110, the transistor can be operated without any problem. Further, in the undoped AlGaN layer 104, the thickness of the portion in contact with the source electrode 109 and the drain electrode 110 is smaller than the thickness of the portion located in the gate region, so that the source electrode 109 and the drain electrode 110 and the two-dimensional electron gas are Therefore, the ohmic contact resistance at the interface between the undoped AlGaN layer 104 and the source electrode 109 and the drain electrode 110 can be reduced. However, if the thickness of the undoped AlGaN layer 104 in contact with the source and drain electrodes becomes too thin, the channel resistance between the gate and source electrodes or between the gate and drain electrodes increases, so the undoped AlGaN layer 104 is a film of about 10 nm or more. Thickness is desirable.

  The element isolation region 107 is formed by increasing the resistance of part of the undoped AlGaN layer 104 and the undoped GaN layer 103 by ion implantation of, for example, B (boron). Therefore, no step is formed between the element formation region and the element isolation region 107. In the conventional field effect transistor shown in FIG. 15, when element isolation is performed by forming a step using dry etching, a crystal defect is generated by etching, and thus a leakage current through the crystal defect is generated in the step portion. In contrast, in the field effect transistor of this embodiment, the source-drain leakage current and the element-to-element leakage current are greatly reduced.

  In the GaN-based HFET, so-called current collapse, in which the drain current decreases when the drain voltage is increased, often causes a problem. In the field effect transistor of this embodiment, the upper surface portion other than the source, drain, and gate electrodes is all formed on the SiN film. Since it is covered with 108, the surface level is reduced and the occurrence of current collapse is suppressed.

In order to suppress the spread of the depletion layer to the p-type GaN layer 105, the carrier concentration in the p-type GaN layer 105 is desirably 1 × 10 ¹⁸ cm ⁻³ or more. In the field effect transistor of this embodiment, the carrier concentration in the p-type GaN layer 105 is set to 1 × 10 ¹⁸ cm ⁻³ . In the field effect transistor of this embodiment, the concentration of the two-dimensional electron gas generated at the interface between the undoped AlGaN layer 104 and the undoped GaN layer 103 is about 1 × 10 ¹³ cm ⁻² and the p-type GaN layer 105 having a thickness of 100 nm. By setting the inside carrier concentration to 1 × 10 ¹⁸ cm ⁻³ , the two-dimensional electron gas generated at the interface between the undoped AlGaN layer 104 and the undoped GaN layer 103 can be canceled, and the field effect transistor can be made a normally-off type. . Here, if the number of carriers per sheet in the p-type GaN layer 105 is greater than or equal to the number of electrons of the two-dimensional electron gas, the two-dimensional electron gas can be offset. In order to adjust the field effect transistor to a normally-off type, in addition to adjusting the impurity concentration, the thickness of the undoped AlGaN layer 104 may be adjusted.

  The field effect transistor of the present embodiment is characterized by a two-dimensional electron gas formed at the interface between the undoped AlGaN layer 104 and the undoped GaN layer 103 because the gate electrode 111 is in ohmic contact with the high-concentration p-type GaN layer 106. And the p-type GaN layer 105 form a pn junction formed in the gate region. Since the barrier due to the pn junction is larger than the barrier due to the Schottky junction, in the field effect transistor of this embodiment, gate leakage is less likely to occur even when the gate voltage is higher than in the prior art.

  In the field effect transistor of this embodiment, since the thin high-concentration p-type GaN layer 106 is provided under the gate electrode 111, it is easy to form an ohmic junction with the gate electrode 111. In general, a p-type GaN-based semiconductor is less likely to form an ohmic junction than a p-type GaAs-based semiconductor, and thus it is not essential that the high-concentration p-type GaN layer 106 is provided. 106 is preferably provided. The material of the gate electrode is preferably a material having a high work function, and Ni or the like can be used in addition to Pd.

  FIG. 2A is an energy band diagram in the longitudinal section of the gate region of the field effect transistor according to this embodiment, and FIG. 2B is an energy band diagram in the longitudinal section between the gate region and the source region. is there.

  As shown in FIGS. 2 (a) and 2 (b), at the heterointerface between the undoped AlGaN layer and the undoped GaN layer, the junction between the undoped layers is a junction band due to charges generated by spontaneous polarization and piezoelectric polarization. Grooves are formed. On the other hand, as shown in FIG. 2B, since the p-type GaN layer 105 is not connected to the undoped AlGaN layer 104 in the element region other than the gate region, the groove of this conduction band is located at a position lower than the Fermi level. The two-dimensional electron gas is formed even when no gate voltage is applied. However, in the gate region, as shown in FIG. 2A, the p-type GaN layer 105 is connected to the undoped AlGaN layer 104, whereby the energy levels of the undoped AlGaN layer 104 and the undoped GaN layer 103 are raised, and the undoped The groove of the conduction band at the heterointerface between the AlGaN layer 104 and the undoped GaN layer 103 is at the same position as the Fermi level. As a result, in the state where no bias is applied to the gate electrode, the two-dimensional electron gas is not formed in the gate region, and the normally-off state is obtained. As described above, since a two-dimensional electron gas is generated in the element formation region other than the gate region, a large current flows between the source and the drain when a positive bias is applied to the gate electrode 111.

  In addition, when a positive bias is applied to the gate electrode, the gate voltage (gate rising voltage) at which the gate current starts to flow increases as the band gap of the semiconductor used increases. As the gate rising voltage is larger, a larger positive bias can be applied to the gate electrode and the drain current can be increased. Therefore, this value is desirably large. When a semiconductor such as GaAs is used, the gate rising voltage is about 1 V. However, in the present invention using a GaN-based semiconductor, the gate rising voltage is a large value corresponding to the band gap of the semiconductor.

  FIGS. 3A and 3B are a diagram showing a relationship between the gate voltage and the drain current and a diagram showing a relationship between the drain current and the drain voltage in the field effect transistor of this embodiment, respectively. As can be seen from FIG. 3A, the field effect transistor of the present embodiment has a threshold voltage of about 0 V and realizes normally-off. Further, since the gate rising voltage is large, even when a positive bias of 2 V is applied to the gate electrode 111, the gate leakage current hardly flows, and a maximum drain current of 300 mmA / mm or more is obtained as shown in FIG. It is done.

  In the above description, the field effect transistor is formed using the (0001) plane of the sapphire substrate 101 as the main surface. However, for example, the field effect is formed on the (10-12) plane (R plane) of the sapphire substrate 101. A transistor may be manufactured. In this case, since a polarization electric field is not generated in the growth direction of the nitride semiconductor, it becomes easy to control the sheet carrier concentration of the two-dimensional electron gas, and it becomes easy to manufacture a normally-off type field effect transistor. That is, in order to set the threshold voltage to a larger positive value, a field effect transistor is not formed on the (0001) plane (that is, c-plane) of the sapphire substrate 101, but a nonpolar plane of nitride semiconductor is obtained. It is desirable to use a substrate that can be used. At this time, an n-type AlGaN layer may be provided in place of the undoped AlGaN layer 104.

In addition, although the example in which the undoped AlGaN layer 104 is composed of Al _0.25 Ga _0.75 N has been described for the field effect transistor of the present embodiment, the composition ratio of Al and Ga is not limited thereto. Further, an undoped AlN layer may be provided instead of the undoped AlGaN layer 104. In these cases, if the composition of the undoped AlGaN layer 104 changes, the band diagram also changes. Therefore, the film thickness, impurity concentration, etc. of each layer are adjusted as appropriate so that the threshold becomes 0 V or more.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing a field effect transistor according to the second embodiment of the present invention.

  As shown in the figure, the field effect transistor of this embodiment includes a sapphire substrate 401, a 100 nm thick AlN buffer layer 402 provided on the sapphire substrate 401, and a thickness provided on the AlN buffer layer 402. An undoped GaN layer 403 having a thickness of 2 μm, an undoped AlGaN layer 404 having a thickness of 25 nm provided on the undoped GaN layer 403, and a p-type AlGaN layer having a thickness of 100 nm provided on a part of the undoped AlGaN layer 404 405 and a high-concentration p-type GaN layer 406 having a thickness of 5 nm provided on the p-type AlGaN layer 405. In addition, the field effect transistor of the present embodiment includes a gate electrode 411 made of Pd that is in ohmic contact with the high-concentration p-type GaN layer 406, a source electrode 409 that is in ohmic contact with the undoped AlGaN layer 404, and made of a Ti layer and an Al layer. A drain electrode 410 and a SiN film 408 are provided. In addition, the element formation region is electrically insulated from adjacent elements by the element isolation region 407.

The field effect transistor of this embodiment is different from the field effect transistor of the first embodiment in that a p-type AlGaN layer 405 is provided instead of the p-type GaN layer 105. Other configurations are the same as those of the first embodiment. The p-type AlGaN layer 405 is made of a material having the same composition as that of the undoped AlGaN layer 404 and is made of, for example, Al _0.25 Ga _0.75 N.

  FIG. 5 is an energy band diagram in a longitudinal section of the gate region of the field effect transistor according to the present embodiment.

  As shown in the figure, in the field effect transistor of this embodiment, since the p-type AlGaN layer 405 and the undoped AlGaN layer 404 are made of the same material, no band discontinuity occurs at the interface between the two layers. Compared to this, in the field effect transistor of the first embodiment shown in FIG. 2, band discontinuity occurs at the heterointerface between the p-type GaN layer and the undoped AlGaN layer. Therefore, in the field effect transistor of the present embodiment, holes are not accumulated at the interface between the p-type AlGaN layer 405 and the undoped AlGaN layer, and the generation of gate leakage current due to band-to-band tunneling is greater than in the first embodiment. It is surely suppressed. As a result, the gate effect voltage of the field effect transistor of this embodiment is higher than that of the field effect transistor of the first embodiment.

  FIG. 5 shows an example in which the composition ratio of the p-type AlGaN layer 405 is the same as that of the undoped AlGaN layer. However, a p-type nitride semiconductor layer having a larger band gap than the undoped AlGaN layer 404 is used as the p-type AlGaN layer 405. It may be provided instead of. In this case, a band discontinuity is formed at the heterointerface between the undoped AlGaN layer 404 and the p-type AlGaN layer 405. However, since the potential energy of the valence band of the p-type AlGaN layer 405 decreases as it approaches the undoped AlGaN layer 404, holes do not accumulate near the interface between the undoped AlGaN layer 404 and the p-type AlGaN layer 405. .

  FIGS. 6A and 6B are a diagram showing a relationship between the gate voltage and the drain current and a diagram showing a relationship between the drain current and the drain voltage in the field effect transistor of this embodiment, respectively. As can be seen from FIG. 6A, the threshold voltage is about 0 V, and normally-off is realized. Further, as shown in FIG. 6B, since the gate leakage current is less likely to occur, in the field effect transistor of this embodiment, the gate leakage is increased even if the gate-source voltage Vgs is increased to 2.5V. It can be operated without generating current.

  FIG. 7 is a diagram showing the forward current / voltage characteristics between the gate and the source of the field effect transistor according to the first and second embodiments of the present invention. From the results shown in the figure, it can be seen that the field effect transistor of the second embodiment has a higher gate rise voltage than the field effect transistor of the first embodiment. Therefore, in the field effect transistor of the present embodiment, a large positive bias can be applied to the gate electrode, so that a drain current larger than that of the field effect transistor of the first embodiment can be obtained.

  Next, an example of a method for manufacturing the field effect transistor of this embodiment shown in FIG. 4 will be described. 8A to 8F are cross-sectional views illustrating a method for manufacturing a field effect transistor according to this embodiment.

  First, as shown in FIG. 8A, an AlN buffer layer 402 having a thickness of 100 nm is formed on the (0001) surface of the sapphire substrate 401 by metal organic chemical vapor deposition (MOCVD). An undoped GaN layer 403 having a thickness of 2 μm, an undoped AlGaN layer 404 having a thickness of 25 nm, a p-type AlGaN layer 405 having a thickness of 100 nm, and a high-concentration p-type GaN layer 406 having a thickness of 5 nm are formed in this order.

  Next, as shown in FIG. 8B, the upper portions of the high-concentration p-type GaN layer 406, the p-type AlGaN layer 405, and the undoped AlGaN layer 404 are formed by dry etching such as ICP (Inductive-Coupled Plasma) etching. A portion other than the gate region is selectively removed.

  Next, as shown in FIG. 8C, in the state where the element formation region is covered with a photoresist or the like, for example, B (boron) or the like is ion-implanted to partially increase the undoped AlGaN layer 404 and the undoped GaN layer 403. Resistive is formed, and an element isolation region 407 is formed.

Subsequently, as shown in FIG. 8D, a SiN film 408 having a thickness of, for example, 100 nm is formed by a vapor deposition method (Chemical Vapor Deposition: CVD) using SiH ₄ , NH ₃ and N ₂ .

Next, as shown in FIG. 8E, an SiN film is opened by, for example, ICP dry etching, and a source electrode 409 and a drain electrode 410 made of a Ti layer and an Al layer are formed in the opening, and an N ₂ atmosphere is formed. A heat treatment is performed at 650 ° C.

  Next, as shown in FIG. 8F, the portion of the SiN film 408 provided on the high-concentration p-type GaN layer 406 is removed by ICP dry etching, for example. Subsequently, a gate electrode 411 made of Pd is formed in the opening of the SiN film 408. Note that the source electrode 409, the drain electrode 410, and the gate electrode 411 may be formed before the SiN film 408. The element isolation region 407 may be formed after the source electrode 409, the drain electrode 410, and the gate electrode 411. As described above, the field effect transistor of this embodiment can be manufactured.

(Third embodiment)
FIG. 9 is a sectional view showing a field effect transistor according to the third embodiment of the present invention.

  As shown in the figure, the field effect transistor of this embodiment includes a sapphire substrate 901, an AlN buffer layer 902 having a thickness of 100 nm provided on the sapphire substrate 901, and a thickness provided on the AlN buffer layer 902. An undoped GaN layer 903 having a thickness of 2 μm, an n-type GaN layer 904 having a thickness of 5 nm provided on the undoped GaN layer 903, and an undoped AlGaN layer 905 having a thickness of 20 nm provided on the n-type GaN layer 904, A p-type AlGaN layer 906 having a thickness of 100 nm provided on the undoped AlGaN layer 905 and a high-concentration p-type GaN layer 907 having a thickness of 5 nm provided on the p-type AlGaN layer 906. In addition, the field effect transistor according to the present embodiment is provided on both sides of the n-type GaN layer 904 and on the undoped GaN layer 903, and includes a high-concentration n containing a higher concentration of n-type impurities than the n-type GaN layer 904. Is provided between the n-type region 909, the n-type GaN layer 904, the undoped AlGaN layer 905, and one of the high-concentration n-type regions 909 (drain region). A low-concentration n-type region 908 including a source electrode 912 and a drain electrode 913 made of Ti / Al provided on the high-concentration n-type region 909, respectively. Similar to the field effect transistors of the first and second embodiments, the field effect transistor of the present embodiment is provided with the element isolation region 910, the gate electrode 914 made of Pd, and the SiN film 911.

In the field effect transistor of this embodiment, since the high concentration n-type region 909 is formed by ion implantation of Si, the ohmic contact resistance generated between the source electrode 912 and the drain electrode 913 and the high concentration n-type region 909 is The source resistance and drain resistance are reduced significantly. Therefore, the field effect transistor according to the present embodiment can flow a large current during operation while being normally-off type. In addition, power consumption is reduced compared to conventional field effect transistors. In order to sufficiently reduce the ohmic contact resistance, the carrier concentration in the high concentration n-type region is preferably 2 × 10 ¹⁸ cm ⁻³ or more.

Further, the carrier concentration of the low concentration n-type region 908 is, for example, about 1 × 10 ¹⁷ cm ⁻³ . When the low-concentration n-type region 908 is formed between the n-type GaN layer 904 and the undoped AlGaN layer 905 and the high-concentration n-type region 909 on the drain electrode side, when a high voltage is applied to the drain electrode, Since the electric field is prevented from concentrating on the high-concentration n-type region on the drain side, the breakdown voltage can be increased.

  FIG. 10 is an energy band diagram in a longitudinal section of the gate region of the field effect transistor according to the present embodiment.

  As shown in the figure, in the field effect transistor of this embodiment, an n-type GaN layer 904 functioning as a channel is inserted between an undoped GaN layer 903 and an undoped AlGaN layer 905. For this reason, the width of the groove (well) in the conduction band at the heterointerface between the undoped AlGaN layer 905 and the n-type GaN layer 904 in which carriers travel is wider than when the n-type GaN layer 904 is not inserted. Therefore, the channel resistance when the positive bias is applied to the gate electrode 914 to turn on the field effect transistor is reduced, and a large drain current can be extracted.

  Next, an example of a method for manufacturing the field effect transistor of this embodiment shown in FIG. 9 will be described. 11A to 11G are cross-sectional views illustrating a method for manufacturing a field effect transistor according to this embodiment.

  First, as shown in FIG. 11A, an AlN buffer layer 902 having a thickness of 100 nm, an undoped GaN layer 903 having a thickness of 2 μm, and a thickness of 5 nm are formed on the (0001) surface of the sapphire substrate 901 by MOCVD. An n-type GaN layer 904, an undoped AlGaN layer 905 having a thickness of 20 nm, a p-type AlGaN layer 906 having a thickness of 100 nm, and a high-concentration p-type GaN layer 907 having a thickness of 5 nm are sequentially formed.

  Next, as shown in FIG. 11B, portions other than the gate region in the upper portions of the high-concentration p-type GaN layer 907, the p-type AlGaN layer 906, and the undoped AlGaN layer 905 by dry etching such as ICP etching, for example. Is selectively removed.

Next, as shown in FIG. 11C, after implanting Si ions into regions of the substrate located on both sides of the gate region, an impurity activation heat treatment is performed in an N ₂ atmosphere, thereby reducing the low concentration n. A mold region 908 and a high concentration n-type region 909 are formed.

  Subsequently, as shown in FIG. 11D, for example, B is ion-implanted to increase the resistance of the undoped AlGaN layer 905, the n-type GaN layer 904, and a part of the undoped GaN layer 903, thereby forming an element isolation region 910. To do.

Next, as shown in FIG. 11E, a SiN film 911 having a thickness of 100 nm is formed on the substrate by a CVD method using SiH ₄ , NH ₃ and N ₂ .

Next, as shown in FIG. 11F, the portion of the SiN film 911 provided on the high concentration n-type region 909 is removed by, for example, ICP dry etching. Subsequently, a source electrode 912 and a drain electrode 913 made of a Ti layer and an Al layer are formed in the opening of the SiN film 911, and heat treatment is performed at 650 ° C. in an N ₂ atmosphere.

  Next, as shown in FIG. 11G, the portion of the SiN film 911 provided on the high-concentration p-type GaN layer 907 is removed by, for example, ICP dry etching. Subsequently, a gate electrode 914 made of Pd is formed in the opening of the SiN film 911. Here, the method of forming the SiN film 911 before forming the electrode is shown, but the SiN film 911 may be formed after forming the electrode. Further, the element isolation region may be formed by ion implantation after the formation of the SiN film 911. As described above, the field effect transistor of this embodiment can be manufactured.

(Fourth embodiment)
FIG. 12 is a cross-sectional view showing a field effect transistor according to the fourth embodiment of the present invention. As shown in the figure, the field effect transistor of this embodiment includes a sapphire substrate 1201, an AlN buffer layer 1202 having a thickness of 100 nm, an undoped GaN layer 1203 having a thickness of 2 μm, and a thickness provided on the sapphire substrate 1201 in this order. An n-type GaN layer 1204 having a thickness of 5 nm, an undoped AlGaN layer 1205 having a thickness of 20 nm, a p-type composition gradient AlGaN layer 1206 having a thickness of 100 nm, and a high-concentration p-type GaN layer 1207 having a thickness of 5 nm are provided. The field effect transistor of this embodiment includes a high concentration n-type region 1209, a low concentration n-type region 1208 containing an n-type impurity at a concentration lower than that of the high concentration n-type region 909, and a high concentration n-type region 1209. A source electrode 1212 and a drain electrode 1213 made of Ti / Al are provided on each of them. Similar to the field effect transistors of the first to third embodiments, the field effect transistor of this embodiment is provided with the element isolation regions 1210, the gate electrode 1214 made of Pd, and the SiN film 1211. That is, the field effect transistor of this embodiment is the same as the field effect transistor according to the third embodiment, except that the p-type composition gradient AlGaN layer 1206 is provided instead of the p-type AlGaN layer 906.

FIG. 13 is an energy band diagram in the longitudinal section of the gate region of the field effect transistor according to the present embodiment. In the field effect transistor of the present embodiment, the Al composition ratio of the p-type composition gradient AlGaN layer 1206 changes so that it is highest on the sapphire substrate side and zero on the gate electrode side. That is, the p-type composition gradient AlGaN layer 1206 has the same composition as the undoped AlGaN layer 1205 at the interface in contact with the undoped AlGaN layer 1205 and the same composition as the high-concentration p-type GaN layer 1207 at the interface in contact with the high-concentration p-type GaN layer 1207. Thus, the composition of Al and Ga changes in an inclined manner. Here, the undoped AlGaN layer 1205 is made of, for example, Al _0.25 Ga _0.75 N.

  Due to the above-described configuration, no band discontinuity occurs at the interface between the p-type composition gradient AlGaN layer 1206 and the undoped AlGaN layer 1205, and no gate leakage current due to band-to-band tunneling occurs. As a result, the gate rising voltage becomes high, so that a large drain current can be obtained.

  Also, since the p-type carrier concentration can be higher in the GaN layer than in the AlGaN layer, the carrier concentration on the gate electrode side portion of the p-type composition gradient AlGaN layer 1206 should be higher than that on the substrate side. Can do. As a result, it is possible to easily form an ohmic junction with the gate electrode.

  Further, the Al composition ratio in the vicinity of the interface with the undoped AlGaN layer 1205 in the p-type composition gradient AlGaN layer 1206 may be made larger than that in the undoped AlGaN layer 1205. Also in this case, since holes are not accumulated near the interface between the p-type composition gradient AlGaN layer 1206 and the undoped AlGaN, it is possible to suppress the gate leakage current from flowing through the undoped AlGaN layer 1205 due to the band-to-band tunneling. it can.

  In the present embodiment, an example in which the Al composition of the p-type AlGaN layer is changed in an inclined manner has been shown. However, when the p-type GaN layer is provided on the undoped AlGaN layer as in the first embodiment. May eliminate the band discontinuity at the interface between the p-type GaN layer and the undoped AlGaN layer by changing the Al composition of the undoped AlGaN layer in a gradient.

(Fifth embodiment)
FIG. 14 is a sectional view showing a field effect transistor according to the fifth embodiment of the present invention.

As shown in the figure, in the field effect transistor of this embodiment, for example, a Si substrate is used as a conductive substrate.

  That is, the field effect transistor of this embodiment includes a Si substrate 1401, an AlN buffer layer 1402 having a thickness of 100 nm, an undoped GaN layer 1403 having a thickness of 1 μm, and an undoped layer having a thickness of 25 nm, which are sequentially provided on the upper surface of the Si substrate 1401. An AlGaN layer 1404 and a high-concentration p-type GaN layer 1406 having a thickness of 5 nm are provided.

  In addition, the field effect transistor of this embodiment includes a gate electrode 1411 made of Pd that is in ohmic contact with the high-concentration p-type GaN layer 1406, a source electrode 1409 that is in ohmic contact with the undoped AlGaN layer 1404, and made of a Ti layer and an Al layer. A drain electrode 1410, a back electrode 1415 that is in ohmic contact with the back surface of the Si substrate 1401, and a SiN film 1408 are formed, and an element isolation region 1407 surrounding the element formation region is formed. Furthermore, in the field effect transistor of the present embodiment, a via hole 1412 that is formed in the element formation region and extends from the SiN film 1408 to the Si substrate 1401 is provided at the bottom of the via hole 1412 and is in ohmic contact with the Si substrate 1401. A via hole metal 1413 made of Al or the like, and a wiring metal 1414 connecting the source electrode 1409 and the via hole metal 1413 are formed. As a material for the back electrode 1415, a laminate of titanium silicide (TiSi) and titanium nitride (TiN) is used. In the case where silicon carbide (SiC) is used as the conductive substrate instead of the Si substrate, a Ti / Al laminate can be used as the back electrode.

  In the field effect transistor of this embodiment, the source electrode 1409 is electrically connected to the Si substrate 1401 through the wiring metal 1414 and the via hole metal 1413. Therefore, the source electrode 1409 can be grounded via the via hole metal 1413 and the back electrode 1415 by setting the back electrode 1415 to the ground potential. As a result, the source wiring on the element surface can be eliminated, and the element area can be reduced. In addition, when a high drain voltage is applied, the lines of electric force from the drain electrode are directed not only to the gate electrode but also to the Si substrate, so that the electric field concentration between the gate and drain electrodes can be relaxed and the breakdown voltage can be increased. . Therefore, the element structure of this embodiment is effective for operating as a power transistor.

  The field effect transistor of the present invention is useful as a power transistor used in a power circuit of a consumer device such as a television.

101, 401, 901, 1201 Sapphire substrate
102, 402, 902, 1202, 1402 AlN buffer layer
103, 403, 903, 1203, 1403 Undoped GaN layer
104, 404, 905, 1205, 1404 Undoped AlGaN layer
105 p-type GaN layer
106, 406, 907, 1207, 1406 High-concentration p-type GaN layer
107, 407, 910, 1210, 1407 Element isolation region
108, 408, 911, 1211, 1408 SiN film
109, 409, 912, 1212, 1409 Source electrode
110, 410, 913, 1213, 1410 Drain electrode
111, 411, 914, 1214, 1411 Gate electrode
405, 906 p-type AlGaN layer
904, 1204 n-type GaN layer
908, 1208 Low concentration n-type region
909, 1209 High concentration n-type region
1206 P-type composition gradient AlGaN layer
1401 Si substrate
1412 Bahia Hall
1413 Via Hole Metal
1414 Wiring metal
1415 Back electrode

Claims (14)

A substrate,
A first nitride semiconductor layer provided on the substrate;
Provided on the first nitride semiconductor layer, has a band gap energy larger than that of the first nitride semiconductor layer, and generates a two-dimensional electron gas at the interface with the first nitride semiconductor layer during operation. A second nitride semiconductor layer,
A p-type third nitride semiconductor layer provided on the second nitride semiconductor layer;
A gate electrode provided on the third nitride semiconductor layer;
A source electrode and a drain electrode provided on both sides of the gate electrode in plan view on the second nitride semiconductor;
A via hole formed from the second nitride semiconductor layer to the substrate;
Via hole metal provided at the bottom of the via hole;
A field effect transistor comprising a wiring metal connecting the via hole metal and the source electrode.   The field effect transistor according to claim 1, wherein the second nitride semiconductor layer is an undoped layer.   The field effect transistor according to claim 1, wherein the gate electrode is an ohmic electrode.   2. The field effect transistor according to claim 1, which is a normally-off type.   When the third nitride semiconductor layer is not provided, the third nitride is more than the number of electrons of the two-dimensional electron gas generated at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer. 5. The field effect transistor according to claim 4, wherein the number of holes contained in the semiconductor layer is larger. A fourth nitride semiconductor layer, which is provided between the third nitride semiconductor layer and the gate electrode and contains a higher concentration of p-type impurities than the other part of the third nitride semiconductor layer; With
The field effect transistor according to claim 1, wherein the gate electrode is in ohmic contact with the fourth nitride semiconductor layer. Of the second nitride semiconductor layer, the thickness of the portion located immediately below the gate electrode is larger than the thickness of the portion located directly below the source electrode and the drain electrode,
The field effect transistor according to claim 1, wherein the source electrode and the drain electrode are both provided on the second nitride semiconductor layer. The first nitride semiconductor is composed of GaN;
The second nitride semiconductor layer is made of Al _x Ga _1-x N (0 <x ≦ 1),
The field effect transistor according to claim 1, wherein the third nitride semiconductor layer is made of Al _y Ga _1-y N (0 ≦ y ≦ 1).   9. The field effect transistor according to claim 8, wherein an Al composition ratio y of the third nitride semiconductor layer increases in a slope as it goes downward. A first n-type region into which an n-type impurity is introduced is formed in a region located immediately below the source electrode and the drain electrode in the first nitride semiconductor layer and the second nitride semiconductor layer. The field effect transistor according to claim 1, wherein the first n-type region is in contact with the source electrode or the drain region.   Of the first nitride semiconductor layer and the second nitride semiconductor layer, between the first n-type region formed below the drain electrode and a region located directly below the gate electrode The field effect transistor according to claim 10, wherein a second n-type region containing an n-type impurity at a lower concentration than the first n-type region is formed.   2. The field effect transistor according to claim 1, wherein an n-type impurity is introduced into an interface portion of the first nitride semiconductor layer with the second nitride semiconductor layer. 2. The field effect transistor according to claim 1, wherein a crystal orientation of the second nitride semiconductor layer does not generate a polarization electric field in a direction perpendicular to the substrate.   2. The field effect transistor according to claim 1, further comprising a silicon nitride film that covers at least a side surface of a junction between the second nitride semiconductor layer and the third nitride semiconductor layer.

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