WO2015037288A1 - High-electron-mobility transistor and method for manufacturing same - Google Patents

High-electron-mobility transistor and method for manufacturing same Download PDF

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WO2015037288A1
WO2015037288A1 PCT/JP2014/064774 JP2014064774W WO2015037288A1 WO 2015037288 A1 WO2015037288 A1 WO 2015037288A1 JP 2014064774 W JP2014064774 W JP 2014064774W WO 2015037288 A1 WO2015037288 A1 WO 2015037288A1
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layer
algan
inaln
mobility transistor
nitride semiconductor
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Japanese (ja)
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富田　英幹
将一 兼近
上田　博之
誠 桑原
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トヨタ自動車株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the technology disclosed in this specification relates to a high electron mobility transistor and a method for manufacturing the same.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2009-71061 discloses an example of a high electron mobility transistor.
  • a high electron mobility transistor disclosed in Patent Document 1 includes an AlGaN layer (electron supply layer) provided on an electron transit layer, an AlN layer (insulating layer) provided on the AlGaN layer, and an AlN layer. And a gate electrode provided via a nitride semiconductor layer.
  • an AlN layer is interposed to insulate an AlGaN layer and a nitride semiconductor layer. For this reason, after forming an AlN layer on an AlGaN layer, a nitride semiconductor layer must be formed on the AlN layer. However, when an AlN layer is formed on the AlGaN layer, the AlN layer may not be formed well. Therefore, it has been demanded to improve the quality of the high electron mobility transistor by forming a layer between the AlGaN layer and the nitride semiconductor layer well.
  • the high electron mobility transistor disclosed in this specification includes an electron transit layer, an AlGaN layer provided on the electron transit layer, and an insulating layer containing In and Al provided on the AlGaN layer. I have.
  • the high electron mobility transistor includes a nitride semiconductor layer provided on the insulating layer, a source electrode and a drain electrode provided on the AlGaN layer, and a gate electrode provided on the nitride semiconductor layer. And.
  • the AlGaN layer (electron supply layer) and the insulating layer containing In and Al can be brought into close contact with each other, and a high-quality high electron mobility transistor can be obtained. That is, in the conventional high electron mobility transistor of Patent Document 1, the “AlN” layer is used as an insulating layer that insulates the AlGaN layer (electron supply layer) and the nitride semiconductor layer. Therefore, the lattice constants of the electron supply layer and the insulating layer are greatly separated, and the insulating layer may not be formed on the electron supply layer with good quality.
  • the insulating layer is a layer containing In and Al
  • the lattice constants of the electron supply layer (AlGaN layer) and the insulating layer (layer containing In and Al) are used. Can be brought closer. Thereby, an insulating layer containing In and Al can be formed on the electron supply layer (AlGaN layer) with high quality, and a high quality high electron mobility transistor can be obtained.
  • the insulating layer may be formed of InAlN having a composition ratio of In 0.18 Al 0.82 N.
  • a method for manufacturing a high electron mobility transistor disclosed in the present specification includes a step of providing an AlGaN layer on an electron transit layer, and a step of providing an insulating layer containing In and Al on the AlGaN layer. I have.
  • the manufacturing method includes a step of providing a nitride semiconductor layer on the insulating layer, a step of providing a source electrode and a drain electrode on the AlGaN layer, a step of providing a gate electrode on the nitride semiconductor layer, It has.
  • the above manufacturing method may include a step of removing a part of the nitride semiconductor layer up to the insulating layer by an etching method before providing the gate electrode.
  • the high electron mobility transistor 1 includes an electron transit layer 103 supported on a substrate 101, an AlGaN layer 104 provided on the electron transit layer 103, and an AlGaN layer 104. And an InAlN layer 100 (an example of an insulating layer) provided by epitaxial growth.
  • the high electron mobility transistor 1 includes a nitride semiconductor layer 107 provided on the InAlN layer 100, a source electrode 109 and a drain electrode 110 provided on the AlGaN layer 104, and a nitride semiconductor layer 107. And a gate electrode 111 provided thereon.
  • the high electron mobility transistor 1 includes an interlayer insulating film 108.
  • the substrate 101 for example, a sapphire substrate or a silicon substrate can be used.
  • a buffer layer 102 is provided on the substrate 101.
  • As a material of the buffer layer 102 for example, AlN or GaN can be used.
  • An electron transit layer 103 is provided on the buffer layer 102.
  • the electron transit layer 103 becomes a channel through which electrons supplied from the electron supply layer 104 travel.
  • the electron transit layer 103 for example, an undoped GaN layer or an InGaN layer can be used.
  • the AlGaN layer 104 is an electron supply layer that supplies electrons to the electron transit layer 103.
  • the AlGaN layer 104 is not doped (undoped).
  • the AlGaN layer 104 (electron supply layer) and the electron transit layer 103 form a heterojunction, and a two-dimensional electron gas layer (2DEG) is formed on the heterojunction surface.
  • the composition ratio of AlGaN in the AlGaN layer 104 can be Al 1-x Ga x N (0.15 ⁇ x ⁇ 1.0).
  • the lattice constant of AlGaN is 3.12 to 3.189 ⁇ .
  • the AlGaN layer 104 has a larger band gap than the electron transit layer 103.
  • the InAlN layer 100 contains In and Al and is an insulating layer that insulates the AlGaN layer 104 and the nitride semiconductor layer 107.
  • the InAlN layer 100 is formed by epitaxial growth, and can be formed by, for example, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the composition ratio of InAlN in the InAlN layer 100 can be In 1-x Al x N (0.85 ⁇ x ⁇ 1.0). In the present embodiment, InAlN having a composition ratio of In 0.18 Al 0.82 N is used in the InAlN layer 100 (insulating layer).
  • the lattice constant of InAlN can completely match the lattice constant of the underlying AlGaN, and InAlN has a larger band gap. Therefore, a high-quality InAlN layer without lattice distortion can be formed, and device characteristics such as gate current suppression can be improved.
  • the lattice constant is 3.17 ⁇ , and lattice matching is possible with In 0.14 Al 0.86 N thereon.
  • the lattice constant of AlN used as an insulating layer in the semiconductor device of Patent Document 1 is about 3.11 mm.
  • a plurality of openings 121 for disposing the source electrode 109 and the drain electrode 110 are formed in the InAlN layer 100 so as to be separated from each other.
  • the source electrode 109 and the drain electrode 110 are disposed in the opening 121 and are provided apart from each other.
  • the source electrode 109 and the drain electrode 110 are in ohmic contact with the surface of the AlGaN layer 104.
  • the nitride semiconductor layer 107 includes a lower P-type GaN layer 105 provided on the InAlN layer 100 and an upper P-type GaN layer 106 provided on the lower P-type GaN layer 105.
  • the upper P-type GaN layer 106 contains a higher concentration of P-type impurities than the lower P-type GaN layer 105.
  • the nitride semiconductor layer 107 is disposed between the source electrode 109 and the drain electrode 110 when the high electron mobility transistor 1 is viewed in plan.
  • a gate electrode 111 is provided on the upper P-type GaN layer 106.
  • the nitride semiconductor layer 107 is disposed on a part of the InAlN layer 100, and the periphery thereof is covered with an interlayer insulating film 108.
  • the gate electrode 111 is in ohmic contact with the surface of the upper P-type GaN layer 106.
  • the gate voltage applied to the gate electrode 111 By controlling the gate voltage applied to the gate electrode 111, the two-dimensional electron gas concentration at the heterojunction interface between the underlying AlGaN layer 104 (electron supply layer) and the electron transit layer 103 increases or decreases, and the source electrode 109 and the drain The main current flowing between the electrodes 110 can be controlled.
  • the gate electrode 111 is provided above the InAlN layer 100 with the nitride semiconductor layer 107 interposed therebetween.
  • the interlayer insulating film 108 has an insulating property and is made of, for example, SiN.
  • the interlayer insulating film 108 covers the electron transit layer 103, the AlGaN layer 104, the InAlN layer 100, the lower P-type GaN layer 105, and the upper P-type GaN layer 106.
  • a plurality of openings 123 are formed in the interlayer insulating film 108, and a source electrode 109, a drain electrode 110, and a gate electrode 111 are arranged in each opening 123.
  • the manufacturing method of the high electron mobility transistor according to the embodiment includes a step of providing the AlGaN layer 104 on the electron transit layer 103 and a step of providing the InAlN layer 100 on the AlGaN layer 104 by epitaxial growth. Further, this manufacturing method includes a step of providing the nitride semiconductor layer 107 on the InAlN layer 100, a step of providing the source electrode 109 and the drain electrode 110 on the AlGaN layer 104, and a gate on the nitride semiconductor layer 107. A step of providing an electrode 111. In addition, this manufacturing method includes a step of removing a part of the nitride semiconductor layer 107 up to the InAlN layer 100 by an etching method before providing the gate electrode 111. This manufacturing method will be described in more detail below.
  • a substrate 101, a buffer layer 102, and an electron transit layer 103 are sequentially stacked, and AlGaN is formed on the electron transit layer 103.
  • Layer 104 is formed.
  • an InAlN layer 100 is formed on the AlGaN layer 104.
  • the AlGaN layer 104 and the InAlN layer 100 can be formed by an epitaxial growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the laminated layers by trimethylgallium (TMGa) and ammonia (NH 3) metal-organic vapor phase growth method using (MOCVD method).
  • the InAlN layer 100 having a close lattice constant is formed on the AlGaN layer 104, the InAlN layer 100 can be formed with high quality by epitaxial growth.
  • the thickness of the buffer layer 102 is 2.4 ⁇ m
  • the thickness of the electron transit layer 103 is 1.6 ⁇ m
  • the thickness of the AlGaN layer 104 is 20 nm
  • the thickness of the InAlN layer 100 is 1 nm.
  • the thickness of each layer is not particularly limited.
  • a nitride semiconductor layer 107 is provided on the InAlN layer 100.
  • the lower P-type GaN layer 105 is formed on the InAlN layer 100
  • the upper P-type GaN layer 106 is formed on the lower P-type GaN layer 105.
  • the lower P-type GaN layer 105 and the upper P-type GaN layer 106 can be formed by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the thickness of the lower P-type GaN layer 105 is 100 nm and the thickness of the upper P-type GaN layer 106 is 5 nm.
  • the thickness of each layer is not particularly limited.
  • the upper P-type GaN layer 106, the lower P-type GaN layer 105, the InAlN layer 100, the AlGaN layer 104, and the electron transit layer 103 are selectively removed by photolithography and vapor phase etching. To do. Specifically, the peripheral part of each layer is removed. The electron transit layer 103 is removed partway through the layer.
  • the nitride semiconductor layer 107 (the upper P-type GaN layer 106 and the lower P-type GaN layer 105) is selectively removed by photolithography and vapor phase etching. Specifically, a part (peripheral part) of the nitride semiconductor layer 107 is removed up to the InAlN layer 100. At this time, the presence of the insulating layer 100 prevents the lower AlGaN layer 104 from being etched.
  • an interlayer insulating film 108 is formed on the stacked body.
  • the interlayer insulating film 108 covers the upper P-type GaN layer 106, the lower P-type GaN layer 105, the InAlN layer 100, the AlGaN layer 104, and the electron transit layer 103.
  • the interlayer insulating film 108 can be formed by plasma CVD, for example.
  • a plurality of openings 121 are formed in the interlayer insulating film 108 and the InAlN layer 100 as shown in FIG.
  • the opening 121 can be formed by selectively removing the interlayer insulating film 108 and the InAlN layer 100 by, for example, photolithography and vapor phase etching.
  • the source electrode 109 and the drain electrode 110 are formed on the AlGaN layer 104 in the opening 121.
  • the source electrode 109 and the drain electrode 110 can be formed by plasma CVD, for example.
  • an opening 123 is formed in the interlayer insulating film 108 as shown in FIG.
  • the opening 123 can be formed by selectively removing the interlayer insulating film 108 by photolithography and vapor phase etching.
  • the gate electrode 111 is formed on the upper P-type GaN layer 106 in the opening 123 (see FIG. 1).
  • the gate electrode 111 can be formed by plasma CVD, for example.
  • the InAlN layer 100 (insulating layer) is formed on the surface of the AlGaN layer 104 (electron supply layer) by epitaxial growth. Therefore, the AlGaN layer 104 and the InAlN layer 100 can be brought into close contact with each other, and a high-quality high electron mobility transistor 1 can be obtained. That is, since the lattice constants of the electron supply layer (AlGaN layer 104) and the insulating layer (InAlN layer 100) are close to each other, the InAlN layer 100 can be formed on the AlGaN layer 104 with high quality by epitaxial growth, and a high-quality high-electron mobility transistor.
  • AlN layer 104 the lattice constants of the electron supply layer (AlGaN layer 104) and the insulating layer (InAlN layer 100) are close to each other, the AlN layer can be manufactured with less stress on the interface than when the AlN layer is used as the insulating layer. This is effective in reducing current collapse, which is the biggest problem in GaN-HEMT. Thereby, it becomes possible to ensure high reliability.
  • the InAlN layer 100 becomes an etching stop layer, so that the AlGaN layer 104 under the InAlN layer 100 is not etched.
  • the gate current can be suppressed even if the voltage applied by the gate electrode 111 is increased.
  • the InAlN layer 100 on the surface of the AlGaN layer 104, positive charges can be collected at the interface between the InAlN layer 100 and the AlGaN layer 104 by piezoelectric polarization.
  • the two-dimensional electron gas (2DEG) formed at the interface between the electron transit layer 103 and the AlGaN layer 104 can be increased, and the on-resistance can be reduced.
  • the critical film thickness of the insulating layer (InAlN layer 100) is made AlN. It can be thicker than the layer.
  • the present invention is not limited to this configuration, and an InAlGaN layer may be used as the insulating layer.
  • high electron mobility transistor 100 InAlN layer (insulating layer) 101; substrate 102; buffer layer 103; electron transit layer 104; AlGaN layer (electron supply layer) 105; lower P-type GaN layer 106; upper P-type GaN layer 107; nitride semiconductor layer 108; interlayer insulating film 109; source electrode 110; drain electrode 111; gate electrode 121;

Abstract

This high-electron-mobility transistor (1) is provided with: an AlGaN layer (104) arranged on an electron transit layer (103); an InAlN layer (100) arranged on the AlGaN layer (104); a nitride semiconductor layer (107) arranged on the InAlN layer (100); a source electrode (109) and a drain electrode (110) arranged on the AlGaN layer (104); and a gate electrode (111) arranged on the nitride semiconductor layer (107).

Description

高電子移動度トランジスタ及びその製造方法High electron mobility transistor and manufacturing method thereof
　本明細書に開示の技術は、高電子移動度トランジスタ及びその製造方法に関する。 The technology disclosed in this specification relates to a high electron mobility transistor and a method for manufacturing the same.
　従来から電界効果トランジスタの一つとして、化合物半導体材料を利用した高電子移動度トランジスタ（ＨＥＭＴ：High Electron Mobility Transistor）が知られている。この高電子移動度トランジスタは、ヘテロ接合に起因した高移動度の二次元電子ガス（２ＤＥＧ）をチャネルとしている。特許文献１（日本国特開２００９－７１０６１号公報）には高電子移動度トランジスタの一例が開示されている。特許文献１に開示の高電子移動度トランジスタは、電子走行層の上に設けられたＡｌＧａＮ層（電子供給層）と、ＡｌＧａＮ層の上に設けられたＡｌＮ層（絶縁層）と、ＡｌＮ層の上に窒化物半導体層を介して設けられたゲート電極とを備えている。 Conventionally, as one of the field effect transistors, a high electron mobility transistor (HEMT) using a compound semiconductor material is known. This high electron mobility transistor uses a high mobility two-dimensional electron gas (2DEG) caused by a heterojunction as a channel. Patent Document 1 (Japanese Unexamined Patent Publication No. 2009-71061) discloses an example of a high electron mobility transistor. A high electron mobility transistor disclosed in Patent Document 1 includes an AlGaN layer (electron supply layer) provided on an electron transit layer, an AlN layer (insulating layer) provided on the AlGaN layer, and an AlN layer. And a gate electrode provided via a nitride semiconductor layer.
　特許文献１に開示された高電子移動度トランジスタでは、ＡｌＮ層を介在させることによりＡｌＧａＮ層と窒化物半導体層との間を絶縁している。このため、ＡｌＧａＮ層の上にＡｌＮ層を形成した後に、そのＡｌＮ層上に窒化物半導体層を形成しなければならない。しかしながら、ＡｌＧａＮ層の上にＡｌＮ層を形成しようとすると、ＡｌＮ層が良好に形成されないことがあった。そのため、ＡｌＧａＮ層と窒化物半導体層との間の層を良好に形成して高電子移動度トランジスタの品質を高めることが要求されていた。 In the high electron mobility transistor disclosed in Patent Document 1, an AlN layer is interposed to insulate an AlGaN layer and a nitride semiconductor layer. For this reason, after forming an AlN layer on an AlGaN layer, a nitride semiconductor layer must be formed on the AlN layer. However, when an AlN layer is formed on the AlGaN layer, the AlN layer may not be formed well. Therefore, it has been demanded to improve the quality of the high electron mobility transistor by forming a layer between the AlGaN layer and the nitride semiconductor layer well.
　そこで本明細書は、高品質の高電子移動度トランジスタを得ることができる技術を提供することを目的とする。 Therefore, it is an object of the present specification to provide a technique capable of obtaining a high quality high electron mobility transistor.
　本明細書に開示する高電子移動度トランジスタは、電子走行層と、電子走行層の上に設けられたＡｌＧａＮ層と、ＡｌＧａＮ層の上に設けられたＩｎ及びＡｌを含有する絶縁層と、を備えている。また、高電子移動度トランジスタは、絶縁層の上に設けられた窒化物半導体層と、ＡｌＧａＮ層の上に設けられたソース電極及びドレイン電極と、窒化物半導体層の上に設けられたゲート電極と、を備えている。 The high electron mobility transistor disclosed in this specification includes an electron transit layer, an AlGaN layer provided on the electron transit layer, and an insulating layer containing In and Al provided on the AlGaN layer. I have. The high electron mobility transistor includes a nitride semiconductor layer provided on the insulating layer, a source electrode and a drain electrode provided on the AlGaN layer, and a gate electrode provided on the nitride semiconductor layer. And.
　このような構成によれば、ＡｌＧａＮ層（電子供給層）とＩｎ及びＡｌを含有する絶縁層とを密着させることができ、高品質の高電子移動度トランジスタを得ることができる。すなわち、上記従来の特許文献１の高電子移動度トランジスタでは、ＡｌＧａＮ層（電子供給層）と窒化物半導体層を絶縁する絶縁層に「ＡｌＮ」層を用いている。そのため、電子供給層と絶縁層の格子定数が大きく離れ、電子供給層上に絶縁層を品質良く形成できないことがある。これに対して本明細書に開示の技術では、絶縁層をＩｎ及びＡｌを含有する層にしているので、電子供給層（ＡｌＧａＮ層）と絶縁層（Ｉｎ及びＡｌを含有する層）の格子定数を近づけることができる。これにより、Ｉｎ及びＡｌを含有する絶縁層を電子供給層（ＡｌＧａＮ層）の上に高品質に形成でき、高品質の高電子移動度トランジスタを得ることができる。 According to such a configuration, the AlGaN layer (electron supply layer) and the insulating layer containing In and Al can be brought into close contact with each other, and a high-quality high electron mobility transistor can be obtained. That is, in the conventional high electron mobility transistor of Patent Document 1, the “AlN” layer is used as an insulating layer that insulates the AlGaN layer (electron supply layer) and the nitride semiconductor layer. Therefore, the lattice constants of the electron supply layer and the insulating layer are greatly separated, and the insulating layer may not be formed on the electron supply layer with good quality. On the other hand, in the technique disclosed in this specification, since the insulating layer is a layer containing In and Al, the lattice constants of the electron supply layer (AlGaN layer) and the insulating layer (layer containing In and Al) are used. Can be brought closer. Thereby, an insulating layer containing In and Al can be formed on the electron supply layer (AlGaN layer) with high quality, and a high quality high electron mobility transistor can be obtained.
　上記高電子移動度トランジスタにおいて、絶縁層は、組成比がＩｎ０．１８Ａｌ０．８２ＮのＩｎＡｌＮから形成されていてもよい。
　また、本明細書に開示する高電子移動度トランジスタの製造方法は、電子走行層の上にＡｌＧａＮ層を設ける工程と、ＡｌＧａＮ層の上にＩｎ及びＡｌを含有する絶縁層を設ける工程と、を備えている。また、この製造方法は、絶縁層の上に窒化物半導体層を設ける工程と、ＡｌＧａＮ層の上にソース電極及びドレイン電極を設ける工程と、窒化物半導体層の上にゲート電極を設ける工程と、を備えている。 In the high electron mobility transistor, the insulating layer may be formed of InAlN having a composition ratio of In 0.18 Al 0.82 N.
Further, a method for manufacturing a high electron mobility transistor disclosed in the present specification includes a step of providing an AlGaN layer on an electron transit layer, and a step of providing an insulating layer containing In and Al on the AlGaN layer. I have. The manufacturing method includes a step of providing a nitride semiconductor layer on the insulating layer, a step of providing a source electrode and a drain electrode on the AlGaN layer, a step of providing a gate electrode on the nitride semiconductor layer, It has.
　上記の製造方法では、ゲート電極を設ける前に、窒化物半導体層の一部をエッチング法により絶縁層まで除去する工程を含むことができる。 The above manufacturing method may include a step of removing a part of the nitride semiconductor layer up to the insulating layer by an etching method before providing the gate electrode.
高電子移動度トランジスタの断面図である。It is sectional drawing of a high electron mobility transistor. 高電子移動度トランジスタの製造方法を説明する図である（１）。It is a figure explaining the manufacturing method of a high electron mobility transistor (1). 高電子移動度トランジスタの製造方法を説明する図である（２）。It is a figure explaining the manufacturing method of a high electron mobility transistor (2). 高電子移動度トランジスタの製造方法を説明する図である（３）。It is a figure explaining the manufacturing method of a high electron mobility transistor (3). 高電子移動度トランジスタの製造方法を説明する図である（４）。It is a figure explaining the manufacturing method of a high electron mobility transistor (4). 高電子移動度トランジスタの製造方法を説明する図である（５）。It is a figure explaining the manufacturing method of a high electron mobility transistor (5). 高電子移動度トランジスタの製造方法を説明する図である（６）。It is a figure explaining the manufacturing method of a high electron mobility transistor (6). 高電子移動度トランジスタの製造方法を説明する図である（７）。It is a figure explaining the manufacturing method of a high electron mobility transistor (7). 高電子移動度トランジスタの製造方法を説明する図である（８）。It is a figure explaining the manufacturing method of a high electron mobility transistor (8).
　以下、実施形態について添付図面を参照して説明する。実施形態に係る高電子移動度トランジスタ１は、図１に示すように、基板１０１に支持された電子走行層１０３と、電子走行層１０３の上に設けられたＡｌＧａＮ層１０４と、ＡｌＧａＮ層１０４の上にエピタキシャル成長により設けられたＩｎＡｌＮ層１００（絶縁層の一例）とを備えている。また、高電子移動度トランジスタ１は、ＩｎＡｌＮ層１００の上に設けられた窒化物半導体層１０７と、ＡｌＧａＮ層１０４の上に設けられたソース電極１０９及びドレイン電極１１０と、窒化物半導体層１０７の上に設けられたゲート電極１１１とを備えている。また、高電子移動度トランジスタ１は層間絶縁膜１０８を有している。 Hereinafter, embodiments will be described with reference to the accompanying drawings. As shown in FIG. 1, the high electron mobility transistor 1 according to the embodiment includes an electron transit layer 103 supported on a substrate 101, an AlGaN layer 104 provided on the electron transit layer 103, and an AlGaN layer 104. And an InAlN layer 100 (an example of an insulating layer) provided by epitaxial growth. The high electron mobility transistor 1 includes a nitride semiconductor layer 107 provided on the InAlN layer 100, a source electrode 109 and a drain electrode 110 provided on the AlGaN layer 104, and a nitride semiconductor layer 107. And a gate electrode 111 provided thereon. The high electron mobility transistor 1 includes an interlayer insulating film 108.
　基板１０１としては、例えばサファイア基板やシリコン基板を用いることができる。基板１０１の上にはバッファ層１０２が設けられている。バッファ層１０２の材質としては、例えばＡｌＮやＧａＮを用いることができる。バッファ層１０２の上には電子走行層１０３が設けられている。 As the substrate 101, for example, a sapphire substrate or a silicon substrate can be used. A buffer layer 102 is provided on the substrate 101. As a material of the buffer layer 102, for example, AlN or GaN can be used. An electron transit layer 103 is provided on the buffer layer 102.
　電子走行層１０３は、電子供給層１０４から供給された電子が走行するチャネルになる。電子走行層１０３としては、例えばアンドープのＧａＮ層やＩｎＧａＮ層を用いることができる。 The electron transit layer 103 becomes a channel through which electrons supplied from the electron supply layer 104 travel. As the electron transit layer 103, for example, an undoped GaN layer or an InGaN layer can be used.
　ＡｌＧａＮ層１０４は、電子走行層１０３に電子を供給する電子供給層である。また、ＡｌＧａＮ層１０４は、ドープされていない（アンドープである）。ＡｌＧａＮ層１０４（電子供給層）と電子走行層１０３は、ヘテロ接合を構成しており、そのヘテロ接合面に２次元電子ガス層（２ＤＥＧ）が形成される。ＡｌＧａＮ層１０４におけるＡｌＧａＮの組成比は、Ａｌ１－ｘＧａｘＮ（０．１５≦ｘ＜１．０）とすることができる。ＡｌＧａＮの格子定数は３．１２～３．１８９Åである。また、ＡｌＧａＮ層１０４は電子走行層１０３よりもバンドギャップが大きい。 The AlGaN layer 104 is an electron supply layer that supplies electrons to the electron transit layer 103. The AlGaN layer 104 is not doped (undoped). The AlGaN layer 104 (electron supply layer) and the electron transit layer 103 form a heterojunction, and a two-dimensional electron gas layer (2DEG) is formed on the heterojunction surface. The composition ratio of AlGaN in the AlGaN layer 104 can be Al 1-x Ga x N (0.15 ≦ x <1.0). The lattice constant of AlGaN is 3.12 to 3.189Å. The AlGaN layer 104 has a larger band gap than the electron transit layer 103.
　ＩｎＡｌＮ層１００は、Ｉｎ及びＡｌを含有しており、ＡｌＧａＮ層１０４と窒化物半導体層１０７とを絶縁する絶縁層である。ＩｎＡｌＮ層１００はエピタキシャル成長により形成されており、例えば、有機金属気相成長法（ＭＯＣＶＤ：metal organic chemical vapor deposition）、あるいは分子線エピタキシー法（ＭＢＥ：molecular beam epitaxy）などにより形成できる。ＩｎＡｌＮ層１００におけるＩｎＡｌＮの組成比は、Ｉｎ１－ｘＡｌｘＮ（０．８５≦ｘ＜１．０）とすることができる。本実施形態では、ＩｎＡｌＮ層１００（絶縁層）において、組成比がＩｎ０．１８Ａｌ０．８２ＮのＩｎＡｌＮを用いている。ＩｎＡｌＮの格子定数は下地のＡｌＧａＮと格子定数と完全に一致することが可能で、しかもＩｎＡｌＮのほうがバンドギャップが大きい。そのため、格子歪のない高品質なＩｎＡｌＮ層を形成でき、ゲート電流抑制などデバイス特性の向上が可能である。例えば、下地がＡｌ０．２Ｇａ０．８Ｎのときの格子定数が３．１７Åであり、その上にＩｎ０．１４Ａｌ０．８６Ｎにより格子整合が可能である。なお、特許文献１の半導体装置において絶縁層として用いられているＡｌＮの格子定数は約３．１１Åである。 The InAlN layer 100 contains In and Al and is an insulating layer that insulates the AlGaN layer 104 and the nitride semiconductor layer 107. The InAlN layer 100 is formed by epitaxial growth, and can be formed by, for example, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The composition ratio of InAlN in the InAlN layer 100 can be In 1-x Al x N (0.85 ≦ x <1.0). In the present embodiment, InAlN having a composition ratio of In 0.18 Al 0.82 N is used in the InAlN layer 100 (insulating layer). The lattice constant of InAlN can completely match the lattice constant of the underlying AlGaN, and InAlN has a larger band gap. Therefore, a high-quality InAlN layer without lattice distortion can be formed, and device characteristics such as gate current suppression can be improved. For example, when the base is Al 0.2 Ga 0.8 N, the lattice constant is 3.17 Å, and lattice matching is possible with In 0.14 Al 0.86 N thereon. Note that the lattice constant of AlN used as an insulating layer in the semiconductor device of Patent Document 1 is about 3.11 mm.
　また、ＩｎＡｌＮ層１００にはソース電極１０９及びドレイン電極１１０をそれぞれ配置するための複数の開口１２１が離間して形成されている。ソース電極１０９及びドレイン電極１１０は、開口１２１内にそれぞれ配置され、互いに離間して設けられている。ソース電極１０９及びドレイン電極１１０は、ＡｌＧａＮ層１０４の表面にオーミック接触している。 In addition, a plurality of openings 121 for disposing the source electrode 109 and the drain electrode 110 are formed in the InAlN layer 100 so as to be separated from each other. The source electrode 109 and the drain electrode 110 are disposed in the opening 121 and are provided apart from each other. The source electrode 109 and the drain electrode 110 are in ohmic contact with the surface of the AlGaN layer 104.
　窒化物半導体層１０７は、ＩｎＡｌＮ層１００の上に設けられた下部Ｐ型ＧａＮ層１０５と、下部Ｐ型ＧａＮ層１０５の上に設けられた上部Ｐ型ＧａＮ層１０６とを備えている。上部Ｐ型ＧａＮ層１０６は下部Ｐ型ＧａＮ層１０５よりも高濃度のＰ型不純物を含んでいる。窒化物半導体層１０７は、高電子移動度トランジスタ１を平面視したときに、ソース電極１０９とドレイン電極１１０の間に配置されている。上部Ｐ型ＧａＮ層１０６の上にはゲート電極１１１が設けられている。窒化物半導体層１０７は、ＩｎＡｌＮ層１００上の一部に配置されており、その周囲は層間絶縁膜１０８により覆われている。 The nitride semiconductor layer 107 includes a lower P-type GaN layer 105 provided on the InAlN layer 100 and an upper P-type GaN layer 106 provided on the lower P-type GaN layer 105. The upper P-type GaN layer 106 contains a higher concentration of P-type impurities than the lower P-type GaN layer 105. The nitride semiconductor layer 107 is disposed between the source electrode 109 and the drain electrode 110 when the high electron mobility transistor 1 is viewed in plan. A gate electrode 111 is provided on the upper P-type GaN layer 106. The nitride semiconductor layer 107 is disposed on a part of the InAlN layer 100, and the periphery thereof is covered with an interlayer insulating film 108.
　ゲート電極１１１は上部Ｐ型ＧａＮ層１０６の表面にオーミック接触している。ゲート電極１１１に印加するゲート電圧を制御することで、その下のＡｌＧａＮ層１０４（電子供給層）と電子走行層１０３とのヘテロ接合界面における二次元電子ガス濃度が増減し、ソース電極１０９とドレイン電極１１０の間に流れる主電流を制御できる。ゲート電極１１１は、窒化物半導体層１０７を介してＩｎＡｌＮ層１００の上方に設けられている。 The gate electrode 111 is in ohmic contact with the surface of the upper P-type GaN layer 106. By controlling the gate voltage applied to the gate electrode 111, the two-dimensional electron gas concentration at the heterojunction interface between the underlying AlGaN layer 104 (electron supply layer) and the electron transit layer 103 increases or decreases, and the source electrode 109 and the drain The main current flowing between the electrodes 110 can be controlled. The gate electrode 111 is provided above the InAlN layer 100 with the nitride semiconductor layer 107 interposed therebetween.
　層間絶縁膜１０８は、絶縁性を有しており、例えばＳｉＮにより形成されている。また、層間絶縁膜１０８は、電子走行層１０３、ＡｌＧａＮ層１０４、ＩｎＡｌＮ層１００、下部Ｐ型ＧａＮ層１０５及び上部Ｐ型ＧａＮ層１０６を覆っている。層間絶縁膜１０８には、複数の開口１２３が形成されており、各開口１２３にソース電極１０９、ドレイン電極１１０、ゲート電極１１１がそれぞれ配置されている。 The interlayer insulating film 108 has an insulating property and is made of, for example, SiN. The interlayer insulating film 108 covers the electron transit layer 103, the AlGaN layer 104, the InAlN layer 100, the lower P-type GaN layer 105, and the upper P-type GaN layer 106. A plurality of openings 123 are formed in the interlayer insulating film 108, and a source electrode 109, a drain electrode 110, and a gate electrode 111 are arranged in each opening 123.
　次に、上記のような高電子移動度トランジスタの製造方法について説明する。実施形態に係る高電子移動度トランジスタの製造方法は、電子走行層１０３の上にＡｌＧａＮ層１０４を設ける工程と、ＡｌＧａＮ層１０４の上にエピタキシャル成長によりＩｎＡｌＮ層１００を設ける工程とを備えている。また、この製造方法は、ＩｎＡｌＮ層１００の上に窒化物半導体層１０７を設ける工程と、ＡｌＧａＮ層１０４の上にソース電極１０９及びドレイン電極１１０を設ける工程と、窒化物半導体層１０７の上にゲート電極１１１を設ける工程とを備えている。また、この製造方法は、ゲート電極１１１を設ける前に、窒化物半導体層１０７の一部をエッチング法によりＩｎＡｌＮ層１００まで除去する工程を備えている。この製造方法について以下により詳細に説明してゆく。 Next, a method for manufacturing the high electron mobility transistor as described above will be described. The manufacturing method of the high electron mobility transistor according to the embodiment includes a step of providing the AlGaN layer 104 on the electron transit layer 103 and a step of providing the InAlN layer 100 on the AlGaN layer 104 by epitaxial growth. Further, this manufacturing method includes a step of providing the nitride semiconductor layer 107 on the InAlN layer 100, a step of providing the source electrode 109 and the drain electrode 110 on the AlGaN layer 104, and a gate on the nitride semiconductor layer 107. A step of providing an electrode 111. In addition, this manufacturing method includes a step of removing a part of the nitride semiconductor layer 107 up to the InAlN layer 100 by an etching method before providing the gate electrode 111. This manufacturing method will be described in more detail below.
　実施形態に係る高電子移動度トランジスタの製造方法では、まず図２示すように、基板１０１、バッファ層１０２、および電子走行層１０３を順次積層したものを準備し、電子走行層１０３の上にＡｌＧａＮ層１０４を形成する。続いて、ＡｌＧａＮ層１０４の上にＩｎＡｌＮ層１００を形成する。ＡｌＧａＮ層１０４およびＩｎＡｌＮ層１００は、有機金属気相成長法（ＭＯＣＶＤ）や分子線エピタキシー法（ＭＢＥ）などのエピタキシャル成長法により形成できる。本実施形態では、トリメチルガリウム（ＴＭＧａ）およびアンモニア（ＮＨ３）を用いた有機金属気相成長法（ＭＯＣＶＤ法）により各層を積層した。ＡｌＧａＮ層１０４の上に格子定数が近いＩｎＡｌＮ層１００を形成するので、エピタキシャル成長によりＩｎＡｌＮ層１００を品質良く形成できる。本実施形態では、バッファ層１０２の厚さを２．４μｍとし、電子走行層１０３の厚さを１．６μｍとし、ＡｌＧａＮ層１０４の厚さを２０ｎｍとし、ＩｎＡｌＮ層１００の厚さを１ｎｍとしたが、各層の厚さは特に限定されるものではない。 In the method of manufacturing a high electron mobility transistor according to the embodiment, first, as shown in FIG. 2, a substrate 101, a buffer layer 102, and an electron transit layer 103 are sequentially stacked, and AlGaN is formed on the electron transit layer 103. Layer 104 is formed. Subsequently, an InAlN layer 100 is formed on the AlGaN layer 104. The AlGaN layer 104 and the InAlN layer 100 can be formed by an epitaxial growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In this embodiment, the laminated layers by trimethylgallium (TMGa) and ammonia (NH 3) metal-organic vapor phase growth method using (MOCVD method). Since the InAlN layer 100 having a close lattice constant is formed on the AlGaN layer 104, the InAlN layer 100 can be formed with high quality by epitaxial growth. In the present embodiment, the thickness of the buffer layer 102 is 2.4 μm, the thickness of the electron transit layer 103 is 1.6 μm, the thickness of the AlGaN layer 104 is 20 nm, and the thickness of the InAlN layer 100 is 1 nm. However, the thickness of each layer is not particularly limited.
　次に、図３に示すように、ＩｎＡｌＮ層１００の上に窒化物半導体層１０７を設ける。具体的には、ＩｎＡｌＮ層１００の上に下部Ｐ型ＧａＮ層１０５を形成し、下部Ｐ型ＧａＮ層１０５の上に上部Ｐ型ＧａＮ層１０６を形成する。下部Ｐ型ＧａＮ層１０５および上部Ｐ型ＧａＮ層１０６の形成は、有機金属気相成長法（ＭＯＣＶＤ）や分子線エピタキシー法（ＭＢＥ）により行うことができる。本実施形態では、下部Ｐ型ＧａＮ層１０５の厚さを１００ｎｍとし、上部Ｐ型ＧａＮ層１０６の厚さを５ｎｍとしたが、各層の厚さは特に限定されるものではない。 Next, as shown in FIG. 3, a nitride semiconductor layer 107 is provided on the InAlN layer 100. Specifically, the lower P-type GaN layer 105 is formed on the InAlN layer 100, and the upper P-type GaN layer 106 is formed on the lower P-type GaN layer 105. The lower P-type GaN layer 105 and the upper P-type GaN layer 106 can be formed by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In the present embodiment, the thickness of the lower P-type GaN layer 105 is 100 nm and the thickness of the upper P-type GaN layer 106 is 5 nm. However, the thickness of each layer is not particularly limited.
　次に、図４示すように、フォトリソグラフィーおよび気相エッチング法により、上部Ｐ型ＧａＮ層１０６、下部Ｐ型ＧａＮ層１０５、ＩｎＡｌＮ層１００、ＡｌＧａＮ層１０４、および電子走行層１０３を選択的に除去する。具体的には、各層の周縁部を除去する。また、電子走行層１０３は層の途中まで除去する。 Next, as shown in FIG. 4, the upper P-type GaN layer 106, the lower P-type GaN layer 105, the InAlN layer 100, the AlGaN layer 104, and the electron transit layer 103 are selectively removed by photolithography and vapor phase etching. To do. Specifically, the peripheral part of each layer is removed. The electron transit layer 103 is removed partway through the layer.
　次に、図５示すように、フォトリソグラフィーおよび気相エッチング法により、窒化物半導体層１０７（上部Ｐ型ＧａＮ層１０６および下部Ｐ型ＧａＮ層１０５）を選択的に除去する。具体的には、窒化物半導体層１０７の一部（周縁部）をＩｎＡｌＮ層１００まで除去する。このとき、絶縁層１００の存在により、それより下層のＡｌＧａＮ層１０４がエッチングされることを防いでいる。 Next, as shown in FIG. 5, the nitride semiconductor layer 107 (the upper P-type GaN layer 106 and the lower P-type GaN layer 105) is selectively removed by photolithography and vapor phase etching. Specifically, a part (peripheral part) of the nitride semiconductor layer 107 is removed up to the InAlN layer 100. At this time, the presence of the insulating layer 100 prevents the lower AlGaN layer 104 from being etched.
　次に、図６に示すように、積層体の上に層間絶縁膜１０８を形成する。層間絶縁膜１０８により、上部Ｐ型ＧａＮ層１０６、下部Ｐ型ＧａＮ層１０５、ＩｎＡｌＮ層１００、ＡｌＧａＮ層１０４および電子走行層１０３が覆われる。層間絶縁膜１０８の形成は例えばプラズマＣＶＤにより行うことができる。 Next, as shown in FIG. 6, an interlayer insulating film 108 is formed on the stacked body. The interlayer insulating film 108 covers the upper P-type GaN layer 106, the lower P-type GaN layer 105, the InAlN layer 100, the AlGaN layer 104, and the electron transit layer 103. The interlayer insulating film 108 can be formed by plasma CVD, for example.
　次に、ソース電極１０９及びドレイン電極１１０を配置するために、図７に示すように、層間絶縁膜１０８及びＩｎＡｌＮ層１００に複数の開口１２１を形成する。開口１２１の形成は、例えばフォトリソグラフィーおよび気相エッチングにより、層間絶縁膜１０８及びＩｎＡｌＮ層１００を選択的に除去することにより行うことができる。続いて、図８に示すように、開口１２１においてＡｌＧａＮ層１０４の上にソース電極１０９及びドレイン電極１１０を形成する。ソース電極１０９及びドレイン電極１１０の形成は例えばプラズマＣＶＤにより行うことができる。 Next, in order to dispose the source electrode 109 and the drain electrode 110, a plurality of openings 121 are formed in the interlayer insulating film 108 and the InAlN layer 100 as shown in FIG. The opening 121 can be formed by selectively removing the interlayer insulating film 108 and the InAlN layer 100 by, for example, photolithography and vapor phase etching. Subsequently, as shown in FIG. 8, the source electrode 109 and the drain electrode 110 are formed on the AlGaN layer 104 in the opening 121. The source electrode 109 and the drain electrode 110 can be formed by plasma CVD, for example.
　次に、ゲート電極１１１を配置するために、図９に示すように、層間絶縁膜１０８に開口１２３を形成する。開口１２３の形成は、フォトリソグラフィーおよび気相エッチングにより、層間絶縁膜１０８を選択的に除去することにより行うことができる。続いて、開口１２３において上部Ｐ型ＧａＮ層１０６の上にゲート電極１１１を形成する（図１参照）。ゲート電極１１１の形成は例えばプラズマＣＶＤにより行うことができる。 Next, in order to arrange the gate electrode 111, an opening 123 is formed in the interlayer insulating film 108 as shown in FIG. The opening 123 can be formed by selectively removing the interlayer insulating film 108 by photolithography and vapor phase etching. Subsequently, the gate electrode 111 is formed on the upper P-type GaN layer 106 in the opening 123 (see FIG. 1). The gate electrode 111 can be formed by plasma CVD, for example.
　上述の説明から明らかなように、本明細書に開示の高電子移動度トランジスタ１では、ＡｌＧａＮ層１０４（電子供給層）の表面にエピタキシャル成長によりＩｎＡｌＮ層１００（絶縁層）を形成している。そのため、ＡｌＧａＮ層１０４とＩｎＡｌＮ層１００とを密着させることができ、高品質の高電子移動度トランジスタ１を得ることができる。すなわち、電子供給層（ＡｌＧａＮ層１０４）と絶縁層（ＩｎＡｌＮ層１００）の格子定数が近いため、ＡｌＧａＮ層１０４上にＩｎＡｌＮ層１００をエピタキシャル成長により高品質に形成でき、高品質の高電子移動度トランジスタ１を得ることができる。また、電子供給層（ＡｌＧａＮ層１０４）と絶縁層（ＩｎＡｌＮ層１００）の格子定数が近いことは、ＡｌＮ層を絶縁層として使用するよりも界面へのストレスを与えることなく製造することができるため、ＧａＮ－ＨＥＭＴにおいて最大の課題である、電流コラプスを低減することに効果を発揮する。これにより、高信頼性を確保することが可能となる。 As is clear from the above description, in the high electron mobility transistor 1 disclosed in this specification, the InAlN layer 100 (insulating layer) is formed on the surface of the AlGaN layer 104 (electron supply layer) by epitaxial growth. Therefore, the AlGaN layer 104 and the InAlN layer 100 can be brought into close contact with each other, and a high-quality high electron mobility transistor 1 can be obtained. That is, since the lattice constants of the electron supply layer (AlGaN layer 104) and the insulating layer (InAlN layer 100) are close to each other, the InAlN layer 100 can be formed on the AlGaN layer 104 with high quality by epitaxial growth, and a high-quality high-electron mobility transistor. 1 can be obtained. In addition, since the lattice constants of the electron supply layer (AlGaN layer 104) and the insulating layer (InAlN layer 100) are close to each other, the AlN layer can be manufactured with less stress on the interface than when the AlN layer is used as the insulating layer. This is effective in reducing current collapse, which is the biggest problem in GaN-HEMT. Thereby, it becomes possible to ensure high reliability.
　また、窒化物半導体層１０７をエッチングする際に、ＩｎＡｌＮ層１００がエッチングストップ層となるので、ＩｎＡｌＮ層１００の下層のＡｌＧａＮ層１０４をエッチングしてしまうことがない。また、下部Ｐ型ＧａＮ層１０５とＡｌＧａＮ層１０４の間にバンドギャップが大きいＩｎＡｌＮ層１００が介在するので、ゲート電極１１１による印加電圧を大きくしたとしてもゲート電流を抑制することができる。また、ＡｌＧａＮ層１０４の表面にＩｎＡｌＮ層１００を形成することにより、ピエゾ分極によってＩｎＡｌＮ層１００とＡｌＧａＮ層１０４との界面に正の電荷を集めることができる。その結果、電子走行層１０３とＡｌＧａＮ層１０４との界面に形成される二次元電子ガス（２ＤＥＧ）を増加することができ、オン抵抗を低下させることができる。ＡｌＮ層を絶縁層として使用するよりも電子供給層（ＡｌＧａＮ層１０４）と絶縁層（ＩｎＡｌＮ層１００）の格子定数が近いことを利用して、絶縁層（ＩｎＡｌＮ層１００）の臨界膜厚をＡｌＮ層より厚くすることができる。 In addition, when the nitride semiconductor layer 107 is etched, the InAlN layer 100 becomes an etching stop layer, so that the AlGaN layer 104 under the InAlN layer 100 is not etched. In addition, since the InAlN layer 100 having a large band gap is interposed between the lower P-type GaN layer 105 and the AlGaN layer 104, the gate current can be suppressed even if the voltage applied by the gate electrode 111 is increased. Further, by forming the InAlN layer 100 on the surface of the AlGaN layer 104, positive charges can be collected at the interface between the InAlN layer 100 and the AlGaN layer 104 by piezoelectric polarization. As a result, the two-dimensional electron gas (2DEG) formed at the interface between the electron transit layer 103 and the AlGaN layer 104 can be increased, and the on-resistance can be reduced. Taking advantage of the fact that the lattice constants of the electron supply layer (AlGaN layer 104) and the insulating layer (InAlN layer 100) are closer than using the AlN layer as an insulating layer, the critical film thickness of the insulating layer (InAlN layer 100) is made AlN. It can be thicker than the layer.
　以上、一実施形態について説明したが、具体的な態様は上記実施形態に限定されるものではない。例えば、上記実施形態では絶縁層としてＩｎＡｌＮ層を用いてしたが、この構成に限定されるものではなく、絶縁層としてＩｎＡｌＧａＮ層を用いてもよい。 As mentioned above, although one embodiment was described, a specific mode is not limited to the above-mentioned embodiment. For example, although the InAlN layer is used as the insulating layer in the above embodiment, the present invention is not limited to this configuration, and an InAlGaN layer may be used as the insulating layer.
　以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.
１；高電子移動度トランジスタ
１００；ＩｎＡｌＮ層（絶縁層）
１０１；基板
１０２；バッファ層
１０３；電子走行層
１０４；ＡｌＧａＮ層（電子供給層）
１０５；下部Ｐ型ＧａＮ層
１０６；上部Ｐ型ＧａＮ層
１０７；窒化物半導体層
１０８；層間絶縁膜
１０９；ソース電極
１１０；ドレイン電極
１１１；ゲート電極
１２１；開口
１２３；開口 1; high electron mobility transistor 100; InAlN layer (insulating layer)
101; substrate 102; buffer layer 103; electron transit layer 104; AlGaN layer (electron supply layer)
105; lower P-type GaN layer 106; upper P-type GaN layer 107; nitride semiconductor layer 108; interlayer insulating film 109; source electrode 110; drain electrode 111; gate electrode 121;

Claims (4)

  1. 　電子走行層と、
    　電子走行層の上に設けられたＡｌＧａＮ層と、
    　ＡｌＧａＮ層の上に設けられたＩｎ及びＡｌを含有する絶縁層と、
    　絶縁層の上に設けられた窒化物半導体層と、
    　ＡｌＧａＮ層の上に設けられたソース電極及びドレイン電極と、
    　窒化物半導体層の上に設けられたゲート電極と、を備える高電子移動度トランジスタ。     An electronic travel layer,
    An AlGaN layer provided on the electron transit layer;
    An insulating layer containing In and Al provided on the AlGaN layer;
    A nitride semiconductor layer provided on the insulating layer;
    A source electrode and a drain electrode provided on the AlGaN layer;
    And a gate electrode provided on the nitride semiconductor layer.
  2. 　絶縁層は、組成比がＩｎ０．１８Ａｌ０．８２ＮのＩｎＡｌＮからなる請求項１に記載の高電子移動度トランジスタ。 The high electron mobility transistor according to claim 1, wherein the insulating layer is made of InAlN having a composition ratio of In 0.18 Al 0.82 N.
  3. 　電子走行層の上にＡｌＧａＮ層を設ける工程と、
    　ＡｌＧａＮ層の上にＩｎ及びＡｌを含有する絶縁層を設ける工程と、
    　絶縁層の上に窒化物半導体層を設ける工程と、
    　ＡｌＧａＮ層の上にソース電極及びドレイン電極を設ける工程と、
    　窒化物半導体層の上にゲート電極を設ける工程と、を備える高電子移動度トランジスタの製造方法。     Providing an AlGaN layer on the electron transit layer;
    Providing an insulating layer containing In and Al on the AlGaN layer;
    Providing a nitride semiconductor layer on the insulating layer;
    Providing a source electrode and a drain electrode on the AlGaN layer;
    Providing a gate electrode on the nitride semiconductor layer. A method for manufacturing a high electron mobility transistor.
  4. 　ゲート電極を設ける前に、窒化物半導体層の一部をエッチング法により絶縁層まで除去する工程を備える、請求項３に記載の高電子移動度トランジスタの製造方法。
    　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　      4. The method for manufacturing a high electron mobility transistor according to claim 3, further comprising a step of removing a part of the nitride semiconductor layer up to the insulating layer by an etching method before providing the gate electrode.
PCT/JP2014/064774 2013-09-12 2014-06-03 High-electron-mobility transistor and method for manufacturing same WO2015037288A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273630A (en) * 2003-03-06 2004-09-30 Sumitomo Electric Ind Ltd Method of manufacturing field effect transistor
JP2009071061A (en) * 2007-09-13 2009-04-02 Toshiba Corp Semiconductor apparatus
JP2013074188A (en) * 2011-09-28 2013-04-22 Fujitsu Ltd Compound semiconductor device and manufacturing method of the same
JP2013074179A (en) * 2011-09-28 2013-04-22 Fujitsu Ltd Compound semiconductor device and manufacturing method of the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273630A (en) * 2003-03-06 2004-09-30 Sumitomo Electric Ind Ltd Method of manufacturing field effect transistor
JP2009071061A (en) * 2007-09-13 2009-04-02 Toshiba Corp Semiconductor apparatus
JP2013074188A (en) * 2011-09-28 2013-04-22 Fujitsu Ltd Compound semiconductor device and manufacturing method of the same
JP2013074179A (en) * 2011-09-28 2013-04-22 Fujitsu Ltd Compound semiconductor device and manufacturing method of the same

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