JP2008010461A - Hetero-junction field effect transistor, and manufacturing method of hetero-junction field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hetero-junction field effect transistor in which a damage imposed on a channel region can be reduced in forming a recess gate, and to provide a manufacturing method of the hetero-junction field effect transistor. <P>SOLUTION: The hetero-junction field effect transistor includes a first layer made of an undoped or n-type nitride semiconductor layer; a second layer made of a p-type nitride semiconductor layer and formed on the first layer; a pair of third layers formed on the second layer with an interval, and made of an undoped or n-type nitride semiconductor layer; a gate electrode formed on at least one part of a region of the second layer between the pair of the third layers; a source electrode formed on any one of third layers; and a drain electrode formed on the other of third layers. The manufacturing method of the hetero-junction field effect transistor is also provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a heterojunction field effect transistor using a nitride semiconductor and a method for manufacturing a heterojunction field effect transistor, and more particularly to a heterojunction field effect transistor capable of reducing damage to a channel region when a recess gate is formed. The present invention relates to a method for manufacturing a transistor and a heterojunction field effect transistor.

  Conventionally, as a method for realizing normally-off of a heterojunction field effect transistor using a nitride semiconductor such as a nitride-based III-V compound semiconductor, for example, a barrier layer made of a nitride semiconductor below a gate electrode is used. There has been a method of forming a recess gate by thinning by plasma etching (for example, see Non-Patent Document 1).

  However, when plasma etching is used, the barrier layer is hit by energetic particles, so that the channel region located below the barrier layer is damaged, and the two-dimensional electron gas concentration and electron mobility are lowered. was there.

Patent Document 1 discloses a method of forming a recess gate by plasma etching and forming a p-type layer by ion implantation. Both plasma etching and ion implantation are methods for damaging the channel region. This is not a fundamental solution to the above problem.
JP 2001-185717 A Takeshi Nakada, Ken Kawasaki, Seiji Yae, “Normally Off AlGaN / GaN HEMT Using Recess Gate”, IEICE Tech. 105, no. 325, pp. 51-56

  In view of the above circumstances, an object of the present invention is to provide a heterojunction field effect transistor and a method for manufacturing a heterojunction field effect transistor that can reduce damage to a channel region when a recess gate is formed. .

  The present invention provides a first layer made of an undoped or n-type nitride semiconductor layer, a second layer made of a p-type nitride semiconductor layer formed on the first layer, and an interval on the second layer. A pair of third layers made of undoped or n-type nitride semiconductor layers, a gate electrode formed in at least part of the region of the second layer between the pair of third layers, and a pair of first layers The heterojunction field-effect transistor includes a source electrode formed on one third layer of the three layers and a drain electrode formed on the other third layer.

  The present invention also provides a first layer made of an undoped or n-type nitride semiconductor layer, a second layer made of Mg δ-doped layer formed on the first layer, and an interval on the second layer. A pair of third layers made of undoped or n-type nitride semiconductor layers, a gate electrode formed in at least part of the region of the second layer between the pair of third layers, and a pair of first layers The heterojunction field-effect transistor includes a source electrode formed on one third layer of the three layers and a drain electrode formed on the other third layer.

  The present invention also includes a step of forming a second layer of a p-type nitride semiconductor layer or a Mg δ-doping layer on a first layer of an undoped or n-type nitride semiconductor layer; Forming a third layer made of an undoped or n-type nitride semiconductor layer, forming a source electrode and a drain electrode on the third layer, and removing a part of the third layer by a photochemical etching method. A step of exposing a part of the surface of the second layer, and a step of forming a gate electrode in at least a part of the exposed surface of the second layer. It is.

  Here, in the method for manufacturing a heterojunction field effect transistor of the present invention, it is preferable that the light used for the photochemical etching includes light having an energy larger than the band gap energy of the third layer.

  In the method for producing a heterojunction field effect transistor of the present invention, it is preferable to use at least part of the source electrode and the drain electrode as electrodes in the photochemical etching method.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the heterojunction field effect transistor which can reduce the damage given to a channel area | region at the time of formation of a recess gate, and a heterojunction field effect transistor can be provided.

  Embodiments of the present invention will be described below. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

(Embodiment 1)
FIG. 1 shows a schematic cross-sectional view of a preferred example of the heterojunction field effect transistor of the present invention. A heterojunction field effect transistor shown in FIG. 1 includes a multiple buffer layer 2 in which a plurality of AlN layers and GaN layers are alternately stacked on a Si substrate 1 as a substrate, a GaN layer 3 as a channel layer, and hetero characteristics. AlN layer 4 as the improvement layer, undoped as the first layer (no doping of n-type dopant and p-type dopant) or n-type Al _0.3 Ga _0.7 N layer 5, p-type as the second layer The Al _0.3 Ga _0.7 N layer 6 and the undoped or n-type Al _0.3 Ga _0.7 N layer 7 as a pair of third layers are stacked in this order.

Here, the undoped or n-type pair of Al _0.3 Ga _0.7 N layers 7 are formed on the p-type Al _0.3 Ga _0.7 N layer 6 with a space therebetween, and on one Al _0.3 Ga _0.7 N layer 7. A source electrode 8 is formed, and a drain electrode 10 is formed on the other Al _0.3 Ga _0.7 N layer 7. A gate electrode 9 is formed in the region of the p-type Al _0.3 Ga _0.7 N layer 6 between these Al _0.3 Ga _0.7 N layers 7.

  Further, since the band gap of the AlN layer 4 is larger than the band gap of the GaN layer 3, a two-dimensional electron gas layer serving as a channel region is formed on the GaN layer 3 side at the interface between the GaN layer 3 and the AlN layer 4. . The carriers supplied from the source electrode 8 are taken out from the drain electrode 10 through the two-dimensional electron gas layer serving as the channel region. The presence or absence of the progression of carriers in the channel region depends on the voltage applied to the gate electrode 9. It can be controlled by the presence or absence of application.

The heterojunction field effect transistor shown in FIG. 1 can be manufactured, for example, as follows. First, as shown in the schematic cross-sectional view of FIG. 2, on a Si substrate 1, a multiple buffer layer 2, for example, a GaN layer 3 having a thickness of 2 μm, for example, an AlN layer 4 having a thickness of 1 nm, for example, an undoped layer having a thickness of 10 nm, n-type Al _0.3 Ga _0.7 N layer 5, for example, p-type Al _0.3 Ga _0.7 N layer 6 with a layer thickness of 3 nm and a carrier concentration of 5 × 10 ¹⁶ cm ⁻³ , and undoped or n-type Al with a layer thickness of 20 nm, for example _{The 0.3} Ga _0.7 N layer 7 is grown in this order by a vapor phase growth method such as MOCVD method or MBE method.

  Here, the substrate is not limited to the Si substrate 1, and a semiconductor substrate such as a sapphire substrate or a SiC substrate can also be used. Note that the layer structure of the multiple buffer layer 2 may change depending on the type of the substrate.

The layer thickness of the GaN layer 3 as the channel layer is preferably 1 μm or more. Further, the carrier concentration of the channel layer is preferably as low as possible, for example, 10 ¹⁵ cm ⁻³ or less.

Further, the composition and layer thickness of the Al _0.3 Ga _0.7 N layer 5 as the first layer are not particularly limited, but the layer thickness required for normally-off varies depending on the composition. For example, in the case of the Al _0.3 Ga _0.7 N layer 5, normally-off can be achieved by setting the layer thickness to 10 nm or less. Further, the composition, layer thickness, and carrier concentration of the Al _0.3 Ga _0.7 N layer 7 as the third layer are not particularly limited.

Next, a resist patterned in a predetermined shape is formed on the surface of the Al _0.3 Ga _0.7 N layer 7 by using a photolithography technique, and a metal film for a source electrode and a drain electrode is deposited on the resist, for example. It is formed by the law. Then, after removing the resist by lift-off, the metal film remaining on the surface of the Al _0.3 Ga _0.7 N layer 7 is subjected to heat treatment. Thereby, as shown in the schematic cross-sectional view of FIG. 3, the source electrode 8 and the drain electrode 10 are formed on the surface of the Al _0.3 Ga _0.7 N layer 7, and the source electrode 8 and the drain electrode 10 are made of Al _0.3 Ga _0.7. Make ohmic contact with N layer 7.

  Here, as a metal film for forming the source electrode 8 and the drain electrode 10, for example, a metal film in which a Ti layer and an Al layer are laminated in this order, or an Hf layer, an Al layer, an Hf layer, and an Au layer are used. A metal film or the like laminated in order can be used.

Subsequently, a part of the surface of the p-type Al _0.3 Ga _0.7 N layer 6 is removed by removing a part of the Al _0.3 Ga _0.7 N layer 7 by photochemical etching, as shown in the schematic cross-sectional view of FIG. Then, a recess gate is formed. The etching time may be longer than the time during which the entire thickness of the Al _0.3 Ga _0.7 N layer 7 is etched by the photochemical etching method. Etching by the photochemical etching method stops when it reaches the p-type Al _0.3 Ga _0.7 N layer 6, so that etching does not proceed any further.

Then, a gate electrode 9 made of, for example, WN or the like that is in Schottky contact with the p-type Al _0.3 Ga _0.7 N layer 6 is formed in at least a part of the exposed surface of the p-type Al _0.3 Ga _0.7 N layer 6. By dividing the wafer after the gate electrode 9 is formed into chips, the heterojunction field effect transistor shown in FIG. 1 is manufactured.

Here, in the photochemical etching method, for example, a part of the surface of the Al _0.3 Ga _0.7 N layer 7 is brought into contact with a solution (for example, H ₂ SO ₄ or KOH) to form the first electrode, which is also in contact with the above solution. Al is in contact with the solution while flowing current through the solution between the first electrode and the second electrode with at least a part of the source electrode 8 and the drain electrode 10 as the second electrode. _0.3 Ga light is irradiated containing _0.7 N layer 7 large light energy than the band gap energy of the Al _0.3 Ga _0.7 N layer 7 in a portion of, the portion of the Al _0.3 Ga _0.7 N layer 7 whose light is irradiated This can be done by etching.

For example, a nitride semiconductor represented by a composition formula of Al _x Ga _y In _z N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≠ 0) is hardly etched by a solution. This is a major factor in using plasma etching in the prior art.

  However, in photochemical etching, electrons are excited to the conduction band by irradiating light having energy larger than the band gap of the nitride semiconductor to be etched, thereby making the nitride semiconductor easily react with the solution. The nitride semiconductor is etched by reaction with the solution.

Therefore, in the photochemical etching method, from the viewpoint of exciting electrons in the nitride semiconductor to the conduction band, it is preferable to irradiate light containing light having energy larger than the band gap energy of the nitride semiconductor to be etched. In the present embodiment, the Al _0.3 Ga _0.7 N layer 7 is etched by the photochemical etching method. For example, when the GaN layer is etched by the photochemical etching method, it corresponds to the band gap energy of GaN of 3.4 eV. It is preferable to irradiate light including light having a wavelength shorter than 365 nm from a light source such as a halogen lamp.

  Further, in order to advance the etching of the nitride semiconductor by the photochemical etching method, it is preferable to perform etching with a solution by irradiating light while passing a current through the nitride semiconductor, but the surface of the nitride semiconductor in contact with the solution is preferably removed. Such a current path can be established by using as the second electrode at least part of the source electrode 8 and the drain electrode 10 which are ohmic electrodes in contact with the same solution as the first electrode. .

  Etching of nitride semiconductors by the photochemical etching method is particularly effective for undoped or n-type nitride semiconductors, and for p-type nitride semiconductors, since electrons become minority carriers, etching proceeds. Therefore, in the etching of the nitride semiconductor by the photochemical etching method, the etching selectivity occurs depending on the conductivity type of the nitride semiconductor.

Thus, for example, as in the present embodiment, etching by photochemical etching by the Al _0.3 Ga _0.7 N layer 6 underlying the p-type Al _0.3 Ga _0.7 N layer 7 is etched previously formed as an etching stop layer This damage does not reach the channel region below the p-type Al _0.3 Ga _0.7 N layer 6, and the etching controllability is excellent.

  Therefore, in the heterojunction field effect transistor of this embodiment manufactured in this way, the two-dimensional electron gas layer serving as the channel region is damaged by etching compared to the conventional method of forming the recess gate using plasma etching. Therefore, the characteristics are excellent. In addition, the heterojunction field effect transistor of this embodiment has in-plane uniformity (a voltage applied to the gate electrode when the heterojunction field effect transistor formed from the same wafer is in a pinch-off state (normally off). In this case, the voltage applied to the gate electrode when a heterojunction field-effect transistor formed from different wafers of the same structure is in a pinch-off state (in the case of normally-off) Can be a normally-off type heterojunction field effect transistor excellent in uniformity of 0V).

(Embodiment 2)
FIG. 5 is a schematic cross-sectional view of another preferred example of the heterojunction field effect transistor of the present invention. The heterojunction field effect transistor shown in FIG. 5 includes a multiple buffer layer 2 in which a plurality of AlN layers and GaN layers are alternately stacked on a Si substrate 1 as a substrate, and Al _0.05 Ga _0.95 as a lower barrier layer. N layer 13, GaN layer 14 as channel layer, AlN layer 15 as hetero characteristic improving layer, undoped or n-type Al _0.25 Ga _0.7 In _0.05 N layer 16 as first layer, Mg δ as second layer The doped layer 17 and the undoped or n-type Al _0.3 Ga _0.65 In _0.05 N layer 18 as a pair of third layers are stacked in this order.

Here, a pair of undoped or n-type Al _0.3 Ga _0.65 In _0.05 N layer 18 is formed on Mg δ-doping layer 17 with an interval, and on one Al _0.3 Ga _0.65 In _0.05 N layer 18 A source electrode 8 is formed, and a drain electrode 10 is formed on the other Al _0.3 Ga _0.65 In _0.05 N layer 18. A gate electrode 9 is formed in at least a part of the region of the Mg δ-doping layer 17 between these Al _0.3 Ga _0.65 In _0.05 N layers 18.

Further, the band gap of the Al _0.05 Ga _0.95 N layer 13 becomes larger than the band gap of the GaN layer 14, Al _0.05 Ga _0.95 N layer 13 and GaN layer 14 side to the channel region of the interface between the GaN layer 14 2 A dimensional electron gas layer is formed. The carriers supplied from the source electrode 8 are taken out from the drain electrode 10 through the two-dimensional electron gas layer serving as the channel region. The presence or absence of the progression of carriers in the channel region depends on the voltage applied to the gate electrode 9. It can be controlled by the presence or absence of application.

The heterojunction field effect transistor shown in FIG. 5 can be manufactured, for example, as follows. First, as shown in the schematic cross-sectional view of FIG. 6, on the Si substrate 1, a multiple buffer layer 2, for example, an Al _0.05 Ga _0.95 N layer 13 having a thickness of 2 μm, a GaN layer 14, for example, an AlN layer 15 having a thickness of 1 nm is formed. For example, an Al _0.25 Ga _0.7 In _0.05 N layer 16 having a layer thickness of 10 nm, for example, a δ-doping layer 17 having a doping concentration of 10 ¹³ cm ⁻² and an Al _0.3 Ga having a layer thickness of 25 nm and a carrier concentration of 5 × 10 ¹⁶ cm ⁻³ _{A 0.65} In _0.05 N layer 18 is formed in this order.

  Here, the substrate is not limited to the Si substrate 1, and a semiconductor substrate such as a sapphire substrate or a SiC substrate can also be used. Note that the layer structure of the multiple buffer layer 2 may change depending on the type of the substrate.

The layer thickness of the Al _0.05 Ga _0.95 N layer 13 as the lower barrier layer is preferably 1 μm or more. Further, the carrier concentration of the channel layer is preferably as low as possible, for example, 10 ¹⁵ cm ⁻³ or less.

Further, the composition and layer thickness of the Al _0.25 Ga _0.7 In _0.05 N layer 16 as the first layer are not particularly limited, but the layer thickness required for normally-off changes depending on the composition. For example, in the case of the Al _0.25 Ga _0.7 In _0.05 N layer 16, normally-off can be achieved by setting the layer thickness to 10 nm or less.

Further, the composition, layer thickness, and carrier concentration of the Al _0.3 Ga _0.65 In _0.05 N layer 18 as the third layer are not particularly limited.

  The Mg δ-doping layer 17 is a layer in which only Mg is deposited, and can be formed, for example, by irradiating only Mg during growth.

Next, a resist patterned in a predetermined shape is formed on the surface of the Al _0.3 Ga _0.65 In _0.05 N layer 18 by using a photolithography technique, and a metal film for the source electrode and the drain electrode is formed thereon. For example, it is formed by vapor deposition. Then, after removing the resist by lift-off, the metal film remaining on the surface of the Al _0.3 Ga _0.65 In _0.05 N layer 18 is subjected to heat treatment. Thus, as shown in a schematic cross-sectional view of FIG. _{7, Al 0.3 Ga 0.65 In 0.05} N layer 18 source electrode 8 and the drain electrode 10 on the surface of formed, respectively source electrode 8 and the drain electrode 10 is Al _0.3 An ohmic contact is made with the Ga _0.65 In _0.05 N layer 18.

  Here, as a metal film for forming the source electrode 8 and the drain electrode 10, for example, a metal film in which a Ti layer and an Al layer are laminated in this order, or an Hf layer, an Al layer, an Hf layer, and an Au layer are used. A metal film or the like laminated in order can be used.

Subsequently, a part of the Al _0.3 Ga _0.65 In _0.05 N layer 18 is removed by photochemical etching to expose a part of the surface of the δ-doping layer 17 as shown in the schematic cross-sectional view of FIG. A recess gate is formed. The etching time may be longer than the time during which the entire thickness of the Al _0.3 Ga _0.65 In _0.05 N layer 18 is etched by the photochemical etching method. Since the etching by the photochemical etching method stops when it reaches the δ-doping layer 17, the etching does not proceed any further.

Further, as in the case of the first embodiment, the photochemical etching method is performed by, for example, contacting a part of the surface of the Al _0.3 Ga _0.65 In _0.05 N layer 18 with a solution (for example, H ₂ SO ₄ or KOH). The first electrode and the source electrode 8 and the drain electrode 10 that are in contact with the solution are used as second electrodes, and a current is passed between the first electrode and the second electrode through the solution. while flowing, was irradiated with light containing a large energy of light than the band gap energy of the Al _0.3 Ga _0.65 in _0.05 Al in a portion of the N layer 18 _0.3 Ga _0.65 in _0.05 N layer 18 in contact with the above solution, the light Can be performed by etching the portion of the Al _0.3 Ga _0.65 In _0.05 N layer 18 irradiated with.

  Then, a gate electrode 9 made of, for example, WN or the like that is in Schottky contact with the δ doping layer 17 is formed in at least a part of the exposed surface of the δ doping layer 17, and the wafer after the gate electrode 9 is formed is formed. The heterojunction field effect transistor shown in FIG. 5 is manufactured by dividing into chips.

  Therefore, in the heterojunction field effect transistor of this embodiment manufactured in this way, the two-dimensional electron gas layer serving as the channel region is damaged by etching as compared with the conventional method of forming the recess gate using plasma etching. Therefore, the characteristics are excellent. In addition, the heterojunction field effect transistor of this embodiment also has in-plane uniformity (the voltage applied to the gate electrode when the heterojunction field effect transistor formed from the same wafer is in a pinch-off state (normally off). In this case, the voltage applied to the gate electrode when a heterojunction field-effect transistor formed from different wafers of the same structure is in a pinch-off state (in the case of normally-off) Can be a normally-off type heterojunction field effect transistor excellent in uniformity of 0V). Other explanations are the same as those in the first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the heterojunction field effect transistor which can reduce the damage given to a channel area | region at the time of formation of a recess gate, and a heterojunction field effect transistor can be provided.

It is typical sectional drawing of a preferable example of the heterojunction field effect transistor of this invention. FIG. 2 is a schematic cross-sectional view illustrating an example of a state in the middle of manufacturing the heterojunction field effect transistor shown in FIG. 1. FIG. 2 is a schematic cross-sectional view illustrating an example of a state in the middle of manufacturing the heterojunction field effect transistor shown in FIG. 1. FIG. 2 is a schematic cross-sectional view illustrating an example of a state in the middle of manufacturing the heterojunction field effect transistor shown in FIG. 1. It is typical sectional drawing of another preferable example of the heterojunction field effect transistor of this invention. FIG. 6 is a schematic cross-sectional view illustrating an example of a state in the middle of manufacturing the heterojunction field effect transistor shown in FIG. 5. FIG. 6 is a schematic cross-sectional view illustrating an example of a state in the middle of manufacturing the heterojunction field effect transistor shown in FIG. 5. FIG. 6 is a schematic cross-sectional view illustrating an example of a state in the middle of manufacturing the heterojunction field effect transistor shown in FIG. 5.

Explanation of symbols

1 Si substrate, 2 multiple buffer layers, 3,14 GaN layer, 4,15 AlN layer, 5 Al _0.3 Ga _0.7 N layer, 6 Al _0.3 Ga _0.7 N layer, 7 Al _0.3 Ga _0.7 N layer, 8 source electrode, 9 Gate electrode, 10 drain electrode, 13 Al _0.05 Ga _0.95 N layer, 16 Al _0.25 Ga _0.7 In _0.05 N layer, 17 δ doping layer, 18 Al _0.3 Ga _0.65 In _0.05 N layer.

Claims (5)

A first layer comprising an undoped or n-type nitride semiconductor layer;
A second layer made of a p-type nitride semiconductor layer formed on the first layer;
A pair of third layers made of undoped or n-type nitride semiconductor layers formed on the second layer at an interval;
A gate electrode formed in at least a part of the region of the second layer between the pair of third layers;
A source electrode formed on one third layer of the pair of third layers; a drain electrode formed on the other third layer;
A heterojunction field effect transistor comprising: A first layer comprising an undoped or n-type nitride semiconductor layer;
A second layer comprising a Mg δ-doping layer formed on the first layer;
A pair of third layers made of undoped or n-type nitride semiconductor layers formed on the second layer at an interval;
A gate electrode formed in at least a part of the region of the second layer between the pair of third layers;
A source electrode formed on one third layer of the pair of third layers; a drain electrode formed on the other third layer;
A heterojunction field effect transistor comprising: Forming a p-type nitride semiconductor layer or a second layer of Mg δ-doping layer on the first layer of undoped or n-type nitride semiconductor layer;
Forming a third layer comprising an undoped or n-type nitride semiconductor layer on the second layer;
Forming a source electrode and a drain electrode on the third layer;
Removing a part of the third layer by a photochemical etching method to expose a part of the surface of the second layer;
Forming a gate electrode in at least a partial region of the exposed surface of the second layer;
A method of manufacturing a heterojunction field effect transistor, comprising:   4. The method of manufacturing a heterojunction field effect transistor according to claim 3, wherein light used in the photochemical etching method includes light having an energy larger than a band gap energy of the third layer.   5. The method of manufacturing a heterojunction field effect transistor according to claim 3, wherein in the photochemical etching method, at least a part of the source electrode and the drain electrode is used as an electrode.

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