JP2013175726A - ENHANCEMENT MODE GaN HEMT DEVICE WITH GATE SPACER AND METHOD FOR FABRICATING THE SAME - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide enhancement-mode GaN devices having a gate spacer, a gate metal material, and a gate compound that are self-aligned, and a method for fabricating the same.SOLUTION: The gate spacer, the gate metal material, and the gate compound are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface between the gate spacer and the gate compound has lower leakage than the interface between a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped group III-V compound corner on the drain contact side, which leads to lower gate leakage current and improved gate reliability.

Description

  The present invention relates to the field of enhancement mode gallium nitride (GaN) high electron mobility transistor (HEMT) devices. In particular, the present invention relates to a method and apparatus for providing an enhancement type HEMT device with a gate spacer.

  Gallium nitride (GaN) semiconductor devices are becoming increasingly desirable for power semiconductor devices because of their ability to carry high currents and handle high voltages. The development of these devices has generally been aimed at high power / high frequency applications. Devices manufactured for such applications are based on common device structures that exhibit high electron mobility, such as heterojunction field effect transistors (HFETs), high electron mobility transistors (HEMTs), or modulation doping. It is called variously like a field effect transistor (MODFET).

  A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Due to the different materials formed on the semiconductor or on the buffer layer, these layers have different band gaps. Different materials in adjacent nitride layers also cause polarization, which is a conductive 2 near the junction of the two layers, specifically in the layer with the narrower band gap. Contributes to the dimensional electron gas (2DEG) region.

  The nitride layer that causes polarization typically includes an AlGaN barrier layer adjacent to a layer of GaN containing 2DEG that allows charge to flow through the device. This barrier layer may be doped or undoped. Most nitride devices are normally on or depletion mode devices because the 2DEG region extends under the gate with zero gate bias. If the 2DEG region is depleted or removed with zero applied gate bias under the gate, the device can be an enhancement mode device. Enhancement mode devices are desirable because they are normally off, which adds safety and is easy to control with a simple low cost drive circuit. Enhancement mode devices require that a positive bias be applied to the gate in order to conduct current.

  In a conventional enhancement mode GaN transistor, the gate metal and the p-type GaN material or p-type AlGaN material are defined using separate photomasks. For example, FIG. 1 (prior art) shows that the gate metal and gate pGaN were processed using two different photomasks. FIG. 1 illustrates a conventional enhancement mode GaN transistor device 100 that includes a substrate 101, which can be either sapphire or silicon, a plurality of transition layers 102, an undoped GaN material 103, and an undoped AlGaN 104. Source ohmic contact metal 109, drain ohmic contact metal 110, p-type AlGaN material or p-type GaN material 105, heavily doped p-type GaN material 106, and gate metal 111.

  As shown in FIG. 1, the gate metal, p-type GaN material or p-type AlGaN material is defined by two separate photomasks. The first mask forms p-type GaN or p-type AlGaN either by patterning a hard mask and selectively growing p-type GaN, or by patterning and etching p-type GaN. Used to do. The second mask is used to form the gate metal either by patterning and lifting off the gate metal or by patterning and etching the gate metal. These two mask processes result in a wider gate length than the photo / etch minimum CD. This results in high gate charge, wider cell pitch, and higher Rdson (“on resistance”). Conventional manufacturing methods also increase manufacturing costs. Another disadvantage is that the highest electric field is located at the gate corner of the p-type GaN material or p-type AlGaN material towards the drain ohmic contact metal. This high electric field results in a large gate leakage current and a high gate reliability risk.

  It would be desirable to provide an enhancement mode GaN transistor structure with a self-aligned gate that avoids the aforementioned drawbacks of the prior art. It is also desirable to provide a function to alleviate a high electric field at the gate corner of p-type GaN or AlGaN.

  Embodiments disclosed herein relate to an enhancement mode GaN transistor having a self-aligned gate spacer, a gate metal material and a gate compound, and a method for manufacturing the same. These materials are patterned and etched using a single photomask, thereby reducing manufacturing costs. The interface between the gate spacer and the gate compound has a lower leak than the interface between the dielectric film and the gate compound, thereby reducing the gate leak. Furthermore, the ohmic contact metal layer is used as a field plate to mitigate the electric field at the corner of the doped III-V compound on the drain contact side, resulting in lower gate leakage current and improved gate reliability.

It is sectional drawing which illustrates the conventional enhancement mode GaN transistor. FIG. 3 illustrates an enhancement mode GaN HEMT device with gate spacers formed in accordance with the first embodiment of the invention described herein. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 1st Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 1st Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 1st Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 1st Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 1st Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 1st Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 1st Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 1st Embodiment of this invention. FIG. 6 illustrates an enhancement mode GaN HEMT device with gate spacers formed in accordance with a second embodiment of the present invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 2nd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 2nd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 2nd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 2nd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 2nd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 2nd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 2nd Embodiment of this invention. FIG. 6 illustrates an enhancement mode GaN HEMT device with gate spacers formed in accordance with the third embodiment of the invention described herein. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 3rd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 3rd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 3rd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 3rd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 3rd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 3rd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 3rd Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 3rd Embodiment of this invention. FIG. 6 illustrates an enhancement mode GaN HEMT device with gate spacers formed in accordance with the fourth embodiment of the invention described herein. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 4th Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 4th Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 4th Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 4th Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 4th Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 4th Embodiment of this invention. It is a figure which shows typically the formation method of the enhancement mode GaN HEMT device according to 4th Embodiment of this invention.

  In the following detailed description, reference is made to specific embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice these embodiments. As will be appreciated, other embodiments may be used and various structural, logical and electrical changes may be made.

  The present invention relates to enhancement mode GaN HEMT devices in which gate spacers, gate metal materials and gate compounds are self-aligned, and methods of manufacturing such devices. These materials are patterned and etched using a single photomask, thereby reducing manufacturing costs. Further, the interface between the gate spacer 21 and the gate compound has a lower leak than the interface between the dielectric film and the gate compound, thereby reducing the gate leak. Furthermore, the ohmic contact metal layer is used as a field plate to mitigate the electric field at the corner of the doped III-V compound on the drain contact side, resulting in lower gate leakage current and improved gate reliability. A field plate at the source potential shields the gate from drain bias. The gate drain charge (Qgd) decreases.

  With reference to FIGS. 2 and 3A-3H, a first embodiment will be described with respect to forming an enhancement mode GaN HEMT device having a gate spacer and a self-aligned gate. Throughout the drawings, similar reference numerals are used for similar parts throughout. FIG. 2 shows an enhancement mode GaN HEMT device 200 having a self-aligned gate metal 17 and a III-V gate compound 15 formed by the method described below with respect to FIGS. 3A-3H. The device 200 includes a silicon substrate 11, a buffer material 12, an undoped GaN buffer material 13, an undoped AlGaN barrier material 14, a group III-V gate compound 15, a gate metal 17, a dielectric material 18, a drain ohmic contact 19, and a source ohmic. A contact 20 and a dielectric spacer 21 are included. The source metal 20 also acts as a field plate that extends above the gate toward the drain contact.

FIG. 3A shows an EPI (epi) structure of a GaN HEMT device 200a, from bottom to top, the silicon substrate 11, buffer material 12, undoped GaN buffer material 13, and undoped AlGaN barrier material 14. , And III-V gate compound material 15. The undoped GaN buffer material 13 preferably has a thickness of about 0.5 μm to about 5 μm. The undoped AlGaN barrier material 14 preferably has a thickness of about 50 to about 300 inches. The undoped AlGaN barrier material 14 includes Al from about 12% to 28% of the metal content of the AlGaN material. The III-V gate compound 15 may have a thickness of about 500 to about 2000 inches. The III-V gate compound 15 may also have a p-type doping concentration between about 10 ¹⁸ atoms / cm ³ and about 10 ²⁰ atoms / cm ³ .

As shown in FIG. 3B, gate metal 17 is deposited on the EPI structure shown in FIG. 3A. The gate metal 17 may alternatively be grown at the end of the EPI growth. The gate metal 17 can be made of a refractory metal such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), palladium (Pd), tungsten (W), tungsten silicide (WSi ₂ ), or a compound thereof. .

  Thereafter, the gate metal 17 is patterned and etched using a single photomask to obtain the stack structure shown in FIG. 3C. The gate metal 17 is etched by a known technique such as plasma etching, and then the photoresist is peeled off.

3D, a dielectric material 21 such as silicon oxide (SiO ₂ ) or plasma enhanced chemical vapor deposition (PECVD) silicon nitride (Si ₃ N ₄ ) is deposited on the structure of FIG. 3C. The After the dielectric material 21 is deposited, the dielectric material 21 is patterned and etched by an etch back process to obtain a spacer 21 on the side wall of the gate metal 17 (shown in FIG. 3E).

Subsequently, referring to FIG. 3F, the III-V gate compound 15 is etched using the gate metal 17 and the spacer 21 as a hard mask. Then, a dielectric material 18 such as Si ₃ N ₄ is deposited on the structure of FIG. 3F. After the dielectric material 18 is deposited, the dielectric material 18 is etched using a contact photomask, and then the photoresist is stripped to form the structure shown in FIG. 3G.

  On the structure of FIG. 3G, ohmic contact metal is deposited. The ohmic contact metal may be made of a stack (stacked body) of titanium (Ti), aluminum (Al), and cap metal. After the ohmic metal is deposited, the ohmic contact metal is patterned and etched using a metal mask to obtain a drain ohmic contact 19 and a source ohmic contact 20 as shown in FIG. 3H. Rapid thermal annealing (RTA) is performed to form ohmic contacts to the AlGaN / GaN 2DEG. The source ohmic contact metal 20 is also provided above the gate and functions as a field plate. This reduces the electric field at the corner of the group III-V gate compound 15 on the side close to the drain ohmic contact 19.

According to the method described above, the gate metal 17 is patterned and etched. Thereafter, dielectric spacers 21 are formed on the side walls of the gate metal 17. Then, the III-V gate compound is etched using the gate metal 17 and the spacer 21 as a hard mask. The gate metal 17, spacer 21 and gate compound 15 are formed after a single photomask and are therefore automatically self-aligned. The ohmic contact metals 19 and 20 are made of a stack of Ti, Al, and cap metal. The source metal 20 extends above the gate and acts as a field plate. This reduces the electric field at the drain-side gate corner. Since the source ohmic contact metal 20 is used as a field plate that relaxes the electric field at the corner of the III-V gate on the drain ohmic contact 19 side, lower gate leakage current and improved gate reliability are achieved. The Furthermore, since the field plate at the source potential shields the gate from the drain bias, the gate-drain charge (Q _gd ) is reduced.

  Next, a second embodiment of the present invention will be described with reference to FIGS. 4 and 5A-5G. FIG. 4 shows an enhancement mode GaN HEMT device 300 having a gate spacer 21 formed by the method shown in FIGS. 5A-5G. The resulting device 300 will have a self-aligned gate metal 17 and a III-V gate compound 15. The device 300 of FIG. 4 differs from the device 200 of FIG. 2 in that the spacers 21 it contains are formed not only on the side walls of the gate metal 17 but also on the side walls of the III-V gate compound 15.

  FIG. 5A shows an EPI structure 300a which, from bottom to top, includes a silicon substrate 11, a buffer material 12, an undoped GaN buffer material 13, an undoped AlGaN barrier material 14, and a III-V gate. Compound material 15 is included. The dimensions and composition of these various materials are the same as those of the first embodiment.

  As shown in FIG. 5B, as in the first embodiment, the gate metal 17 is deposited or grown on the EPI structure shown in FIG. 5A.

  Thereafter, patterning and etching of the gate metal 17 and the III-V gate compound 15 are performed using a single photomask, and the state and structure shown in FIG. 5C are obtained (after the photoresist is peeled off). ).

Referring to FIG. 5D, as before, a dielectric material 21 such as silicon oxide (SiO ₂ ) is deposited on the structure of FIG. 5C. After the dielectric material 21 is deposited, an etch back process is performed to pattern and etch the dielectric material 21 to obtain spacers 21 on the sidewalls of the gate metal 17 and III-V gate compound 15 (FIG. 5E). To show).

A dielectric material 18 such as Si ₃ N ₄ is then deposited on the structure of FIG. 5E. After the dielectric material 18 is deposited, the dielectric material 18 is etched using a contact photomask and then the photoresist is stripped to form the structure shown in FIG. 5F.

  On the structure of FIG. 5F, ohmic contact metal is deposited. The ohmic contact metal may consist of a stack of titanium (Ti), aluminum (Al) and cap metal. After the ohmic metal is deposited, the ohmic contact metal is patterned and etched using a metal mask to obtain a drain ohmic contact 19 and a source ohmic contact 20 as shown in FIG. 5G. Rapid thermal annealing (RTA) is performed to form ohmic contacts to the AlGaN / GaN 2DEG. The source ohmic contact metal 20 is also provided above the gate and functions as a field plate. This reduces the electric field at the corner of the group III-V gate compound 15 on the side close to the drain ohmic contact 19.

  According to the method described above, the gate metal 17 and the III-V gate compound 15 are patterned and etched using a single photomask, and thus are self-aligned, and have the same advantages as the first embodiment.

  Next, with reference to FIG. 6 and 7A-7H, 3rd Embodiment of this invention is described. FIG. 6 shows an enhancement mode GaN HEMT device 400 having a self-aligned gate metal 17 and a III-V gate compound 15 formed by the method described with respect to FIGS. 7A-7H. The device 400 includes a silicon substrate 11, a buffer material 12, an undoped GaN buffer material 13, an undoped AlGaN barrier material 14, a group III-V gate compound 15, a gate metal 17, a dielectric material 18, a drain ohmic contact 19, and a source ohmic. A contact 20, a dielectric spacer 21, and a dielectric film 22 are included. The source metal 20 also acts as a field plate that extends above the gate toward the drain contact.

FIG. 7A shows the EPI structure of the GaN HEMT device 400a, which is from bottom to top, silicon substrate 11, buffer material 12, undoped GaN buffer material 13, undoped AlGaN barrier material 14, and III. -Group V gate compound material 15 is included. The undoped GaN buffer material 13 preferably has a thickness of about 0.5 μm to about 5 μm. The undoped AlGaN barrier material 14 preferably has a thickness of about 50 to about 300 inches. The undoped AlGaN barrier material 14 includes Al from about 12% to 28% of the metal content of the AlGaN material. The III-V gate compound 15 may have a thickness of about 500 to about 2000 inches. The III-V gate compound 15 may also have a p-type doping concentration between about 10 ¹⁸ atoms / cm ³ and about 10 ²⁰ atoms / cm ³ .

As shown in FIG. 7B, a gate metal 17 is deposited on the EPI structure shown in FIG. 7A. The gate metal 17 may alternatively be grown at the end of the EPI growth. The gate metal 17 can be made of a refractory metal such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), palladium (Pd), tungsten (W), tungsten silicide (WSi ₂ ), or a compound thereof. . A dielectric film 22 such as silicon oxide (SiO ₂ ) is deposited or formed on the gate metal 17 by any known process.

  Thereafter, the gate metal 17 and the dielectric film 22 are patterned and etched using a single photomask to obtain the stack structure shown in FIG. 7C. The gate metal 17 and the dielectric film 22 are etched by a known technique such as plasma etching, and then the photoresist is peeled off.

7D, a dielectric material 21 such as silicon oxide (SiO ₂ ) or plasma enhanced chemical vapor deposition (PECVD) silicon nitride (Si ₃ N ₄ ) is deposited on the structure of FIG. 7C. The After the dielectric material 21 is deposited, the dielectric material 21 is patterned and etched by an etch-back process to obtain spacers 21 on the side walls of the gate metal 17 and the dielectric film 22 (shown in FIG. 7E).

Subsequently, referring to FIG. 7F, the III-V gate compound 15 is etched using the dielectric film 22 on the gate metal 17 and the spacer 21 as a hard mask. Then, a dielectric material 18 such as Si ₃ N ₄ is deposited on the structure of FIG. 7F. After the dielectric material 18 is deposited, the dielectric material 18 is etched using a contact photomask and then the photoresist is stripped to form the structure shown in FIG. 7G.

  An ohmic contact metal is deposited on the structure of FIG. 7G. The ohmic contact metal may consist of a stack of titanium (Ti), aluminum (Al) and cap metal. After the ohmic metal is deposited, the ohmic contact metal is patterned and etched using a metal mask to obtain a drain ohmic contact 19 and a source ohmic contact 20 as shown in FIG. 7H. Rapid thermal annealing (RTA) is performed to form ohmic contacts to the AlGaN / GaN 2DEG. The source ohmic contact metal 20 is also provided above the gate and functions as a field plate. This reduces the electric field at the corner of the group III-V gate compound 15 on the side close to the drain ohmic contact 19.

  Next, with reference to FIG. 8 and 9A-9G, 4th Embodiment of this invention is described. FIG. 8 shows an enhancement mode GaN HEMT device 500 having a gate spacer 21 formed by the method shown in FIGS. 9A-9G. The resulting device 500 will have a self-aligned gate metal 17 and a III-V gate compound 15. The device 500 is different from the device 400 of FIG. 6 in that the spacer 21 included therein is formed not only on the side walls of the gate metal 17 and the dielectric film 22 but also on the side walls of the III-V gate compound 15.

  FIG. 9A shows an EPI structure 500a, from bottom to top, which includes a silicon substrate 11, a buffer material 12, an undoped GaN buffer material 13, an undoped AlGaN barrier material 14, and a III-V gate. Compound material 15 is included. The dimensions and composition of these various materials are the same as those of the third embodiment described above.

As shown in FIG. 9B, as in the third embodiment, the gate metal 17 is deposited or grown on the EPI structure shown in FIG. 9A, and then the dielectric film 22 (for example, SiO ₂ ) is formed on the gate metal 17. Is formed.

  Thereafter, patterning and etching of the dielectric film 22, the gate metal 17 and the III-V gate compound 15 are performed using a single photomask to obtain the state and structure shown in FIG. After is done).

Referring to FIG. 9D, as in the third embodiment, a dielectric such as silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ) by plasma enhanced chemical vapor deposition (PECVD) is formed on the structure of FIG. 9C. Material 21 is deposited. After the dielectric material 21 is deposited, an etch back process is performed to pattern and etch the dielectric material 21, and spacers 21 are formed on the sidewalls of the dielectric film 22, the gate metal 17, and the III-V gate compound 15. Is obtained (shown in FIG. 9E).

Then, a dielectric material 18 such as Si ₃ N ₄ is deposited on the structure of FIG. 9E. After the dielectric material 18 is deposited, the dielectric material 18 is etched using a contact photomask and then the photoresist is stripped to form the structure shown in FIG. 9F.

  On the structure of FIG. 9F, ohmic contact metal is deposited. The ohmic contact metal may consist of a stack of titanium (Ti), aluminum (Al) and cap metal. After the ohmic metal is deposited, the ohmic contact metal is patterned and etched using a metal mask to obtain a drain ohmic contact 19 and a source ohmic contact 20 as shown in FIG. 9G. Rapid thermal annealing (RTA) is performed to form ohmic contacts to the AlGaN / GaN 2DEG. The source ohmic contact metal 20 is also provided above the gate and functions as a field plate. This reduces the electric field at the corner of the group III-V gate compound 15 on the side close to the drain ohmic contact 19.

  According to the above-described method, the gate metal 17 and the III-V gate compound 15 are patterned and etched using a single photomask, and thus are self-aligned, and have the same advantages as the first to third embodiments. Have

  The above description and drawings are merely to be regarded as illustrative of specific embodiments for achieving the features and advantages described herein. Specific process conditions can be changed and substituted. Accordingly, the embodiments of the invention are not to be considered as limited by the foregoing description and drawings.

Claims (19)

A substrate,
A buffer material on the substrate;
A barrier material on the buffer material;
A gate III-V compound on the barrier material;
A gate metal on the gate III-V compound;
A spacer material formed on at least the side wall of the gate metal;
An enhancement mode GaN transistor having:   The transistor of claim 1, wherein the gate III-V compound and the gate metal are formed by a single photomask process so as to be self-aligned.   The transistor of claim 1, wherein the buffer material comprises GaN.   The transistor of claim 1, wherein the barrier material comprises AlGaN.   The transistor according to claim 1, wherein the spacer material is formed on sidewalls of the gate metal and the gate III-V compound.   The transistor of claim 1 further comprising a dielectric material on the gate metal.   The transistor of claim 6, wherein the spacer material is also formed on a sidewall of the dielectric material.   The transistor according to claim 6, wherein the spacer material is formed on a side wall of the gate metal, the gate III-V group compound, and the dielectric material. The transistor of claim 1, wherein the spacer material comprises silicon oxide (SiO ₂ ). The transistor of claim 1, wherein the spacer material comprises silicon nitride (Si ₃ N ₄ ) by plasma enhanced chemical vapor deposition (PECVD).   The transistor of claim 1, wherein the gate metal comprises one or more refractory metals, metal compounds or alloys, such as Ta, TaN, TiN, Pd, W, or WSi. A method of manufacturing an enhancement mode GaN transistor comprising:
Forming a buffer material on the substrate;
Forming an AlGaN barrier on the buffer material;
Forming a III-V compound on the AlGaN barrier;
Forming a stack having a gate metal on the III-V compound;
Forming a spacer material on at least the side wall of the gate metal stack;
Etching the III-V compound using the gate metal and the spacer material as a mask,
Deposit a dielectric layer,
Etching the dielectric layer to open a drain contact region and a source contact region, and forming an ohmic drain contact and an ohmic source contact in the opened drain contact region and source contact region;
A method that has that.   The method of claim 12, wherein the spacer material is formed on sidewalls of the gate metal stack and the III-V compound.   The method of claim 12, further comprising forming a dielectric material on each gate metal stack.   The method of claim 14, wherein the spacer material is also formed on sidewalls of the dielectric material.   The method of claim 14, wherein the spacer material is formed on sidewalls of the gate metal stack, the III-V compound, and the dielectric material. The method of claim 12, wherein the spacer material comprises silicon oxide (SiO ₂ ). The spacer material has a plasma chemical vapor deposition (PECVD) of silicon nitride _(Si 3 _{N 4),} The method of claim 12.   The method of claim 12, wherein the gate metal comprises one or more refractory metals, metal compounds, or alloys, such as Ta, TaN, TiN, Pd, W, or WSi.

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