CN114975573A

CN114975573A - High electron mobility transistor and manufacturing method thereof

Info

Publication number: CN114975573A
Application number: CN202110189435.5A
Authority: CN
Inventors: 林永丰; 周钰杰; 林琮翔; 庄理文
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2021-02-19
Filing date: 2021-02-19
Publication date: 2022-08-30

Abstract

A high electron mobility transistor is provided, in which a semiconductor channel layer and a semiconductor barrier layer are disposed on a substrate. The patterned semiconductor protection layer is disposed on the semiconductor barrier layer, and the patterned semiconductor cap layer is disposed between the patterned semiconductor protection layer and the semiconductor barrier layer. The interlayer dielectric layer covers the patterned semiconductor cap layer and the patterned semiconductor protection layer, and the interlayer dielectric layer includes a gate contact hole. The gate electrode is arranged in the gate contact hole and electrically connected with the patterned semiconductor cover layer, wherein a patterned semiconductor protective layer is arranged between the gate electrode and the patterned semiconductor cover layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor cover layer and the resistivity of the interlayer dielectric layer.

Description

High electron mobility transistor and manufacturing method thereof

Technical Field

The invention relates to the field of transistors, in particular to a high electron mobility transistor and a manufacturing method thereof.

Background

In semiconductor technology, III-V semiconductor compounds are useful in forming a variety of integrated circuit devices, such as: a high power field effect transistor, a high frequency transistor, or a High Electron Mobility Transistor (HEMT). A HEMT is a transistor having a two-dimensional electron gas (2DEG), the 2DEG being adjacent to a junction (i.e., a heterojunction) between two materials having different energy gaps. Since HEMTs do not use doped regions as the carrier channel of transistors, but 2DEG as the carrier channel of transistors, HEMTs have a number of attractive characteristics compared to conventional Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), such as: high electron mobility and the ability to transmit signals at high frequencies. For a conventional HEMT, a compound semiconductor channel layer, a compound semiconductor barrier layer, a P-type compound semiconductor cap layer, a metal cap layer, and a gate electrode are sequentially stacked. The gate electrode is used for applying bias voltage to the P-type compound semiconductor cover layer, so that the concentration of two-dimensional electron gas in a compound semiconductor channel layer below the P-type compound semiconductor cover layer can be regulated and controlled, and the on-off of the HEMT can be regulated and controlled.

For the metal cap layer disposed between the P-type compound semiconductor cap layer and the gate electrode, the step of forming the metal cap layer typically includes a wet lateral etching process. However, since the etching degree of the lateral etching process is difficult to be precisely controlled, the metal cap layer of each HEMT has different widths, thereby reducing the uniformity of the electrical performance of each HEMT.

Disclosure of Invention

Accordingly, there is a need for an improved hemt to overcome the drawbacks of the conventional hemts.

According to an embodiment of the present invention, a high electron mobility transistor is provided, which includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor protection layer, a patterned semiconductor cap layer, an interlayer dielectric layer, and a gate electrode. The semiconductor channel layer and the semiconductor barrier layer are disposed on the substrate. The patterned semiconductor protection layer is disposed on the semiconductor barrier layer, and the patterned semiconductor cap layer is disposed between the patterned semiconductor protection layer and the semiconductor barrier layer. The interlayer dielectric layer covers the patterned semiconductor cap layer and the patterned semiconductor protection layer, and the interlayer dielectric layer includes a gate contact hole. The gate electrode is arranged in the gate contact hole and electrically connected with the patterned semiconductor cover layer, wherein a patterned semiconductor protective layer is arranged between the gate electrode and the patterned semiconductor cover layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor cover layer and the resistivity of the interlayer dielectric layer.

According to another embodiment of the present invention, a method for fabricating a high electron mobility transistor is provided, including: providing a substrate, on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer and a semiconductor protection layer are sequentially disposed; etching the semiconductor cover layer and the semiconductor protection layer to form a patterned semiconductor cover layer and a patterned semiconductor protection layer; forming an interlayer dielectric layer covering the patterned semiconductor cap layer and the patterned semiconductor protection layer; forming a gate contact hole in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protection layer and is separated from the patterned semiconductor cap layer; and forming a gate electrode in the gate contact hole, wherein a part of the patterned semiconductor protection layer exists between the gate electrode and the patterned semiconductor cover layer, and the resistivity of the patterned semiconductor protection layer is between that of the patterned semiconductor cover layer and that of the interlayer dielectric layer.

According to the embodiment of the invention, since the resistivity of the patterned semiconductor protection layer is higher than that of the upper gate electrode, even if the side surface of the patterned semiconductor protection layer is not etched laterally, the side surface of the patterned semiconductor protection layer is not easy to generate point discharge, thereby avoiding unnecessary gate leakage current. Furthermore, because the bottom surface of the gate contact hole does not penetrate the patterned semiconductor protection layer when the gate contact hole is manufactured, the etchant can be prevented from contacting the patterned semiconductor cover layer, and the original electrical characteristics of the patterned semiconductor cover layer can be maintained.

Drawings

For the following to be more readily understood, reference is made to the drawings and to the detailed description thereof, when read in conjunction with the appended drawings. The embodiments of the present invention are illustrated in detail and explained with reference to the corresponding drawings, and the operation principle of the embodiments of the present invention is explained. Furthermore, for purposes of clarity, the various features in the drawings may not be to scale and the dimensions of some of the features in some drawings may be exaggerated or minimized.

Fig. 1 is a schematic cross-sectional view of a High Electron Mobility Transistor (HEMT) according to an embodiment of the present invention.

Fig. 2 is an enlarged cross-sectional view of a local region of a high electron mobility transistor according to an embodiment of the invention.

Fig. 3 is an enlarged cross-sectional view of a local region of a hemt according to a variation of the present invention.

Fig. 4 is a schematic cross-sectional view of a hemt according to a variation of the present invention.

Fig. 5 is a cross-sectional view of a high electron mobility transistor according to an embodiment of the invention, wherein the high electron mobility transistor comprises sequentially stacked semiconductor layers.

Fig. 6 is a cross-sectional view of a patterned semiconductor cap layer, a patterned semiconductor protection layer, and a shielding layer for fabricating a hemt according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view of an embodiment of the present invention showing the fabrication of a HEMT, including a gate contact hole in an IMD layer.

Fig. 8 is a cross-sectional view of a high electron mobility transistor according to an embodiment of the invention, including a gate electrode.

FIG. 9 is a cross-sectional view of a high electron mobility transistor including source/drain contact holes disposed in an ILD layer according to an embodiment of the invention.

Fig. 10 is a flow chart of fabricating a high electron mobility transistor according to an embodiment of the invention.

Wherein the reference numerals are as follows:

10-1 … high electron mobility transistor

10-2 … high electron mobility transistor

10-3 … high electron mobility transistor

20 … semiconductor structure

102 … substrate

104 … buffer layer

106 … semiconductor channel layer

106a … two-dimensional electron gas region

106b … two-dimensional electron gas interception area

108 … semiconductor barrier layer

109 … semiconductor cap layer

110 … patterned semiconductor cap layer

111 … semiconductor protective layer

110S … side

110T … Top surface

120 … patterned semiconductor protection layer

120B … bottom surface

Side surface of 120S …

122 … first part

124 … second part

124T … Top surface

126 … groove

126B … bottom surface

126S … side surface

128 … Shielding layer

130 … interlayer dielectric layer

132 … gate contact hole

134 … opening holes

140 … gate electrode

140C … bottom corner

142 … first conductive layer

144 … second conductive layer

150 … interlayer dielectric layer

152 … source/drain contact holes

152B … bottom surface

154 … source/drain electrode

156 … source/drain electrodes

160 … passivation layer

200 … method

202 … step

204 … step

206 … step

208 … step

210 … step

Region A …

Width of D1 …

Width D2 …

Width of D3 …

Width of D4 …

T1 … thickness

T2 … thickness

Detailed Description

The present invention provides several different embodiments, which can be used to implement different features of the present invention. Examples of specific components and arrangements are described herein for simplicity of illustration. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of the first feature being formed over or on the second feature may refer to the first feature being in direct contact with the second feature, or to the second feature being in the presence of other features, such that the first feature is not in direct contact with the second feature. Moreover, various embodiments of the present invention may use repeated reference characters and/or written notation. These repeated reference characters and notations are used to make the description more concise and unambiguous and are not used to indicate any relationship between the different embodiments and/or configurations.

In addition, the spatially related words of description referred to in this invention are, for example: the use of "under", "lower", "under", "over", "under", "top", "bottom" and the like in describing, for purposes of convenience, the relative relationship of one element or feature to another element(s) or feature in the drawings. In addition to the orientations shown in the drawings, the spatially relative terms are also used to describe possible orientations of the semiconductor device during use and operation. With respect to the orientation of the semiconductor device (rotated 90 degrees or at other orientations), the spatially relative descriptions used to describe the orientation of the semiconductor device should be interpreted in a similar manner.

Although the present invention has been described using terms such as first, second, third, etc. to describe various elements, components, regions, layers and/or sections, it should be understood that such elements, components, regions, layers and/or sections should not be limited by such terms. These terms are only used to distinguish one element, component, region, layer and/or block from another element, component, region, layer and/or block, and do not denote any order or importance, nor do they denote any order or importance, unless otherwise indicated. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of embodiments of the present invention.

The term "about" or "substantially" as used herein generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate, i.e., the meaning of "about" or "substantially" may be implied without specifically stating "about" or "substantially".

In the present invention, "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the group III element may be boron (B), aluminum (Al), gallium (Ga), or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, the "III-V semiconductor" may include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), the like, or combinations thereof, but is not limited thereto. Furthermore, if desired, the III-V semiconductor may also include dopants therein, such as an N-type or P-type III-V semiconductor having a particular conductivity type.

Although the invention of the present invention is described below by way of specific embodiments, the inventive principles of the present invention may be applied to other embodiments as well. Moreover, certain details may be omitted so as not to obscure the spirit of the invention, the details being within the knowledge of a person of ordinary skill in the art.

The present invention relates to a High Electron Mobility Transistor (HEMT) that may be used as a power switching transistor for voltage converter applications. The III-V HEMT has a wider band gap compared to silicon power transistors, and thus is characterized by low on-state resistance and low switching loss.

Fig. 1 is a schematic cross-sectional view of a High Electron Mobility Transistor (HEMT) according to an embodiment of the present invention. As shown in fig. 1, according to an embodiment of the present invention, a high electron mobility transistor 10-1, such as an enhancement mode high electron mobility transistor, is disposed on a substrate 102, and a semiconductor channel layer 106, a semiconductor barrier layer 108, a patterned semiconductor cap layer 110, a patterned semiconductor passivation layer 120, and an interlayer dielectric layer 130 may be sequentially disposed on the substrate 102, and the interlayer dielectric layer 130 may be disposed with a gate electrode 140. The resistivity of the patterned semiconductor protection layer 120 is between the resistivity of the patterned semiconductor cap layer 110 and the resistivity of the interlayer dielectric layer 130. According to an embodiment of the present invention, the interlayer dielectric layer 130 may cover the patterned semiconductor cap layer 110 and the patterned semiconductor protection layer 120, and a gate contact hole 132 is disposed in the interlayer dielectric layer 130 for accommodating the gate electrode 140. A portion of the patterned semiconductor protection layer 120 is present between the gate electrode 140 and the patterned semiconductor cap layer 110.

According to an embodiment of the invention, an optional buffer layer 104 may be disposed between the substrate 102 and the semiconductor channel layer 106. An interlayer dielectric layer 150 may be selectively disposed over the interlayer dielectric layer 130. At least two source/drain contact holes 152 may penetrate the interlayer

dielectric layers

130, 150 for accommodating at least two source/

drain electrodes

154, 156, respectively.

According to an embodiment of the present invention, the substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrateA plate, a sapphire (sapphire) substrate, a Silicon On Insulator (SOI) substrate, or a Germanium On Insulator (GOI) substrate, but is not limited thereto. In another embodiment, the substrate 102 further comprises one or more layers of insulating material and/or other suitable materials (e.g., semiconductor layers) and a core layer. The layer of insulating material may be an oxide, nitride, oxynitride, or other suitable insulating material. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), zinc oxide (ZnO) or gallium oxide (Ga) ₂ O ₃ ) Or other suitable ceramic material. In one embodiment, a single or multiple layers of insulating material and/or other suitable material surround the core layer.

The buffer layer 104 may be used to reduce the degree of stress or lattice mismatch existing between the substrate 102 and the semiconductor channel layer 106. According to an embodiment of the invention, the buffer layer 104 may include a plurality of sub-semiconductors, and the resistance of the whole buffer layer is higher than the resistance of other layers on the substrate 102. Specifically, the ratio of a portion of the elements in the buffer layer 104, such as the metal element, gradually changes from the substrate 102 to the semiconductor channel layer 106. For example, in the case where the substrate 102 and the semiconductor channel layer 106 are a silicon substrate and an i-GaN layer (intrinsic GaN layer), respectively, the buffer layer 104 may be aluminum gallium nitride (Al) with a graded composition ratio _x Ga _(1-x) N) and in a direction from the substrate 102 toward the semiconductor channel layer 106, the value of X decreases from 0.9 to 0.15 in a continuous or step-wise manner.

The semiconductor channel layer 106 may comprise one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. The semiconductor channel layer 106 may be one or more doped III-V semiconductor layers, such as P-type III-V semiconductor layers. For the P-type III-V semiconductor layer, the dopant may be C, Fe, Mg or Zn, or not limited thereto. The semiconductor barrier layer 108 may comprise one or more group III-V semiconductor layers and may be different in composition from the group III-V semiconductor of the semiconductor channel layer 106. For example, semiconductor barriersLayer 108 may comprise AlN, Al _y Ga _(1-y) N (0 < y < 1), or a combination thereof. According to an embodiment, the semiconductor channel layer 106 may be an undoped GaN layer, and the semiconductor barrier layer 108 may be an AlGaN layer that is N-type in nature. Since the semiconductor channel layer 106 and the semiconductor barrier layer 108 have discontinuous energy gaps therebetween, by stacking the semiconductor channel layer 106 and the semiconductor barrier layer 108 on top of each other, electrons are collected at the heterojunction between the semiconductor channel layer 106 and the semiconductor barrier layer 108 due to piezoelectric effect (piezo effect), thereby generating a thin layer with high electron mobility, i.e., a two-dimensional electron gas (2DEG) region 106 a. In contrast, the region covered by the patterned semiconductor cap layer 110 may be regarded as the two-dimensional electron gas intercepting region 106b because the two-dimensional electron gas is not formed.

The patterned semiconductor cap layer 110 disposed on the semiconductor barrier layer 108 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. The patterned semiconductor cap layer 110 may be one or more doped group III-V semiconductor layers, such as a P-type group III-V semiconductor layer. For the P-type III-V semiconductor layer, the dopant may be C, Fe, Mg or Zn, but is not limited thereto. According to an embodiment of the present invention, the patterned semiconductor cap layer 110 may be a P-type GaN layer.

The patterned semiconductor protection layer 120 substantially completely covers the underlying patterned semiconductor cap layer 110, such that the side edges thereof may be aligned with the underlying patterned semiconductor cap layer 110, or may be slightly recessed or protruded (the length of the recessed or protruded side edges may be 1-10nm, but is not limited thereto). The composition of the patterned semiconductor protection layer 120 is different from that of the patterned semiconductor cap layer 110. According to an embodiment of the present invention, the composition of the patterned semiconductor protection layer 120 may include a silicon-containing semiconductor, such as silicon, silicon carbide, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, metal silicide, or a combination thereof, and the crystalline state of the patterned semiconductor protection layer 120 may be single crystalline (single crystalline), polycrystalline (pol) or a combination thereofycrystaline) or amorphous (amorphus). For example, the patterned semiconductor protection layer 120 may be low temperature polysilicon (low temperature polysilicon). The resistivity of the patterned semiconductor protection layer 120 may be higher than that of the underlying patterned semiconductor cap layer 110, for example, 10 to 1000 Ω · m, and the longitudinal resistance thereof may be 1 × 10 ⁴ To 1x10 ⁶ Ω, e.g. 1x10 ⁴ Ω、1x10 ⁵ Omega or 1x10 ⁶ Ω, but not limited thereto.

The gate electrode 140 may be electrically connected to the lower patterned semiconductor cap layer 110 by schottky contact, and the bottom of the gate electrode 140 may be buried in the patterned semiconductor protection layer 120 but may be longitudinally separated from the lower patterned semiconductor cap layer 110. Thus, the patterned semiconductor protection layer 120 may include a first portion 122 at the periphery and a second portion 124 in the middle. According to an embodiment of the present invention, the gate electrode 140 may have a single-layer structure or a multi-layer structure, such as a double-layer structure including a first conductive layer 142 and a second conductive layer 144. The first conductive layer 142 may directly contact the patterned semiconductor protection layer 120, and may include a schottky contact metal. The Schottky contact metal refers to a metal, an alloy or a stacked layer thereof that can form a Schottky contact (Schottky contact) with the semiconductor layer, and is, for example, TiN, W, Pt, Ni or Ni, but is not limited thereto. The composition of the second conductive layer 144 may include Ti, Al, Au, Mo, but is not limited thereto. According to an embodiment of the present invention, the first conductive layer 142 may include a metal nitride including a refractory metal, and the refractory metal may be selected from the group consisting of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, technetium, rhenium, ruthenium, osmium, rhodium, and iridium.

The interlayer

dielectric layers

130, 150 may be sequentially disposed on the barrier layer 108 and may be made of materials independently selected from Si ₃ N ₄ 、AlN、Al ₂ O ₃ 、SiO ₂ Or a combination of the foregoing, but not limited thereto. The interlayer

dielectric layers

130, 150 may cover the patterned semiconductor protection layer 120, the patterned semiconductor cap layer 110, the semiconductor barrier layer 108, and the semiconductor channel layer 106. Of which the interlayer dielectric layers 130, 150The resistivity may be higher than that of the patterned semiconductor protection layer 120. For example, the resistivity of the interlayer

dielectric layers

130, 150 may be 1x10 ¹⁰ To 1x10 ¹⁶ Ω · m, e.g. 1x10 ¹³ Ω · m, but is not limited thereto.

Source/

drain electrodes

154, 156 may extend through the ild layers 130, 150, respectively, and are electrically connected to the underlying semiconductor barrier layer 108 and semiconductor channel layer 106. According to an embodiment of the present invention, the gate electrode 140 may have a single-layer or multi-layer structure, and may include an ohmic contact metal. The ohmic contact metal refers to a metal, an alloy or a stacked layer thereof that can make ohmic contact (ohmic contact) with the semiconductor layer, such as, but not limited to, Ti/Al/Ti/TiN, Ti/Al/Ti/Au, Ti/Al/Ni/Au or Ti/Al/Mo/Au.

Fig. 2 is an enlarged cross-sectional view of a local area of a high electron mobility transistor according to an embodiment of the invention, which may correspond to the area a shown in the embodiment of fig. 1. As shown in fig. 2, the bottom surface 120B of the patterned semiconductor cap layer 120 may coincide with the top surface 110T of the patterned semiconductor cap layer 110. And the side 120S of the patterned semiconductor protection layer 120 may be substantially aligned with the side 110S of the patterned semiconductor cap layer 110, such that the lateral dimensions of the patterned semiconductor protection layer 120 and the patterned semiconductor cap layer 110, such as the width D2, may be substantially equal to each other. According to an embodiment of the invention, the surface of the patterned semiconductor protection layer 120 may be provided with a groove 126, such that a bottom surface 126B and a side surface 126S of the groove 126 may coincide with the surface of the patterned semiconductor protection layer 120. A lateral dimension of the groove 126, such as the width D1, may be smaller than the width D2 of the patterned semiconductor cap layer 110, such that the first portion 122 of the patterned semiconductor protection layer 120 may be adjacent to a periphery of the groove 126, and the second portion 124 of the patterned semiconductor protection layer 120 may be disposed directly below the groove 126. Wherein a lateral dimension, such as a width, of each first portion 122 located at a periphery of the groove 126 may be a width D3, D4, respectively. For example, the widths D3, D4 may be 20 to 350nm, and the widths D3, D4 may be the same as or different from each other, but are not limited thereto. Further, a thickness T1 of first portion 122 may be greater than a thickness T2 of second portion 124. For example, the thickness T2 may be 10 to 100nm, but is not limited thereto. The lower portion of the gate electrode 140 may fill the groove 126 and have a width D1, and at least one bottom corner 140C of the gate electrode 140 may directly contact the patterned semiconductor protection layer 120 or be further covered by the patterned semiconductor protection layer 120.

According to the embodiment of the invention, since the resistivity of the patterned semiconductor protection layer 120 is higher than that of the upper gate electrode 140, the patterned semiconductor protection layer 120 does not generate the tip discharge even though the lateral side 120S of the patterned semiconductor protection layer 120 is not etched, thereby preventing the unnecessary gate leakage current. Furthermore, since the width D2 of the patterned semiconductor passivation layer 120 may be substantially the same as the width D2 of the patterned cap layer, good electrical uniformity between semiconductor devices may be maintained even though the semiconductor devices are produced in different batches. In addition, since the bottom corner 140C of the gate electrode 140 can be covered by the patterned semiconductor protection layer 120 with relatively high resistivity, the patterned semiconductor protection layer 120 can be used to buffer the high voltage electric field from the bottom corner 140C of the gate electrode 140, thereby improving the stability of the semiconductor device.

Fig. 3 is an enlarged cross-sectional view of a partial region of a hemt according to a variation of the present invention. The high electron mobility transistor 10-2 shown in the embodiment of fig. 3 is substantially the same as the high electron mobility transistor 10-1 shown in the embodiment of fig. 2, and the main difference between the two is that the bottom surface of the gate electrode 140 of the high electron mobility transistor 10-2 is not embedded in the patterned semiconductor protection layer 120. Therefore, the thickness T1 of the patterned semiconductor layer 120 is constant regardless of whether the thickness T1 is located around or directly under the gate electrode 140. In addition, since the distance between the gate electrode 140 and the patterned semiconductor cap layer 110 is equal to the thickness T1 of the patterned semiconductor layer 120, in order to avoid an excessive resistance between the gate electrode 140 and the patterned semiconductor cap layer 110, the thickness T1 of the patterned semiconductor layer 120 may be 10 to 100 nm.

FIG. 4 is a variation of the present inventionA cross-sectional view of the hemt of the embodiment. The hemt 10-3 shown in the embodiment of fig. 4 is substantially the same as the hemt 10-1 shown in the embodiment of fig. 1, and the main difference between the two is that a passivation layer 160 is additionally disposed between the interlayer dielectric layer 130 and the semiconductor barrier layer 108, the patterned semiconductor cap layer 110, and the patterned semiconductor passivation layer 120 of the hemt 10-3. The passivation layer 160 may be used to eliminate or reduce surface defects existing on the top surface of the semiconductor barrier layer 108, the side surface 110S of the patterned semiconductor cap layer 110, and the side surface 120S of the patterned semiconductor protection layer 120, thereby improving the electrical performance of the hemt 10-3. According to an embodiment of the present invention, the passivation layer 160 has a higher resistivity than the patterned semiconductor protection layer 120, and the passivation layer 160 may be composed of silicon nitride (Si) ₃ N ₄ ) Silicon oxynitride (SiON), aluminum nitride (AlN), and aluminum oxide (Al) ₂ O ₃ ) Or silicon oxide (SiO) ₂ ) But is not limited thereto.

In order to enable those skilled in the art to implement the present invention, the method for fabricating the high electron mobility transistor of the present invention is further described in detail below.

Fig. 5 is a cross-sectional view of a high electron mobility transistor according to an embodiment of the invention, wherein the high electron mobility transistor comprises sequentially stacked semiconductor layers. Fig. 10 is a flow chart of fabricating a high electron mobility transistor according to an embodiment of the invention. According to an embodiment of the present invention, step 202 of the method 200 may be performed to provide a substrate on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, and a semiconductor protection layer are sequentially disposed. As shown in fig. 5, a buffer layer 104, a semiconductor channel layer 106, a semiconductor barrier layer 108, a semiconductor cap layer 109, and a semiconductor protection layer 111 may be sequentially disposed on a substrate 102 in a semiconductor structure 20. The stacked layers on the substrate 102 may be formed by any suitable method, such as molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Atomic Layer Deposition (ALD), or other suitable methods.

Fig. 6 is a schematic cross-sectional view illustrating the fabrication of a hemt according to an embodiment of the present invention, which includes a patterned semiconductor cap layer, a patterned semiconductor protection layer, and a shielding layer. According to an embodiment of the invention, after the steps shown in the embodiment of fig. 5, photolithography and etching processes may be performed to form the mask layer 128 with a feature pattern. Then, step 204 is performed to etch the semiconductor cap layer and the semiconductor protection layer to form a patterned semiconductor cap layer and a patterned semiconductor protection layer. For example, an etching process may be performed to sequentially remove the semiconductor protection layer 111 and the semiconductor cap layer 109 exposed by the mask layer 128 by using the mask layer 128 as an etching mask, thereby forming the patterned semiconductor protection layer 120 and the patterned semiconductor cap layer 110. According to an embodiment of the present invention, since the feature pattern defined by the mask layer 128 is transferred to the underlying semiconductor protection layer 111 and the underlying semiconductor cap layer 109 by the vertical anisotropic etching, the mask layer 128, the patterned semiconductor protection layer 120, and the patterned semiconductor cap layer 110 may have substantially the same lateral dimension, such as the width D2. Therefore, the side 128S of the shielding layer 128, the side 110S of the patterned semiconductor cap layer 110, and the side 120S of the patterned semiconductor protection layer 120 may be substantially aligned with each other. In addition, for the area not covered by the patterned semiconductor cap layer 110, the two-dimensional electron gas can be formed in the two-dimensional electron gas area 106a due to the piezoelectric effect generated between the semiconductor channel layer 106 and the semiconductor barrier layer 108. In contrast, the region covered by the patterned semiconductor cap layer 110 may be regarded as the two-dimensional electron gas intercepting region 106b because no two-dimensional electron gas is formed.

After the patterned semiconductor protection layer 120 and the patterned semiconductor cap layer 110 are manufactured, the shielding layer 128 may be removed to expose the top surface of the patterned semiconductor protection layer 120.

FIG. 7 illustrates the fabrication of high electron mobility device according to one embodiment of the present inventionThe transistor includes a gate contact hole disposed in an interlayer dielectric layer. In step 206, an inter-layer dielectric layer is formed to cover the patterned semiconductor cap layer and the patterned semiconductor protection layer. For example, the interlayer dielectric layer 130 may be formed by a suitable deposition process to completely cover the patterned semiconductor protection layer 120, the patterned semiconductor cap layer 110, the semiconductor barrier layer 108, and the semiconductor channel layer 106. Before removing the mask layer 128 and after forming the interlayer dielectric layer 130, the width D2 of the patterned semiconductor protection layer 120 may remain constant, so that the side 110S of the patterned semiconductor cap layer 110 and the side 120S of the patterned semiconductor protection layer 120 may be substantially aligned with each other. The material of the interlayer dielectric layer 130 may be Si ₃ N ₄ 、AlN、Al ₂ O ₃ Or SiO ₂ However, the present invention is not limited thereto.

Next, in step 208, a gate contact hole is formed in the inter-layer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protection layer and is separated from the patterned semiconductor cap layer. For example, photolithography and etching processes may be performed to sequentially form the opening 134 in the interlayer dielectric layer 130 and the recess 126 on the surface of the patterned semiconductor protection layer 120. Wherein the opening 134 and the recess 126 may form a gate contact hole 132. Therefore, the patterned semiconductor protection layer 120 may be exposed from the gate contact hole 126. The width D1 of the gate contact hole 126 may be smaller than the width D2 of the patterned semiconductor protection layer 120. The bottom surface 126B of the gate contact hole 126 may be located in the patterned semiconductor protection layer 120 and separated from the patterned semiconductor cap layer 110. Accordingly, the top surface 122T of the first portion 122 of the patterned semiconductor protection layer 120 may be higher than the top surface 124T of the second portion 124. According to an embodiment of the present invention, the etching process for forming the gate contact hole 132 may include a dry etching process, such as a plasma etching process. Since the bottom surface of the gate contact hole 132 does not penetrate the patterned semiconductor protection layer 120 during the etching process, the high-energy etchant (e.g., plasma etchant) can be prevented from contacting the patterned semiconductor cap layer 110, and the original electrical characteristics of the patterned semiconductor cap layer 110 can be maintained.

Fig. 8 is a cross-sectional view of a high electron mobility transistor according to an embodiment of the present invention, including a gate electrode. According to an embodiment of the present invention, after the steps shown in FIG. 7, step 210 may be performed to form a gate electrode in the gate contact hole, wherein a portion of the patterned semiconductor protection layer exists between the gate electrode and the patterned semiconductor cap layer. For example, a suitable deposition process may be performed to form one or more conductive layers (not shown) on the top surface of the ILD 130 and within the gate contact hole 132. Then, photolithography and etching processes are performed to pattern the conductive layer, thereby forming the gate electrode 140. According to an embodiment of the present invention, for the gate contact hole 132 with a smaller opening area, the gate electrode 140 may completely fill the gate contact hole 132, but is not limited thereto. According to an embodiment of the present invention, the gate electrode 140 may also be disposed only along the inner wall of the gate contact hole 132 without filling the gate contact hole 132. Then, an additional interlayer dielectric layer or passivation layer, such as an interlayer dielectric layer 150, is formed on the interlayer dielectric layer 130 to cover the gate electrode 140.

FIG. 9 is a cross-sectional view of an embodiment of the present invention showing the fabrication of a HEMT including source/drain contact holes in an IMD layer. As shown in fig. 9, at least one source/drain contact hole, such as two separated source/drain contact holes 152, may be formed on both sides of the gate electrode 140 by performing photolithography and etching processes. When the etching process is completed, the bottom surface 152B of each source/drain contact hole 152 may be located in the semiconductor barrier layer 108 or further extend into the semiconductor channel layer 106 to expose the semiconductor channel layer 106. In addition, since the bottom surface 152B of the source/drain contact hole 152 may be located in the semiconductor channel layer 108 or the semiconductor channel layer 106, a two-dimensional electron gas blocking region 106B is formed below each source/drain contact hole 152.

Subsequently, a suitable deposition process may be performed to form a single or multiple layers of conductive layers (not shown) on the top surface of the interlayer dielectric layer 150 and within the source/drain contact holes 152. Thereafter, photolithography and etching processes are performed to pattern the conductive layer to form source/

drain electrodes

154, 156 similar to those shown in FIG. 1.

The above description is only a preferred embodiment of the present invention, and all the equivalent changes and modifications made by the claims of the present invention should fall within the protection scope of the present invention.

Claims

1. A high electron mobility transistor, comprising:

a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate;

a patterned semiconductor protection layer disposed on the semiconductor barrier layer;

a patterned semiconductor cap layer disposed between the patterned semiconductor protection layer and the semiconductor barrier layer;

an interlayer dielectric layer covering the patterned semiconductor cover layer and the patterned semiconductor protection layer, wherein the interlayer dielectric layer comprises a gate contact hole; and

a gate electrode disposed in the gate contact hole and electrically connected to the patterned semiconductor cap layer, wherein a portion of the patterned semiconductor protection layer is present between the gate electrode and the patterned semiconductor cap layer,

wherein the resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor cover layer and the resistivity of the interlayer dielectric layer.

2. The hemt of claim 1, wherein sides of said patterned semiconductor protection layer are aligned with sides of said patterned semiconductor cap layer.

3. The hemt of claim 1, wherein said gate contact hole has a width less than a width of said patterned semiconductor protection layer.

4. The hemt of claim 1, wherein said gate electrode and said semiconductor cap layer are electrically connected by a schottky contact.

5. The hemt of claim 1, wherein said patterned semiconductor protection layer has a lower resistivity than said gate electrode.

6. The hemt of claim 1, wherein said gate electrode directly contacts said patterned semiconductor protection layer.

7. The hemt of claim 6, wherein said gate electrode comprises a bottom corner, said bottom corner directly contacting said patterned semiconductor protection layer.

8. The hemt of claim 1, wherein:

the composition of the patterned semiconductor cover layer is a P-type III-V semiconductor;

the patterned semiconductor protection layer is composed of a silicon-containing semiconductor; and

the gate electrode comprises a metal.

9. The hemt of claim 1, wherein said surface of said patterned semiconductor protection layer comprises a recess, and said gate electrode fills said recess.

10. The hemt of claim 9, wherein said patterned semiconductor protection layer comprises at least a first portion and a second portion, said at least a first portion is disposed at the periphery of said recess, said second portion is disposed under said recess, and the thickness of said at least a first portion is greater than the thickness of said second portion.

11. The hemt of claim 1, further comprising a passivation layer disposed homeotropically on a top surface of said barrier semiconductor layer, on side surfaces of said patterned cap semiconductor layer, and on side surfaces and a top surface of said patterned protective semiconductor layer.

12. A method for fabricating a high electron mobility transistor, comprising:

providing a substrate, on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer and a semiconductor protection layer are sequentially disposed;

etching the semiconductor cover layer and the semiconductor protection layer to form a patterned semiconductor cover layer and a patterned semiconductor protection layer;

forming an interlayer dielectric layer covering the patterned semiconductor cover layer and the patterned semiconductor protection layer;

forming a gate contact hole in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protection layer and is separated from the patterned semiconductor cover layer; and

forming a gate electrode in the gate contact hole, wherein a portion of the patterned semiconductor protection layer is present between the gate electrode and the patterned semiconductor cap layer,

13. The method of claim 12, further comprising forming a mask layer over the semiconductor protection layer before etching the semiconductor cap layer and the semiconductor protection layer, wherein the semiconductor cap layer and the semiconductor protection layer exposed by the mask layer are removed during etching the semiconductor cap layer and the semiconductor protection layer.

14. The method of claim 13, further comprising removing the mask layer before forming the interlayer dielectric layer, wherein a width of the patterned semiconductor protection layer remains constant before removing the mask layer and after forming the interlayer dielectric layer.

15. The method of claim 14, wherein a side of the patterned semiconductor protection layer is aligned with a side of the patterned semiconductor cap layer before the mask layer is removed and after the interlayer dielectric layer is formed.

16. The method of claim 12, wherein the step of forming the gate contact hole in the interlayer dielectric layer comprises performing photolithography and etching processes.

17. The method of claim 12, wherein the patterned semiconductor protection layer has a resistivity lower than that of the gate electrode.

18. The method of claim 12, wherein the gate electrode directly contacts the patterned semiconductor protection layer.

19. The method of claim 12, wherein after forming the gate electrode, the surface of the patterned semiconductor protection layer comprises a recess, and the gate electrode fills the recess.

20. The method of claim 19, wherein after the gate electrode is formed, the patterned semiconductor protection layer comprises at least a first portion and a second portion, the at least a first portion is disposed at a periphery of the recess, the second portion is disposed under the recess, and a thickness of the at least a first portion is greater than a thickness of the second portion.