CN115513276A - Semiconductor structure and high electron mobility transistor - Google Patents

Semiconductor structure and high electron mobility transistor Download PDF

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Publication number
CN115513276A
CN115513276A CN202110693710.7A CN202110693710A CN115513276A CN 115513276 A CN115513276 A CN 115513276A CN 202110693710 A CN202110693710 A CN 202110693710A CN 115513276 A CN115513276 A CN 115513276A
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layer
graded
same group
compound semiconductor
barrier layer
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陈志谚
王端玮
卢钒达
陈俊扬
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
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  • General Physics & Mathematics (AREA)
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  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a compositional gradient layer. The buffer layer is arranged on the substrate, the channel layer is arranged on the buffer layer, the barrier layer is arranged on the channel layer, the doped compound semiconductor layer is arranged on the barrier layer, and the composition gradient layer is arranged between the barrier layer and the doped compound semiconductor layer, wherein the barrier layer and the composition gradient layer comprise a same third group element and a same fifth group element, and the atomic percentage of the same third group element in the composition gradient layer is gradually increased from the barrier layer to the doped compound semiconductor layer. In addition, a high electron mobility transistor comprising the semiconductor structure is also provided.

Description

Semiconductor structure and high electron mobility transistor
[ technical field ] A
The present disclosure relates to the field of semiconductor devices, and more particularly, to a semiconductor structure and a high electron mobility transistor including the same.
[ background of the invention ]
In semiconductor technology, III-V compound semiconductors are used to form a variety of integrated circuit devices, such as: a high power field effect transistor, a high frequency transistor, or a High Electron Mobility Transistor (HEMT). A HEMT is a transistor having a two-dimensional electron gas (2-DEG), the 2-DEG being adjacent to a junction (i.e., a heterojunction) between two materials having different band gaps. Because HEMTs do not use doped regions as the carrier channel of transistors, but 2-DEG as the carrier channel of transistors, HEMTs have a number of attractive characteristics compared to conventional metal-oxide-semiconductor field effect transistors (MOSFETs), such as: high electron mobility and the ability to transmit signals at high frequencies. For conventional HEMTs, channel layers, barrier layers, cap layers, and gate electrodes may be included in sequential stacks. The bias voltage is applied to the cover layer by using the grid electrode, so that the concentration of the two-dimensional electron gas in the channel layer below the cover layer can be regulated and controlled, and the switch of the HEMT can be regulated and controlled.
Since the dielectric layer above the barrier layer and the channel layer has a compressive stress, the surface of the channel layer and the surface of the barrier layer are usually made to have a polarity by a piezoelectric effect (piezo effect) and cause a surface leakage phenomenon of the HEMT, thereby reducing the electrical performance of the HEMT.
[ summary of the invention ]
Accordingly, there is a need for an improved HEMT for improving the electrical performance of the HEMT.
According to an embodiment of the present disclosure, a semiconductor structure is provided, which includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is arranged on the substrate, the channel layer is arranged on the buffer layer, the barrier layer is arranged on the channel layer, the doped compound semiconductor layer is arranged on the barrier layer, and the composition gradient layer is arranged between the barrier layer and the doped compound semiconductor layer, wherein the barrier layer and the composition gradient layer comprise a same third group element and a same fifth group element, and the atomic percentage of the same third group element in the composition gradient layer is gradually increased from the barrier layer to the doped compound semiconductor layer.
According to an embodiment of the present disclosure, a high electron mobility transistor is provided, which includes the semiconductor structure, the gate electrode, the source electrode, the drain electrode and the passivation layer. The gate electrode is disposed on the doped compound semiconductor layer, the source electrode and the drain electrode are disposed on both sides of the gate electrode, respectively, and the passivation layer covers the gate electrode, the source electrode and the drain electrode.
In order to make the features of the present disclosure comprehensible, embodiments accompanied with figures are described in detail below.
[ description of the drawings ]
For the following to be more readily understood, reference is made to the drawings and to the detailed description thereof, when reading this disclosure. Through the embodiments herein and with reference to the accompanying drawings, the embodiments of the present disclosure are explained in detail and the operation principle of the embodiments of the present disclosure is illustrated. Furthermore, for purposes of clarity, the various features in the drawings may not be to scale and the dimensions of some of the features in some drawings may be exaggerated or minimized.
Fig. 1 is a schematic cross-sectional view of a High Electron Mobility Transistor (HEMT) according to an embodiment of the present disclosure.
Fig. 2, 3, and 4 are concentration curves of atomic percentages of the same group iii element, such as aluminum (Al), in compositionally graded and barrier layers of high electron mobility transistors according to various embodiments of the present disclosure.
Fig. 5 is a schematic cross-sectional view of a hemt according to an embodiment of the present disclosure.
Fig. 6 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure.
Fig. 7 is a cross-sectional view of an intermediate stage in the fabrication of a hemt according to an embodiment of the present disclosure, including a doped compound semiconductor layer disposed on a compositionally-graded layer.
Fig. 8 is a cross-sectional view of an intermediate stage in the fabrication of a hemt according to an embodiment of the present disclosure, including an isolation region disposed at the periphery.
Fig. 9 is a cross-sectional view of an intermediate stage of fabricating a high electron mobility transistor according to an embodiment of the present disclosure, wherein the intermediate stage includes a source electrode and a drain electrode.
Fig. 10 is a cross-sectional view of an intermediate stage in the fabrication of a high electron mobility transistor, including a gate contact hole, according to an embodiment of the present disclosure.
[ embodiment ] A method for producing a semiconductor device
The present disclosure provides several different embodiments, which can be used to implement different features of the present disclosure. For simplicity of explanation, this disclosure also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of the first feature being formed over or on the second feature may refer to the first feature being in direct contact with the second feature, or to the second feature being in the presence of other features, such that the first feature is not in direct contact with the second feature. Moreover, various embodiments in the present disclosure may use repeated reference symbols and/or textual labels. These repeated reference characters and notations are used to make the description more concise and unambiguous and are not used to indicate any relationship between the different embodiments and/or configurations.
In addition, for spatially related words of description mentioned in this disclosure, for example: the use of "under", "lower", "under", "over", "under", "top", "bottom" and the like in describing, for purposes of convenience, the relative relationship of one element or feature to another element(s) or feature in the drawings. In addition to the orientations shown in the drawings, these spatially relative terms are also used to describe possible orientations of the semiconductor device during use and operation. With respect to the swinging direction of the semiconductor device (rotated 90 degrees or other orientations), the spatially relative descriptions for describing the swinging direction should be interpreted in a similar manner.
Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers and/or sections, it should be understood that these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or block from another element, component, region, layer and/or block, and do not denote any order or importance, nor do they denote any order or importance, unless otherwise indicated. Thus, a first element, component, region, layer or block discussed below could be termed a second element, component, region, layer or block without departing from the scope of embodiments of the present disclosure.
The term "about" or "substantially" as referred to in this disclosure generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate, i.e., the meaning of "about" or "substantially" may be implied without specifically stating "about" or "substantially".
In the present disclosure, "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Wherein the group III element may be boron (B), aluminum (Al), gallium (Ga), or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, the "iii-v semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor, or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (inaas), gallium indium arsenide (InGaAs), the like, or combinations thereof, but is not limited thereto. Furthermore, if desired, the iii-v semiconductor may also include dopants, and is a iii-v semiconductor with a specific conductivity type, such as an n-type or p-type iii-v semiconductor. Hereinafter, the III-V semiconductor may also be referred to as a III-V semiconductor.
Although the invention of the present disclosure is described below in terms of specific embodiments, the inventive principles of the present disclosure can be applied to other embodiments as well. Moreover, certain details have been left out in order not to obscure the spirit of the invention, which details are within the knowledge of a person of ordinary skill in the art.
The present disclosure relates to a semiconductor structure, and a High Electron Mobility Transistor (HEMT) including the semiconductor structure, which may be used as a power switching transistor for a voltage converter application. Group III-V semiconductor HEMTs (III-V HEMTs) are characterized by low on-state resistance and low switching loss due to their wider band gap compared to silicon power transistors.
Fig. 1 is a schematic cross-sectional view of a High Electron Mobility Transistor (HEMT) according to an embodiment of the present disclosure. As shown in fig. 1, according to an embodiment of the present disclosure, a high electron mobility transistor 100-1, such as an enhancement mode high electron mobility transistor, is disposed on a substrate 102, and a buffer layer, a channel layer 110, a barrier layer 112, a composition gradient layer (composition gradient layer) 114, a doped compound semiconductor layer 116, and a passivation layer (passivation layer) 120 may be sequentially disposed on the substrate 102. In one embodiment, the buffer layer includes a nucleation layer (104), a Superlattice Layer (SL) 106, a high resistance layer (108), or a combination thereof. Wherein the doped compound semiconductor layer 116 is disposed on the composition-graded layer 114, and is in contact with the composition-graded layer 114. The passivation layer 120 is in contact with the compositionally-graded layer 114, and the doped compound semiconductor layer 116 is buried in the passivation layer 120. In one embodiment, the passivation layer 120 contacts a portion of the top surface of the graded layer 114.
In addition, the hemt 100-1 further comprises a gate electrode 126, a source electrode 122 and a drain electrode 124, wherein the gate electrode 126 is disposed on the doped compound semiconductor layer 116 and covered by the passivation layer 120 or penetrates through the passivation layer 120, and the source electrode 122 and the drain electrode 124 are respectively disposed on two sides of the gate electrode 126 and covered by the passivation layer 120. According to one embodiment, the source electrode 122 and the drain electrode 124 extend down through the compositional gradient layer 114 and the barrier layer 112 to a depth location in the channel layer 110, at a distance from the high resistance layer 108. According to another embodiment, the source electrode 122 and the drain electrode 124 may extend from the passivation layer 120 down through the composition graded layer 114 to a depth location in the barrier layer 112, such as near the bottom location of the barrier layer 112. In addition, the isolation region 118 is disposed at the periphery of the source electrode 122 and the drain electrode 124 to isolate the adjacent devices, the isolation region 118 penetrates through the composition gradient layer 114 and the barrier layer 112 to a depth position in the channel layer 110, and the bottom of the isolation region 118 is lower than the bottoms of the source electrode 122 and the drain electrode 124, so that the isolation region 118 is closer to the high resistance layer 108 than the source electrode 122 and the drain electrode 124, thereby achieving a good electrical isolation effect, but the invention is not limited thereto.
According to an embodiment of the present disclosure, the channel layer 110 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, alGaN, inGaN, or InAlGaN, but is not limited thereto. In addition, the channel layer 110 may be one or more undoped or doped III-V semiconductor layers, and the doped channel layer 110 may be, for example, a p-type III-V semiconductor layer, and the dopant of the p-type III-V semiconductor layer may be, but is not limited to, carbon (C), iron (Fe), magnesium (Mg), or zinc (Zn). The barrier layer 112 may comprise one or more III-V semiconductor layers and may be different in composition from the III-V semiconductor of the channel layer 110. For example, the barrier layer 112 may comprise AlN, al z Ga (1-z) N (0 < z < 1), or a combination thereof. The material of the doped compound semiconductor layer 116 includes a doped compound semiconductor material, for example, gaN doped with a p-type dopant or an n-type dopant. According to one embodiment, the channel layer 110 may be an undoped GaN layer, and the barrier layer 112 may be an essentially n-type AlGaN layer. Since the channel layer 110 and the barrier layer 112 have discontinuous energy gaps therebetween, by stacking the channel layer 110 and the barrier layer 112 on top of each other, electrons are collected at the heterojunction between the channel layer 110 and the barrier layer 112 due to the piezoelectric effect, thereby generating a thin layer with high electron mobility, i.e., a two-dimensional electron gas (2-DEG) region 130. For normally off (normal off) assemblies,when no voltage is applied to the gate electrode 126, the region covered by the doped compound semiconductor layer 116 does not form a 2-DEG, which may be considered as a 2-DEG cut-off region, and no conduction occurs between the source electrode 122 and the drain electrode 124. When a positive voltage is applied to the gate electrode 126, the region covered by the doped compound semiconductor layer 116 forms a 2-DEG such that the 2-DEG region 130 between the source electrode 122 and the drain electrode 124 is continuous to allow conduction between the source electrode 122 and the drain electrode 124. The present disclosure, however, is not limited to normally off (normal off) assemblies. In a normally-on (normal open) device, when a voltage is applied to the gate electrode 126, the region covered by the doped compound semiconductor layer 116 does not form a 2-DEG, which can be regarded as a 2-DEG cut-off region, and no conduction occurs between the source electrode 122 and the drain electrode 124.
According to an embodiment of the present disclosure, a composition gradient layer 114 is disposed between the passivation layer 120 and the barrier layer 112, and between the doped compound semiconductor layer 116 and the barrier layer 112, the composition gradient layer 114 is disposed on the surface of the barrier layer 112 in a forward direction, and the composition gradient layer 114 covers the entire surface of the barrier layer 112 between the source electrode 122 and the drain electrode 124. According to an embodiment, the barrier layer 112 and the composition-graded layer 114 include a same group iii element and a same group v element, and the atomic percentage of the same group iii element in the composition-graded layer 114 gradually increases from the barrier layer 112 to the passivation layer 120, i.e., the atomic percentage of the same group iii element in the composition-graded layer 114 gradually increases from bottom to top in the depth direction.
According to the embodiment of the present disclosure, the composition-graded layer 114 can reduce or eliminate the positive polarity of the surface of the barrier layer 112 due to the surface polarization, and gradually increase the lowest conduction band energy level (Ec) of the composition-graded layer 114 from the side close to the barrier layer 112 to the side close to the passivation layer 120, thereby preventing a potential well (potential well) from being generated between the passivation layer 120 and the barrier layer 112. By eliminating the potential well, electrons can be prevented from flowing in the potential well, thereby preventing the surface leakage current of HEMT, improving the electrical performance of HEMT, and maintaining the 2-DEG performance of HEMT. In addition, the composition gradient layer 114 can also improve the etching process tolerance of the doped compound semiconductor layer 116 formed on the composition gradient layer 114, thereby improving the manufacturing yield of the HEMT.
However, in an example of an embodiment, the High Electron Mobility Transistor (HEMT) does not have the composition gradient layer 114, because of the compressive stress in the passivation layer and the positive charge (or positive polarity) generated by the surface polarization of the barrier layer, a potential well (potential well) is generated between the barrier layer and the passivation layer, and a parasitic channel (parasitic channel) is generated between the passivation layer and the barrier layer, so that a surface leakage current is generated between the gate electrode and the source electrode and between the gate electrode and the drain electrode. This surface leakage current phenomenon can cause the on-off switch of the HEMT to be difficult to control, and thus the electrical performance of the HEMT is affected.
According to an embodiment of the present disclosure, the overall atomic percentage of the same group iii element in the composition graded layer 114 is higher than the atomic percentage of the same group iii element in the barrier layer 112. According to one embodiment, the barrier layer 112 may comprise a ternary III-V compound semiconductor, such as aluminum gallium nitride (Al) z Ga (1-z) N, wherein 0<z<1) Wherein z is a fixed value; compositionally graded layer 114 may comprise a ternary or quaternary III-V compound semiconductor, such as aluminum gallium nitride (Al) x Ga (1-x) N, wherein 0.2<x<0.4 Or aluminum gallium indium nitride (Al) x Ga (1-x-y) InyN, wherein 0.2<x<0.6，0<y<0.4 X and y are values that vary with depth, and the same group iii element is aluminum (Al) and the same group v element is nitrogen (N). According to an embodiment, the atomic percentage of aluminum (Al) in the composition graded layer 114 gradually increases from the barrier layer 112 to the passivation layer 120, i.e., the atomic percentage of aluminum (Al) in the composition graded layer 114 gradually increases from bottom to top in the depth direction. In addition, the atomic percentages of other group iii elements, such as gallium (Ga) and indium (In), in the composition gradient layer 114 gradually decrease from the barrier layer 112 to the passivation layer 120, i.e., the atomic percentages of other group iii elements In the composition gradient layer 114 decrease from the depth directionDecreasing from bottom to top. According to an embodiment, the thickness of the compositionally-graded layer 114 is 10% to 50% of the thickness of the barrier layer 112, and the compositionally-graded layer 114 in this thickness range does not affect the 2-DEG performance of the HEMT and can protect the barrier layer 112 thereunder during the etching process for forming the doped compound semiconductor layer 116.
Fig. 2, 3 and 4 are graphs of atomic percentages of the same group iii element, such as aluminum (Al), in the compositionally-graded and barrier layers of a High Electron Mobility Transistor (HEMT) according to various embodiments of the present disclosure. In fig. 2, the horizontal axis represents the positions of the compositionally-graded layer 114 and the barrier layer 112 in the depth direction, and the vertical axis represents the atomic percent of aluminum (Al), according to an embodiment, as shown in fig. 2, the atomic percent of aluminum (Al) in the barrier layer 112 is a fixed value C1, and the atomic percent of aluminum (Al) in the compositionally-graded layer 114 increases from the value C1 to the value C2 in the depth direction, wherein the value C1 is about 20% and the value C2 is about 40%, and the concentration variation curve may be a straight line 201. In other embodiments, the atomic percentage of aluminum (Al) in the composition graded layer 114 may also be gradually increased from other values lower than the value C1 as the starting value to the value C2. According to an embodiment of the present disclosure, the overall atomic percentage of aluminum (Al) in the composition graded layer 112 is higher than the atomic percentage of aluminum (Al) in the barrier layer 114, i.e., the average atomic percentage of aluminum (Al) in the composition graded layer 112 is higher than the average atomic percentage of aluminum (Al) in the barrier layer 114.
The embodiment of fig. 3 differs from fig. 2 in that the concentration of aluminum (Al) in the graded layer 114 gradually increases from a value C1 to a value C2 from bottom to top in the depth direction, which may be an arc 202, and other similar parts can be found in the description of fig. 2.
The difference between the embodiment of fig. 4 and fig. 2 is that the concentration of aluminum (Al) in the graded layer 114 gradually increases from a value C1 to a value C2 from bottom to top in the depth direction, which may be a step-shaped curve 203, and other similar parts can be referred to the description of fig. 2. In another embodiment, the stepped curve 203 may be a wavy curve.
In addition, according to an embodiment of the present disclosure, the composition graded layer 114 may contain a metal dopant, which may be, but is not limited to, magnesium (Mg), cadmium (Cd), carbon (C), zinc (Zn), iron (Fe), or a combination thereof. In one embodiment, the composition graded layer 114 may be doped with magnesium (Mg) to be a p-type composition graded layer. Also, according to an embodiment of the present disclosure, the atomic percentage of aluminum (Al) in the barrier layer 112 is not limited to a fixed value, and the concentration thereof may slightly vary along the depth direction.
Fig. 5 is a schematic cross-sectional view of the HEMT 100-2 according to an embodiment of the present disclosure. The difference between the HEMT 100-2 of the embodiment of fig. 5 and the HEMT 100-1 of the embodiment of fig. 1 is that a cap layer 115 is further disposed between the compositionally-graded layer 114 and the passivation layer 120, and between the compositionally-graded layer 114 and the doped compound semiconductor layer 116, the cap layer 115 is disposed on the surface of the compositionally-graded layer 114 in a homeotropic manner, and the cap layer 115 covers the entire surface of the compositionally-graded layer 114 between the source electrode 122 and the drain electrode 124, wherein the passivation layer 120 contacts the top surface of the cap layer 115. According to an embodiment, the composition of the cap layer 115 may include the same group iii element and the same group v element in the barrier layer 112 and the composition graded layer 114, for example, the cap layer 115 may be an aluminum nitride (AlN) layer. In an embodiment, the average atomic concentration of the same group iii element of the cap layer 115 is higher than the average atomic concentration of the same group iii element of the composition graded layer 114, for example, the average atomic concentration of aluminum (Al) of the cap layer 115 is higher than the average atomic concentration of aluminum (Al) of the composition graded layer 114. In an embodiment, the atomic percent of the same group iii element of the cap layer 115 is higher than the atomic percent of the same group iii element of the graded layer 114, e.g., the atomic percent of aluminum (Al) of the cap layer 115 is higher than the atomic percent of aluminum (Al) of the graded layer 114. In addition, according to an embodiment, the cap layer 115 may further include a metal dopant, which may be magnesium (Mg), cadmium (Cd), carbon (C), zinc (Zn), iron (Fe), or a combination thereof, but is not limited thereto, for example, the cap layer 115 may be doped with magnesium (Mg) to form a p-type cap layer. According to an embodiment, in the case that the average atomic concentration of the same group iii element in the cap layer 115 is higher than the average atomic concentration of the same group iii element in the composition graded layer 114, the thickness of the cap layer 115 is 2% to 10% of the thickness of the composition graded layer 114, the cap layer 115 in this thickness range does not affect the electrical performance of the HEMT, and the composition graded layer 114 located thereunder can be protected during the etching process for forming the doped compound semiconductor layer 116. In contrast, when the thickness of the cap layer 115 exceeds 20% of the thickness of the graded composition layer 114, the graded composition layer 114 adjacent to the bottom surface of the cap layer 115 further generates 2-DEG, which affects the electrical performance of the HEMT.
Fig. 6 is a cross-sectional view of a semiconductor structure 100 according to an embodiment of the disclosure, and fig. 7, 8, 9 and 10 are cross-sectional views of intermediate stages in the fabrication of a high electron mobility transistor 100-1 according to an embodiment of the disclosure. According to an embodiment of the present disclosure, as shown in fig. 6, a substrate 102 is provided, on which a nucleation layer 104, a superlattice layer 106, a high resistance layer 108, a channel layer 110, a barrier layer 112, a composition gradient layer 114 and a doped compound semiconductor layer 116 are sequentially formed. According to an embodiment, the substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire (sapphire) substrate, a Silicon On Insulator (SOI) substrate, or a Germanium On Insulator (GOI) substrate, but is not limited thereto. In another embodiment, the substrate 102 further comprises one or more layers of insulating material and/or other suitable materials (e.g., semiconductor layers) and a core layer. The layer of insulating material may be an oxide, nitride, oxynitride, or other suitable insulating material. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al) 2 O 3 ) Aluminum gallium nitride (AlGaN), zinc oxide (ZnO) or gallium oxide (Ga) 2 O 3 ) Or other suitable ceramic material. In one embodiment, the core layer is surrounded by one or more layers of insulating material and/or other suitable material.
The nucleation layer 104 may be selectively disposed on the substrate 102 with fewer lattice defects, thereby improving the epitaxial quality of the superlattice layer 106 disposed on the nucleation layer 104. In one embodiment, the nucleation layer 104 may comprise a nitride (AlN) stack layer, which may comprise a first nitride layer and a second nitride layer, for example. According to an embodiment of the present disclosure, the first nitride layer may be, for example, a low temperature aluminum nitride layer (LT-AlN) that may be formed at an ambient temperature of 800-1100 ℃ via metal-organic chemical vapor deposition (MOCVD); the second nitride layer may be, for example, a high temperature aluminum nitride layer (HT-AlN) that may be formed at ambient temperatures of 1100-1400 c by metal organic chemical vapor deposition, but is not limited thereto.
A Superlattice Layer (SL) 106 may optionally be disposed on the substrate 102, such as on the nucleation layer 104. The superlattice layer 106 may be utilized to reduce a degree of lattice mismatch (lattice mismatch) between the substrate 102 and a semiconductor layer disposed on the superlattice layer 106, as well as stress caused by the lattice mismatch. The superlattice layer 106 may be a superlattice stack layer, such as including a first superlattice layer and a second superlattice layer, according to an embodiment of the present disclosure. According to different requirements, the first superlattice layer and the second superlattice layer may each be a periodic alternating layer structure composed of at least two III-V compound semiconductors, such as an AlN thin layer/GaN thin layer alternately stacked structure, or each may be a III-V compound semiconductor with gradually changed composition ratio, such as aluminum gallium nitride (Al) with gradually decreased aluminum composition ratio from bottom to top a Ga 1- a N,0.15 ≦ a ≦ 0.9), but is not limited thereto.
The high resistance layer 108 may optionally be disposed on the substrate 102, such as on the superlattice layer 106. The high resistance layer 108 has a higher resistivity than other layers, thereby preventing leakage current between the semiconductor layer disposed on the high resistance layer 108 and the substrate 102. According to an embodiment of the present disclosure, the high resistance layer 108 may be a group III-V semiconductor layer having a dopant, such as, but not limited to, a carbon-doped gallium nitride (c-GaN) layer.
The channel layer 110 may be disposed on the substrate 102, such as on the high resistance layer 108. The channel layer 110 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, alGaN, inGaN, or InAlGaN, but is not limited thereto. According to an embodiment of the present disclosure, the channel layer 110 is an undoped group III-V semiconductor, such as undoped GaN (u-GaN). According to other embodiments of the present disclosure, the channel layer 110 may also be one or more doped III-V semiconductor layers, such as p-type III-V semiconductor layers. For the p-type group III-V semiconductor layer, the dopant may be cadmium (Cd), iron (Fe), magnesium (Mg) or zinc (Zn), but is not limited thereto.
Barrier layer 112 may be disposed on channel layer 110. Barrier layer 112 may comprise one or more III-V semiconductor layers and may be of a different composition than the III-V semiconductor of channel layer 110. For example, the barrier layer 112 may comprise AlN, al z Ga (1-z) N (0 < z < 1), or a combination thereof. According to one embodiment, the barrier layer 112 may be an n-type group III-V semiconductor, such as, but not limited to, an essentially n-type AlGaN layer.
Since the channel layer 110 and the barrier layer 112 have discontinuous energy gaps therebetween, by stacking the channel layer 110 and the barrier layer 112 on top of each other, electrons are collected in the channel layer 110 due to the piezoelectric effect and are adjacent to the heterojunction between the channel layer 110 and the barrier layer 112. The collected electrons may constitute a thin layer with high carrier mobility, i.e., a two-dimensional electron gas (2-DEG) region 130.
According to an embodiment of the present disclosure, the compositionally-graded layer 114 may be formed on the barrier layer 112, and the compositionally-graded layer 114 may include aluminum gallium nitride (Al) x Ga (1-x) N, wherein 0.2<x<0.4 Or aluminum gallium indium nitride (Al) x Ga (1-x-y) InyN, wherein 0.2<x<0.6，0<y<0.4 X and y are values that vary with depth, where the value of x gradually increases from bottom to top in the depth direction and the value of y gradually decreases from bottom to top in the depth direction. According to one embodiment, the compositionally-graded Layer 114 may be formed using an Atomic Layer Deposition (ALD) process, by adjusting the source gas ratios for depositing each atomic Layer, such as the source gases of aluminum (Al), nitrogen (N), gallium (Ga), and/or indium (In), a plurality of atomic Layer stacks with graded composition ratios may be deposited to form, for example, a compositionally-graded Layer 114 with a graded atomic percentage or atomic concentration of aluminum (Al). According to aThe thickness of the composition graded layer 114 may be 2nm to 10nm, or may be 10% to 50% of the thickness of the barrier layer 112, by way of example.
According to an embodiment of the present disclosure, a doped compound semiconductor layer 116 may be formed on the composition graded layer 114 to deplete a two-dimensional electron gas (2-DEG) region to achieve a normally-off (normal-off) state of the HEMT. The doped compound semiconductor layer 116 may be one or more doped III-V semiconductor layers, which may have a composition of GaN, alGaN, inGaN, or InAlGaN, and a dopant of C, fe, mg, or Zn, but is not limited thereto. According to an embodiment, the doped compound semiconductor layer 116 may be a p-type GaN layer.
Next, according to an embodiment of the present disclosure, as shown in fig. 7, a patterned doped compound semiconductor layer 116 is formed on the composition gradient layer 114. According to an embodiment, the patterned doped compound semiconductor layer 116 may be formed by using photolithography and etching processes, during which the composition graded layer 114 may protect the barrier layer 112 located thereunder, so that the etching process for forming the patterned doped compound semiconductor layer 116 is more tolerant.
Next, as shown in fig. 8, an isolation region 118 is formed at the periphery of the HEMT to isolate adjacent HEMTs according to an embodiment of the present disclosure. According to one embodiment, the isolation region 118 extends through the graded composition layer 114 and the barrier layer 112 down into the channel layer 110 and is spaced apart from the high resistance layer 108. In one embodiment, the isolation region 118 may be a Shallow Trench Isolation (STI), which may be formed by forming a trench in the composition graded layer 114, the barrier layer 112 and the channel layer 110 through an etching process, filling the trench with one or more layers of dielectric materials, such as silicon oxide, silicon nitride or a combination thereof, and performing a Chemical Mechanical Polishing (CMP) process to form the isolation region 118. In another embodiment, the isolation region 118 may be formed by ion implantation, using a hard mask to cover the region outside the predetermined isolation region 118, and implanting a dopant, such as helium or carbon, into the graded composition layer 114, the barrier layer 112, and the channel layer 110 to form the isolation region 118. However, the present invention is not limited thereto, and those skilled in the art can adjust the depth of the isolation region 118 in other layers according to actual requirements.
Next, as shown in fig. 9, a first passivation layer 120-1 is formed on the isolation region 118 and the composition-graded layer 114, and a source electrode 122 and a drain electrode 124 are formed on both sides of the doped compound semiconductor layer 116, according to an embodiment of the present disclosure. In one embodiment, the first passivation layer 120-1 exposes the source electrode 122 and the drain electrode 124, and the source electrode 122 and the drain electrode 124 extend through the composition graded layer 114 and the barrier layer 112 down into the channel layer 110 such that the bottom of the source electrode 122 and the drain electrode 124 are higher than the bottom of the isolation region 118 and lower than the top surface of the channel layer 110. In another embodiment, the source electrode 122 and the drain electrode 124 extend through the first passivation layer 120-1 and the compositionally-graded layer 114 down into the barrier layer 112 such that the bottom of the source electrode 122 and the drain electrode 124 are above the bottom of the isolation region 118 and below the top surface of the barrier layer 112.
According to an embodiment, a first passivation layer 120-1 may be deposited to cover the isolation region 118, the compositional gradient layer 114, and the doped compound semiconductor layer 116, contact holes of the source electrode 122 and the drain electrode 124 respectively located at both sides of the doped compound semiconductor layer 116 may then be formed in the first passivation layer 120-1, the compositional gradient layer 114, the barrier layer 112, and the channel layer 110, and then a conductive material layer may be deposited in the contact holes and on the first passivation layer 120-1. In one embodiment, the source electrode 122 and the drain electrode 124 may be formed by a chemical mechanical polishing process and expose the top surface of the doped compound semiconductor layer 116, wherein the top surfaces of the source electrode 122 and the drain electrode 124 may be flush with the top surface of the doped compound semiconductor layer 116. In another embodiment, after depositing the conductive material layer, an etching process may be used to remove the conductive material layer except the contact holes to form the source and drain electrodes 122 and 124, and the top surface of the doped compound semiconductor layer 116 may still be covered by the first passivation layer 120-1.
According to an embodiment, the source electrode 122 and the drain electrode 124 may be a single layer or a multi-layer structure, and the composition thereof may include an ohmic contact metal. Wherein the ohmic contact metal refers to a metal, an alloy or a stacked layer thereof that can generate ohmic contact (ohmic contact) with a semiconductor layer (e.g., the channel layer 110), such as, but not limited to, ti/Al/Ti/TiN, ti/Al/Ti/Au, ti/Al/Ni/Au or Ti/Al/Mo/Au.
Next, as shown in fig. 10, a second passivation layer 120-2 is formed to cover the first passivation layer 120-1, the doped compound semiconductor layer 116, the source electrode 122 and the drain electrode 124, and the first passivation layer 120-1 and the second passivation layer 120-2 may be referred to as the passivation layer 120 in combination, according to an embodiment of the present disclosure. Then, a contact hole 125 of the gate electrode 126 is formed in the second passivation layer 120-2 to expose the top surface of the doped compound semiconductor layer 116. According to an embodiment of the present disclosure, in case that an etch stop layer (not shown) is disposed on the top surface of the doped compound semiconductor layer 116, the etch stop layer may be exposed from the contact hole 125. The etching stop layer can be used to protect the doped compound semiconductor layer 116, so as to prevent the doped compound semiconductor layer 116 from directly contacting with the etchant used for forming the contact hole 125. Thereafter, a conductive material layer is deposited in the contact hole 125 and on the second passivation layer 120-2, and patterned by photolithography and etching processes to form the gate electrode 126 as shown in FIG. 1. According to an embodiment, the top surface of the gate electrode 126 is higher than the top surface of the passivation layer 120. In another embodiment, a portion of the gate electrode 126 may also extend onto the top surface of the passivation layer 120.
According to an embodiment, the gate electrode 126 may have a single-layer or multi-layer structure, such as a double-layer structure including a first conductive layer and a second conductive layer. The first conductive layer may directly contact the doped compound semiconductor layer 116, and the composition of the first conductive layer includes a schottky contact metal. The Schottky contact metal refers to a metal, an alloy or a stacked layer thereof that can make Schottky contact with a semiconductor layer (e.g., the doped compound semiconductor layer 116), such as TiN, W, pt, ni or Ni, but is not limited thereto. The composition of the second conductive layer may include Ti, al, au, mo, but is not limited thereto. According to an embodiment, the first conductive layer may further include a metal nitride of a refractory metal, and the refractory metal may be selected from the group consisting of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, technetium, rhenium, ruthenium, osmium, rhodium, and iridium.
According to an embodiment of the present disclosure, the material of the first passivation layer 120-1 and the second passivation layer 120-2 includes aluminum oxide (Al) 2 O 3 ) Silicon nitride (Si) 3 N 4 ) Silicon oxynitride (SiON), aluminum nitride (AlN), or silicon oxide (SiO) 2 ) And the materials of the first and second passivation layers 120-1 and 120-2 may be the same. In another embodiment, the materials of the first passivation layer 120-1 and the second passivation layer 120-2 may be different.
According to an embodiment of the present disclosure, with respect to the HEMT 100-2 shown in fig. 5, a manufacturing method of the HEMT 100-2 of fig. 5 is different from the manufacturing method of the HEMT 100-1 of fig. 1 in that before the doped compound semiconductor layer 116 is formed, a cap layer 115 is formed on the composition graded layer 114, and then the doped compound semiconductor layer 116 is formed on the cap layer 115, wherein an isolation region 118 is formed in the cap layer 115, the composition graded layer 114, the barrier layer 112 and the channel layer 110. Thereafter, a passivation layer 120 is formed to cover the doped compound semiconductor layer 116 and the cap layer 115, and the source electrode 122 and the drain electrode 124, which are subsequently formed, pass through the cap layer 115. In this embodiment, the cap layer 115 may protect the underlying graded layer 114 during the etching process of the patterned doped compound semiconductor layer 116, thereby further increasing the tolerance of the etching process of the patterned doped compound semiconductor layer 116, and since the cap layer 115 is thin, it does not affect the 2-DEG performance of the HEMT.
According to the embodiments of the present disclosure, the graded composition layer disposed between the barrier layer and the passivation layer is intended to reduce or eliminate the surface polarization of the barrier layer, thereby preventing the surface leakage current between the gate electrode and the source electrode, and between the gate electrode and the drain electrode of the HEMT, allowing more precise switching control of the HEMT, while maintaining the 2-DEG performance of the HEMT, and further improving the electrical performance of the HEMT. In addition, the arrangement of the composition gradient layer and the cover layer can also improve the etching process tolerance of the patterned semiconductor cover layer formed on the composition gradient layer or the cover layer, and improve the manufacturing yield of HEMT.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the present invention.
[ description of symbols ]
100 method 8230and semiconductor structure
100-1 \8230andhigh electronic mobility transistor
100-2 (8230)' high electronic mobility transistor
102 \ 8230and substrate
104' \ 8230and nucleating layer
106 method 8230and superlattice layer
108 \ 8230and high resistance layer
110 \ 8230and channel layer
112, 8230and barrier layer
114 \ 8230and composition gradient layer
115 deg.8230a cap layer
116' \ 8230and doped compound semiconductor layer
118 method 8230and isolation region
120 \ 8230and passivation layer
120-1 \8230firstpassivation layer
120-2 (8230); the first passivation layer
122 method 8230and source electrode
124 \ 8230and drain electrode
125\8230contacthole
126 8230and a grid electrode
130 \ 8230two-dimensional electron gas region
C1 value 8230and numerical value
C2 value 8230and numerical value
201 \ 8230and straight line
202, 8230a arc
203 \ 8230and a stepped curve.

Claims (11)

1. A semiconductor structure, comprising:
a buffer layer disposed on a substrate;
a channel layer arranged on the buffer layer;
a barrier layer disposed on the channel layer;
a doped compound semiconductor layer disposed on the barrier layer; and
a composition gradient layer disposed between the barrier layer and the doped compound semiconductor layer, wherein the barrier layer and the composition gradient layer comprise a same group III element and a same group V element, and the atomic percentages of the same group III element in the composition gradient layer gradually increase from the barrier layer to the doped compound semiconductor layer.
2. The semiconductor structure of claim 1, wherein the overall atomic percent of the same group iii element in the compositionally graded layer is higher than the atomic percent of the same group iii element in the barrier layer.
3. The semiconductor structure of claim 1, wherein said compositionally graded layer comprises a metal dopant comprising magnesium, cadmium, carbon or zinc.
4. The semiconductor structure of claim 1, further comprising a cap layer disposed between said compositionally-graded layer and said doped compound semiconductor layer, wherein said cap layer comprises said same group-III element and said same group-V element.
5. The semiconductor structure of claim 4, wherein an average atomic concentration of said same group-Ill element of said cap layer is higher than an average atomic concentration of said same group-Ill element of said compositionally-graded layer.
6. The semiconductor structure of claim 4, wherein a thickness of said cap layer is 2% to 10% of a thickness of said compositionally-graded layer.
7. The semiconductor structure of claim 1, wherein the barrier layer comprises aluminum gallium nitride (Al) z Ga (1-z) N, wherein 0<z<1) The compositionally graded layer includes aluminum gallium nitride (Al) x Ga (1-x) N, wherein 0.2<x<0.4 Or aluminum gallium indium nitride (Al) x Ga (1-x-y) In y N, wherein 0.2<x<0.6，0<y<0.4 And the same group iii element is aluminum (Al).
8. The semiconductor structure of claim 1, wherein the thickness of the compositionally-graded layer is 10% to 50% of the thickness of the barrier layer.
9. A high electron mobility transistor comprising:
a semiconductor structure as in claim 1;
a gate electrode disposed on the doped compound semiconductor layer;
a source electrode and a drain electrode respectively arranged at two sides of the gate electrode; and
a passivation layer covering the gate electrode, the source electrode and the drain electrode.
10. The hemt of claim 9, wherein the passivation layer comprises aluminum oxide (Al) 2 O 3 ) Silicon nitride (Si) 3 N 4 ) Silicon oxynitride (SiON), aluminum nitride (AlN), or silicon oxide (SiO) 2 )。
11. The hemt of claim 9, wherein the passivation layer contacts a portion of the top surface of the compositionally graded layer.
CN202110693710.7A 2021-06-22 2021-06-22 Semiconductor structure and high electron mobility transistor Pending CN115513276A (en)

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