TWI755277B - High electron mobility transistor and fabrication method thereof - Google Patents

Abstract

A high electron mobility transistor includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor protection layer, a patterned semiconductor capping layer, an interlayer dielectric layer, and a gate electrode. The semiconductor channel layer and the semiconductor barrier layer are disposed on the substrate. The patterned semiconductor protection layer is disposed on the semiconductor barrier layer, and the patterned semiconductor capping layer is disposed between the patterned semiconductor protection layer and the semiconductor barrier layer. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and the interlayer dielectric layer includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where a portion of the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

Description

High electron mobility transistor and method of making the same

The present disclosure relates to the field of transistors, and in particular, to a high electron mobility transistor and a fabrication method thereof.

In semiconductor technology, group III-V semiconductor compounds can be used to form various integrated circuit devices, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMTs). A HEMT is a transistor with two dimensional electron gas (2DEG), and the 2DEG is adjacent to a junction (ie, a heterojunction) between two materials with different energy gaps. Since the HEMT does not use the doped region as the carrier channel of the transistor, but uses the 2DEG as the carrier channel of the transistor, compared with the conventional MOSFET, HEMT has various attractive properties. Characteristics such as high electron mobility and the ability to transmit signals at high frequencies. For a conventional HEMT, a compound semiconductor channel layer, a compound semiconductor barrier layer, a P-type compound semiconductor capping layer, a metal capping layer, and a gate electrode may be sequentially stacked. Using the gate electrode to bias the P-type compound semiconductor cap layer, the two-dimensional electron gas concentration in the compound semiconductor channel layer under the P-type compound semiconductor cap layer can be regulated, thereby regulating the switching of the HEMT.

For the metal cap layer disposed between the P-type compound semiconductor cap layer and the gate electrode, the step of forming the metal cap layer usually includes a wet side etching process. However, due to the lateral The etching degree of the etching process is difficult to precisely control, so that the metal cap layers of each HEMT have different widths, thereby reducing the uniformity of the electrical performance of each HEMT.

In view of this, it is necessary to propose an improved high electron mobility transistor to improve the shortcomings of the conventional high electron mobility transistor.

According to an embodiment of the present disclosure, a high electron mobility transistor is provided, including a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor protective layer, a patterned semiconductor cap layer, an interlayer dielectric layer, and a gate electrode. The semiconductor channel layer and the semiconductor barrier layer are disposed on the substrate. The patterned semiconductor protective layer is disposed on the semiconductor barrier layer, and the patterned semiconductor capping layer is disposed between the patterned semiconductor protective layer and the semiconductor barrier layer. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protective layer, and the interlayer dielectric layer includes a gate contact hole. The gate electrode is arranged in the gate contact hole and is electrically connected to the patterned semiconductor cap layer, wherein a patterned semiconductor protective layer exists between the gate electrode and the patterned semiconductor cap layer. The resistivity of the patterned semiconductor protective layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

According to another embodiment of the present disclosure, a method for fabricating a high electron mobility transistor is provided, including: providing a substrate on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, and a semiconductor channel layer are sequentially disposed. Semiconductor protective layer; etching the semiconductor capping layer and the semiconductor protective layer to form a patterned semiconductor capping layer and a patterned semiconductor protective layer; forming an interlayer dielectric layer to cover the patterned semiconductor capping layer and the patterned semiconductor protective layer; forming a gate electrode A contact hole is in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protective layer and is separated from the patterned semiconductor cap layer; and a gate electrode is formed in the gate contact hole, wherein the gate electrode and Part of the patterned semiconductor protective layer exists between the patterned semiconductor cap layers, wherein the resistivity of the patterned semiconductor cap layer is between the resistivity of the patterned semiconductor cap layer and the resistivity of the interlayer dielectric layer.

According to the embodiments of the present disclosure, since the resistivity of the patterned semiconductor protective layer is higher than that of the upper gate electrode, even if the side surfaces of the patterned semiconductor protective layer are not etched sideways, the side surfaces of the patterned semiconductor protective layer are not easily etched. A tip discharge is generated, whereby unnecessary gate leakage current can be avoided. Furthermore, when the gate contact hole is fabricated, the bottom surface of the gate contact hole will not penetrate the patterned semiconductor protective layer, so the etchant can be prevented from contacting the patterned semiconductor capping layer, and the original pattern of the patterned semiconductor capping layer can be maintained. electrical characteristics.

10-1: High Electron Mobility Transistors

10-2: High Electron Mobility Transistors

10-3: High Electron Mobility Transistors

20: Semiconductor Structure

102: Substrate

104: Buffer layer

106: Semiconductor channel layer

106a: two-dimensional electron gas region

106b: Two-dimensional electron gas cut-off region

108: Semiconductor barrier layer

109: Semiconductor capping layer

110: Patterned semiconductor capping layer

111: Semiconductor protective layer

110S: Side

110T: Top surface

120: Patterned semiconductor protective layer

120B: Bottom

120S: Side

122: Part 1

124: Part II

124T: top surface

126: Groove

126B: Bottom

126S: Side

128:Mask layer

130: Interlayer dielectric layer

132: Gate contact hole

134: Opening

140: gate electrode

140C: Bottom corner

142: the first conductive layer

144: the second conductive layer

150: interlayer dielectric layer

152: source/drain contact hole

152B: Bottom

154: source/drain electrodes

156: source/drain electrodes

160: Passivation layer

200: Method

202: Steps

204: Steps

206: Steps

208: Steps

210: Steps

A: area

D1: width

D2: width

D3: width

D4: width

T1: Thickness

T2: Thickness

In order to make the following easier to understand, reference is made to both the drawings and their detailed description while reading the present disclosure. The specific embodiments of the present disclosure will be explained in detail through the specific embodiments herein and the corresponding drawings will be referred to, and the working principles of the specific embodiments of the present disclosure will be described. Furthermore, for clarity, the features in the drawings may not be drawn to actual scale and thus the dimensions of some of the features in some of the drawings may be intentionally exaggerated or reduced in size.

FIG. 1 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure.

FIG. 2 is an enlarged cross-sectional schematic diagram of a partial region of a high electron mobility transistor according to an embodiment of the present disclosure.

FIG. 3 is an enlarged schematic cross-sectional view of a partial region of a high electron mobility transistor according to a variant embodiment of the present disclosure.

FIG. 4 is a schematic cross-sectional view of a high electron mobility transistor according to a variant embodiment of the present disclosure.

FIG. 5 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes sequentially stacked semiconductor layers.

FIG. 6 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes a patterned semiconductor cap layer, a patterned semiconductor protective layer, and a mask layer.

FIG. 7 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes a gate contact hole disposed in an interlayer dielectric layer.

FIG. 8 is a schematic cross-sectional view of a high electron mobility transistor including a gate electrode according to an embodiment of the present disclosure.

FIG. 9 is a schematic cross-sectional view of a high electron mobility transistor including source/drain contact holes disposed in an interlayer dielectric layer according to an embodiment of the present disclosure.

FIG. 10 is a flow chart of fabricating a high electron mobility transistor according to an embodiment of the present disclosure.

The present disclosure provides several different embodiments for implementing different features of the present disclosure. For simplicity of illustration, the present disclosure also describes examples of specific components and arrangements. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or over the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". There are other features between features", so that the first feature is not in direct contact with the second feature. Additionally, various embodiments in the present disclosure may use repeated reference symbols and/or textual notation. These repeated reference signs and notations are used for brevity and clarity of description, rather than to indicate associations between different embodiments and/or configurations.

In addition, for the space-related narrative words mentioned in this disclosure, for example: "below", "low", "below", "above", "above", "below", "top" ”, “bottom” and similar words, for ease of description, are used to describe the relative relationship of one element or feature to another (or more) elements or features in the drawings. In addition to the pendulum shown in the drawings, these space-related terms are also used to describe the possible pendulum orientations of the semiconductor device during use and operation. Depending on the swing direction of the semiconductor device (spin 90 degrees or other orientations), the space-related descriptions used to describe the direction of its swing should also be interpreted in a similar way.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that such elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not by themselves imply or represent that element The presence of any preceding ordinal numbers does not imply the order in which an element is arranged relative to another element, or the order of the method of manufacture. Thus, a first element, component, region, layer or block discussed below could be termed a second element, component, region, layer or block without departing from the scope of the specific embodiments of the present disclosure Of.

The terms "about" or "substantially" referred to in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meaning of "about" or "substantially" can still be implied without the specific description of "about" or "substantially".

In the present disclosure, "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the group III element can be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element can be nitrogen (N), phosphorus (P), arsenic (As) or antimony ( Sb). Further, "III-V semiconductors" may include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), Indium Aluminum Gallium Nitride (InAlGaN), Indium Gallium Nitride (InGaN), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Gallium Arsenide (AlGaAs), Aluminum Indium Arsenide (InAlAs), Arsenide Gallium Indium (InGaAs), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Gallium Arsenide (AlGaAs), Aluminum Indium Arsenide (InAlAs), Gallium Indium Arsenide (InGaAs), the like or the above A combination of compounds, but not limited thereto. In addition, depending on the requirements, the III-V group semiconductor may also include dopants, which are III-V group semiconductors with a specific conductivity type, such as N-type or P-type III-V semiconductors.

Although the invention of the present disclosure is described below with reference to specific embodiments, the inventive principles of the present disclosure can also be applied to other embodiments. Furthermore, in order not to obscure the spirit of the present invention, certain details will be omitted, which are within the knowledge of those having ordinary skill in the art.

The present disclosure relates to a high electron mobility transistor (HEMT), which can be used as a power switching transistor for voltage converter applications. Compared with silicon power transistors, III-V HEMTs have the characteristics of low on-state resistance and low switching losses due to their wider energy bandgap.

FIG. 1 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure. As shown in FIG. 1 , according to an embodiment of the present disclosure, a high electron mobility transistor 10 - 1 , such as an enhancement type high electron mobility transistor, is disposed on the substrate 102 , and the substrate 102 may be disposed on the substrate 102 in sequence. The semiconductor channel layer 106 , the semiconductor barrier layer 108 , the patterned semiconductor cap layer 110 , the patterned semiconductor protective layer 120 , and the interlayer dielectric layer 130 , and the interlayer dielectric layer 130 may be provided with a gate electrode 140 . The resistivity of the patterned semiconductor protective layer 120 is between the resistivity of the patterned semiconductor cap layer 110 and the resistivity of the interlayer dielectric layer 130 . According to an embodiment of the present disclosure, the interlayer dielectric layer 130 can cover the patterned semiconductor cap layer 110 and the patterned semiconductor protective layer 120 , and the interlayer dielectric layer 130 is provided with a gate contact hole 132 for accommodating the gate electrode 140 . Part of the patterned semiconductor protective layer 120 exists between the gate electrode 140 and the patterned semiconductor cap layer 110 .

According to an embodiment of the present disclosure, an optional buffer layer 104 may be disposed between the substrate 102 and the semiconductor channel layer 106 . An interlayer dielectric layer 150 may be selectively disposed above the interlayer dielectric layer 130 . At least two source/drain contact holes 152 can penetrate through the interlayer dielectric layers 130 and 150 to accommodate at least two source/drain electrodes 154 and 156 , respectively.

According to an embodiment of the present disclosure, the substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire (sapphire) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (germanium-on-insulator). germanium on insulator, GOI) substrate, but not limited to this. In another embodiment, the substrate 102 further includes a single or multiple layers of insulating material and/or other suitable material layers (eg, semiconductor layers) and a core layer. The insulating material layer may be oxide, nitride, oxynitride, or other suitable insulating material. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), zinc oxide (ZnO) or gallium oxide (Ga ₂ O ₃ ), or other suitable ceramic materials. In one embodiment, a single or multiple layers of insulating material and/or other suitable material layers coat the core layer.

The buffer layer 104 may be used to reduce the degree of stress or lattice mismatch that exists between the substrate 102 and the semiconductor channel layer 106 . According to an embodiment of the present disclosure, the buffer layer 104 may include a plurality of sub-semiconductors, and the overall resistance of the buffer layer 104 may be higher than that of other layers on the substrate 102 . Specifically, the proportion of some elements in the buffer layer 104 , such as metal elements, will gradually change from the substrate 102 to the direction of the semiconductor channel layer 106 . For example, where substrate 102 and semiconductor channel layer 106 are silicon substrates and i-GaN layers, respectively, buffer layer 104 may be graded aluminum gallium nitride ( _{AlxGa (1-x)} N), and The X value decreases from 0.9 to 0.15 in a continuous or stepwise manner along the direction of the substrate 102 toward the semiconductor channel layer 106 .

The above-mentioned semiconductor channel layer 106 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN or InAlGaN, but is not limited thereto. In addition, the semiconductor channel layer 106 may also be one or more doped III-V semiconductor layers, such as P-type III-V semiconductor layers. For the P-type III-V semiconductor layer, the dopant may be C, Fe, Mg or Zn, or not limited thereto. The semiconductor barrier layer 108 may include one or more III-V semiconductor layers, and its composition may be different from the III-V semiconductor of the semiconductor channel layer 106 . For example, the semiconductor barrier layer 108 may include AlN, _{AlyGa (1-y)} N (0<y<1), or a combination thereof. According to an embodiment, the semiconductor channel layer 106 may be an undoped GaN layer, and the semiconductor barrier layer 108 may be an N-type AlGaN layer in nature. Since there is a discontinuous energy gap between the semiconductor channel layer 106 and the semiconductor barrier layer 108, by stacking the semiconductor channel layer 106 and the semiconductor barrier layer 108 on each other, electrons will be collected in the piezoelectric effect (piezoelectric effect) The heterojunction between the semiconductor channel layer 106 and the semiconductor barrier layer 108 thus produces a thin layer of high electron mobility, ie, a two-dimensional electron gas (2DEG) region 106a. In contrast, the area covered by the patterned semiconductor capping layer 110 can be regarded as the two-dimensional electron gas blocking area 106b because the two-dimensional electron gas will not be formed.

The patterned semiconductor capping layer 110 disposed above the semiconductor barrier layer 108 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN or InAlGaN, but not limited to this. The patterned semiconductor capping layer 110 may be one or more doped III-V semiconductor layers, such as P-type III-V semiconductor layers. For the P-type III-V semiconductor layer, the dopant may be C, Fe, Mg or Zn, but is not limited thereto. According to an embodiment of the present disclosure, the patterned semiconductor capping layer 110 may be a P-type GaN layer.

The patterned semiconductor protective layer 120 can substantially completely cover the underlying patterned semiconductor capping layer 110, so that its sides can be flush with the underlying patterned semiconductor capping layer 110, or slightly shrink or protrude (each side The length of the indentation or protrusion can be 1-10nm, but not limited thereto). The composition of the patterned semiconductor protective layer 120 is a semiconductor different from that of the patterned semiconductor capping layer 110 . According to an embodiment of the present disclosure, the composition of the patterned semiconductor protective layer 120 may include a silicon-containing semiconductor or a silicon-containing material, such as silicon, silicon carbide, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon carbonitride , silicon oxycarbide, silicon oxycarbonitride, metal silicide, or a combination thereof, and the crystalline state of the patterned semiconductor protective layer 120 may be single crystalline, polycrystalline or amorphous. For example, the patterned semiconductor protective layer 120 may be low temperature polysilicon. The resistivity of the patterned semiconductor protective layer 120 may be higher than that of the underlying patterned semiconductor capping layer 110, for example, 10 to 1000 Ω·m, and its longitudinal resistance may be 1×10 ⁴ to 1×10 ⁶ Ω, for example, 1×10 ⁴ Ω, 1×10 ⁵ Ω or 1x10 ⁶ Ω, but not limited to this.

The gate electrode 140 can be electrically connected with the underlying patterned semiconductor capping layer 110 through Schottky contact, and the bottom of the gate electrode 140 can be buried in the patterned semiconductor protective layer 120, but still It is longitudinally separated from the underlying patterned semiconductor capping layer 110 . Therefore, the patterned semiconductor protective layer 120 may include the first portion 122 at the periphery and the second portion 124 at the middle. According to an embodiment of the present disclosure, the gate electrode 140 may be a single-layer or multi-layer structure, for example, a double-layer structure including a first conductive layer 142 and a second conductive layer 144 . The first conductive layer 142 can directly contact the patterned semiconductor protective layer 120, and its composition includes Schottky contact metal. The Schottky contact metal refers to a metal, an alloy or a stacked layer thereof that can make Schottky contact with the semiconductor layer, such as TiN, W, Pt, Ni or Ni, but not limited thereto. The composition of the second conductive layer 144 may include Ti, Al, Au, Mo, but is not limited thereto. According to an embodiment of the present disclosure, the first conductive layer 142 may include a metal nitride containing a refractory metal, and the refractory metal may be selected from titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and manganese , onium, rhenium, ruthenium, osmium, rhodium and iridium.

The interlayer dielectric layers 130 and 150 can be disposed on the semiconductor barrier layer 108 in sequence, and their materials can be independently selected from Si ₃ N ₄ , AlN, Al ₂ O ₃ , SiO ₂ , or a combination of the foregoing, but not limited to here. The interlayer dielectric layers 130 and 150 may cover the patterned semiconductor protective layer 120 , the patterned semiconductor capping layer 110 , the semiconductor barrier layer 108 and the semiconductor channel layer 106 . The resistivity of the interlayer dielectric layers 130 and 150 may be higher than that of the patterned semiconductor protection layer 120 . For example, the resistivity of the interlayer dielectric layers 130 and 150 may be 1× ^{10 10} to 1×10 ¹⁶ Ω·m, such as 1×10 ¹³ Ω·m, but not limited thereto.

The source/drain electrodes 154 , 156 may each penetrate the interlayer dielectric layers 130 , 150 and be electrically connected to the underlying semiconductor barrier layer 108 and the semiconductor channel layer 106 . According to an embodiment of the present disclosure, the source/drain electrodes 154 and 156 may be a single-layer or multi-layer structure, and the composition may include ohmic contact metal. Wherein, the ohmic contact metal refers to a metal, alloy or its stacked layer that can make ohmic contact with the semiconductor layer, such as Ti, Ti/Al, Ti/Al/Ti/TiN, Ti/Al/Ti/Au , Ti/Al/Ni/Au or Ti/Al/Mo/Au, but not limited thereto.

FIG. 2 is an enlarged cross-sectional schematic diagram of a partial region of the high electron mobility transistor according to an embodiment of the present disclosure, which may correspond to the region A shown in the embodiment of FIG. 1 . As shown in Figure 2, the patterned semiconductor The bottom surface 120B of the bulk protection layer 120 may coincide with the top surface 110T of the patterned semiconductor capping layer 110 . And the side surface 120S of the patterned semiconductor capping layer 120 can be substantially aligned with the side surface 110S of the patterned semiconductor capping layer 110 , so that the lateral dimension of the patterned semiconductor capping layer 120 and the patterned semiconductor capping layer 110 , such as the width D2 , can be substantially equal to each other. According to an embodiment of the present disclosure, grooves 126 may be provided on the surface of the patterned semiconductor protective layer 120 , so that the bottom surface 126B and the side surface 126S of the grooves 126 may overlap with the surface of the patterned semiconductor protective layer 120 . The lateral dimension of the groove 126 , such as the width D1 , may be smaller than the width D2 of the patterned semiconductor capping layer 110 such that the first portion 122 of the patterned semiconductor capping layer 120 may be adjacent to the perimeter of the groove 126 while the patterned semiconductor capping layer 120 is The second portion 124 of the can be disposed just below the groove 126 . The lateral dimension, such as the width, of each of the first portions 122 located at the periphery of the groove 126 may be widths D3 and D4, respectively. For example, the widths D3 and D4 may be 20 to 350 nm, and the widths D3 and D4 may be the same or different from each other, but not limited thereto. Also, the thickness T1 of the first portion 122 may be greater than the thickness T2 of the second portion 124 . For example, the thickness T2 may be 10 to 100 nm, but is not limited thereto. The lower portion of the gate electrode 140 can fill the groove 126 to have a width D1 , and at least one bottom corner 140C of the gate electrode 140 can directly contact the patterned semiconductor protection layer 120 or be further covered by the patterned semiconductor protection layer 120 .

According to the embodiment of the present disclosure, since the resistivity of the patterned semiconductor protective layer 120 is higher than that of the upper gate electrode 140 , even if the side surface 120S of the patterned semiconductor protective layer 120 is not laterally etched, the patterned semiconductor protective layer 120 also does not generate tip discharge, so unnecessary gate leakage current can be avoided. Furthermore, since the width D2 of the patterned semiconductor protective layer 120 can be substantially the same as the width D2 of the patterned capping layer, even semiconductor elements produced in different batches can still maintain good electrical power between the semiconductor elements. Sexual consistency. In addition, since the bottom corner 140C of the gate electrode 140 may be covered by the patterned semiconductor protective layer 120 having a relatively high resistivity, the patterned semiconductor protective layer 120 may be used to buffer the bottom corner 140C originating from the gate electrode 140 The high-voltage electric field can improve the stability of semiconductor components.

FIG. 3 is an enlarged cross-sectional schematic diagram of a partial region of a high electron mobility transistor according to a variant embodiment of the present disclosure. The high electron mobility transistor 10-2 shown in the embodiment of FIG. 3 is substantially the same as the high electron mobility transistor 10-1 shown in the embodiment of FIG. 2, with the main difference between the two being, The bottom surface of the gate electrode 140 of the high electron mobility transistor 10 - 2 is not buried in the patterned semiconductor protective layer 120 . Therefore, for the thickness T1 of the patterned semiconductor layer 120 , the thickness T1 of the patterned semiconductor layer 120 can be kept constant whether it is located at the periphery of the gate electrode 140 or directly under the gate electrode 140 . In addition, since the distance between the gate electrode 140 and the patterned semiconductor capping layer 110 is equal to the thickness T1 of the patterned semiconductor layer 120, in order to avoid excessive resistance between the gate electrode 140 and the patterned semiconductor capping layer 110, the patterned The thickness T1 of the semiconductor layer 120 may be 10 to 100 nm.

FIG. 4 is a schematic cross-sectional view of a high electron mobility transistor according to a variant embodiment of the present disclosure. The high electron mobility transistor 10-3 shown in the embodiment of FIG. 4 is substantially the same as the high electron mobility transistor 10-1 shown in the embodiment of FIG. 1, with the main difference between the two being, A forward passivation layer 160 is additionally disposed between the interlayer dielectric layer 130 of the high electron mobility transistor 10 - 3 and the semiconductor barrier layer 108 , the patterned semiconductor capping layer 110 , and the patterned semiconductor protective layer 120 . The passivation layer 160 can be used to eliminate or reduce surface defects existing on the top surface of the semiconductor barrier layer 108 , the side surface 110S of the patterned semiconductor capping layer 110 , and the side surface 120S of the patterned semiconductor protective layer 120 , thereby improving high electron mobility. Electrical performance of crystal 10-3. According to an embodiment of the present disclosure, the resistivity of the passivation layer 160 is higher than that of the patterned semiconductor protective layer 120 , and the passivation layer 160 may be composed of silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON) , aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ) or silicon oxide (SiO ₂ ), but not limited thereto.

In order to enable those with ordinary knowledge in the technical field to realize the invention of the present disclosure, the fabrication method of the high electron mobility transistor of the present disclosure is further described in detail below.

FIG. 5 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes sequentially stacked semiconductor layers. FIG. 10 is a flow chart of fabricating a high electron mobility transistor according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the fabrication method 200 may be implemented In step 202, a substrate is provided, and a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, and a semiconductor protective layer are sequentially disposed on the substrate. As shown in FIG. 5 , a buffer layer 104 , a semiconductor channel layer 106 , a semiconductor barrier layer 108 , a semiconductor cap layer 109 , and a semiconductor protective layer 111 may be sequentially disposed on the substrate 102 in the semiconductor structure 20 . The stacked layers on the substrate 102 can be formed by any suitable method, such as through molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydrogenation hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD) or other suitable methods.

FIG. 6 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes a patterned semiconductor cap layer, a patterned semiconductor protective layer, and a mask layer. According to an embodiment of the present disclosure, after the steps shown in the embodiment of FIG. 5 , photolithography and etching processes may be performed to form a mask layer 128 having a characteristic pattern. Following step 204, the semiconductor cap layer and the semiconductor protective layer are etched to form a patterned semiconductor cap layer and a patterned semiconductor protective layer. For example, the mask layer 128 can be used as an etching mask to perform an etching process to sequentially remove the semiconductor protective layer 111 and the semiconductor capping layer 109 exposed on the mask layer 128, thereby forming a patterned semiconductor protective layer 120 and the patterned semiconductor capping layer 110 . According to an embodiment of the present disclosure, since the feature pattern defined by the mask layer 128 is transferred to the underlying semiconductor protective layer 111 and the semiconductor cap layer 109 by longitudinal anisotropic etching, the mask layer 128, pattern The patterned semiconductor capping layer 120 and the patterned semiconductor capping layer 110 may have substantially the same lateral dimension, eg, width D2. Therefore, the side surface 128S of the mask layer 128 , the side surface 110S of the patterned semiconductor cap layer 110 , and the side surface 120S of the patterned semiconductor protective layer 120 can be substantially aligned with each other. In addition, for the area not covered by the patterned semiconductor cap layer 110 , the two-dimensional electron gas can be formed in the two-dimensional electron gas region due to the piezoelectric effect generated between the semiconductor channel layer 106 and the semiconductor barrier layer 108 106a. In contrast, the area covered by the patterned semiconductor capping layer 110 can be regarded as the two-dimensional electron gas blocking area 106b because the two-dimensional electron gas will not be formed.

After the patterned semiconductor protective layer 120 and the patterned semiconductor capping layer 110 are fabricated, the mask layer 128 may be removed to expose the top surface of the patterned semiconductor protective layer 120 .

FIG. 7 is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present disclosure, which includes a gate contact hole disposed in an interlayer dielectric layer. According to an embodiment of the present disclosure, step 206 is performed to form an interlayer dielectric layer to cover the patterned semiconductor capping layer and the patterned semiconductor protective layer. For example, the interlayer dielectric layer 130 can be formed through a suitable deposition process to completely cover the patterned semiconductor protective layer 120 , the patterned semiconductor cap layer 110 , the semiconductor barrier layer 108 , and the semiconductor channel layer 106 . Before removing the mask layer 128 and after forming the interlayer dielectric layer 130 , the width D2 of the patterned semiconductor protection layer 120 can be kept constant, so that the side surface 110S of the patterned semiconductor cap layer 110 and the side surface of the patterned semiconductor protection layer 120 can be maintained. The 120S can essentially be cut flush with each other. The material of the interlayer dielectric layer 130 may be Si ₃ N ₄ , AlN, Al ₂ O ₃ or SiO ₂ , but is not limited thereto.

Next, step 208 is performed to form a gate contact hole in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protective layer and is separated from the patterned semiconductor capping layer. For example, by performing photolithography and etching processes, the openings 134 can be formed in the interlayer dielectric layer 130 in sequence, and the grooves 126 can be formed on the surface of the patterned semiconductor protective layer 120 . The opening 134 and the groove 126 may constitute the gate contact hole 132 . Therefore, the patterned semiconductor protective layer 120 may be exposed from the gate contact hole 132 . The width D1 of the gate contact hole 132 may be smaller than the width D2 of the patterned semiconductor protective layer 120 . The bottom surface 126B of the gate contact hole 132 may be located in the patterned semiconductor protective layer 120 and separated from the patterned semiconductor capping layer 110 . Therefore, the top surface 122T of the first portion 122 of the patterned semiconductor protective layer 120 may be higher than the top surface 124T of the second portion 124 . According to an embodiment of the present disclosure, the etching process for forming the gate contact hole 132 may include a dry etching process, such as a plasma etching process. Since the bottom surfaces of the gate contact holes 132 will not penetrate the patterned semiconductor protective layer 120 during the etching process, it is possible to prevent a high-energy etchant (eg, plasma etchant) from contacting the patterned semiconductor cap layer 110 , and further The original electrical properties of the patterned semiconductor capping layer 110 may be maintained.

FIG. 8 is a schematic cross-sectional view of a high electron mobility transistor including a gate electrode according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, after the step shown in the embodiment of FIG. 7, step 210 may be performed to form a gate electrode in the gate contact hole, wherein a portion exists between the gate electrode and the patterned semiconductor cap layer patterned semiconductor protective layer. For example, a suitable deposition process may be performed to form a single or multiple conductive layer (not shown) on the top surface of the interlayer dielectric layer 130 and in the gate contact hole 132 . After that, photolithography and etching processes are performed to pattern the conductive layer to form the gate electrode 140 . According to an embodiment of the present disclosure, for the gate contact hole 132 with a smaller opening area, the gate electrode 140 may completely fill the gate contact hole 132 , but it is not limited thereto. According to an embodiment of the present disclosure, the gate electrode 140 may also be disposed only along the inner wall of the gate contact hole 132 without filling the gate contact hole 132 . Next, an additional interlayer dielectric layer or passivation layer, such as the interlayer dielectric layer 150 , is formed on the interlayer dielectric layer 130 to cover the gate electrode 140 .

FIG. 9 is a schematic cross-sectional view of a high electron mobility transistor including source/drain contact holes disposed in an interlayer dielectric layer according to an embodiment of the present disclosure. As shown in FIG. 9, at least one source/drain contact hole, such as two separate source/drain contact holes 152, can be formed on both sides of the gate electrode 140 by performing photolithography and etching processes. . When the etching process is completed, the bottom surface 152B of each source/drain contact hole 152 may be located in the semiconductor barrier layer 108 or further extend into the semiconductor channel layer 106 to expose the semiconductor channel layer 106 . In addition, since the bottom surface 152B of the source/drain contact hole 152 may be located in the semiconductor channel layer 108 or the semiconductor channel layer 106 , a two-dimensional electron gas blocking region 106b is correspondingly formed under each source/drain contact hole 152 .

Next, a suitable deposition process may be performed to form a single-layer or multi-layer conductive layer (not shown) on the top surface of the interlayer dielectric layer 150 and in the source/drain contact holes 152 . After that, photolithography and etching processes are performed to pattern the conductive layer to form source/drain electrodes 154 and 156 similar to those shown in FIG. 1 .

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10-1: High Electron Mobility Transistors

110: Patterned semiconductor capping layer

110S: Side

110T: Top surface

120: Patterned semiconductor protective layer

120B: Bottom

120S: Side

122: Part 1

124: Part II

124T: top surface

126: Groove

126B: Bottom

126S: Side

130: Interlayer dielectric layer

132: Gate contact hole

140: gate electrode

140C: Bottom corner

142: the first conductive layer

144: the second conductive layer

A: area

D1: width

D2: width

D3: width

D4: width

T1: Thickness

T2: Thickness

Claims (20)

A high electron mobility transistor, comprising: a semiconductor channel layer and a semiconductor barrier layer, disposed on a substrate; a patterned semiconductor protective layer, disposed on the semiconductor barrier layer; a patterned semiconductor cap layer, disposed between the patterned semiconductor protective layer and the semiconductor barrier layer; an interlayer dielectric layer covering the patterned semiconductor cap layer and the patterned semiconductor protective layer, wherein the interlayer dielectric layer includes a gate contact hole and a gate electrode disposed in the gate contact hole and electrically connected to the patterned semiconductor cap layer, wherein a portion of the patterned semiconductor protective layer exists between the gate electrode and the patterned semiconductor cap layer, wherein , the resistivity of the patterned semiconductor protective layer is between the resistivity of the patterned semiconductor cap layer and the resistivity of the interlayer dielectric layer. The high electron mobility transistor of claim 1, wherein the side surface of the patterned semiconductor protective layer is flush with the side surface of the patterned semiconductor cap layer. The high electron mobility transistor of claim 1, wherein the width of the gate contact hole is smaller than the width of the patterned semiconductor protective layer. The high electron mobility transistor of claim 1, wherein the gate electrode and the semiconductor cap layer are electrically connected by Schottky contacts. The high electron mobility transistor of claim 1, wherein the patterned semiconductor protects The resistivity of the layer is higher than that of the gate electrode. The high electron mobility transistor of claim 1, wherein the gate electrode directly contacts the patterned semiconductor protective layer. The high electron mobility transistor of claim 6, wherein the gate electrode comprises a bottom corner, and the bottom corner directly contacts the patterned semiconductor protective layer. The high electron mobility transistor of claim 1, wherein: the composition of the patterned semiconductor capping layer is a P-type III-V semiconductor; the composition of the patterned semiconductor protective layer is a silicon-containing semiconductor; and The composition of the gate electrode includes metal. The high electron mobility transistor of claim 1, wherein the surface of the patterned semiconductor protective layer includes a groove, and the gate electrode fills the groove. The high electron mobility transistor of claim 9, wherein the patterned semiconductor protective layer comprises at least a first part and a second part, the at least one first part is disposed around the groove, and the second part is disposed below the groove, and the thickness of the at least one first part is greater than the thickness of the second part. The high electron mobility transistor according to claim 1, further comprising a passivation layer disposed on the top surface of the semiconductor barrier layer, the side surface of the patterned semiconductor cap layer, and the patterned semiconductor protection layer The sides and top of the layer. A method for manufacturing a high electron mobility transistor, comprising: providing a substrate on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, and a semiconductor protective layer are sequentially disposed; etching the semiconductor cap layer and the The semiconductor protective layer is used to form a patterned semiconductor cap layer and a patterned semiconductor protective layer; an interlayer dielectric layer is formed to cover the patterned semiconductor cap layer and the patterned semiconductor protective layer; a gate contact hole is formed in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protective layer and is separated from the patterned semiconductor cap layer; and a gate electrode is formed in the gate contact hole, wherein Part of the patterned semiconductor protective layer exists between the gate electrode and the patterned semiconductor cap layer, wherein the resistivity of the patterned semiconductor cap layer is between the resistivity of the patterned semiconductor cap layer and the interlayer dielectric between the resistivities of the layers. The method for fabricating a high electron mobility transistor as claimed in claim 12, wherein before etching the semiconductor cap layer and the semiconductor protective layer, further comprising forming a mask layer on the semiconductor protective layer, and etching the semiconductor cap layer and the semiconductor protective layer. When the semiconductor capping layer and the semiconductor protective layer are used, the semiconductor capping layer and the semiconductor protective layer exposed on the mask layer are removed. The method for fabricating a high electron mobility transistor as claimed in claim 13, before forming the interlayer dielectric layer, further comprising removing the mask layer, wherein before removing the mask layer and forming the interlayer dielectric layer After layering, the width of the patterned semiconductor protective layer remains fixed. The method of fabricating a high electron mobility transistor as claimed in claim 14, wherein the removing Before the mask layer and after forming the interlayer dielectric layer, the side surfaces of the patterned semiconductor protective layer are flush with the side surfaces of the patterned semiconductor cap layer. The method for fabricating a high electron mobility transistor as claimed in claim 12, wherein the step of forming the gate contact hole in the interlayer dielectric layer includes performing photolithography and etching processes. The method for fabricating a high electron mobility transistor according to claim 12, wherein the resistivity of the patterned semiconductor protective layer is lower than the resistivity of the gate electrode. The method for fabricating a high electron mobility transistor according to claim 12, wherein the gate electrode directly contacts the patterned semiconductor protective layer. The method for manufacturing a high electron mobility transistor according to claim 12, wherein after the gate electrode is formed, the surface of the patterned semiconductor protective layer includes a groove, and the gate electrode fills the groove . The method for fabricating a high electron mobility transistor according to claim 19, wherein after the gate electrode is formed, the patterned semiconductor protective layer includes at least a first part and a second part, and the at least one first part is disposed on the At the periphery of the groove, the second portion is disposed below the groove, and the thickness of the at least one first portion is greater than the thickness of the second portion.

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