CN114335172B - Semiconductor structure - Google Patents
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- CN114335172B CN114335172B CN202011051566.9A CN202011051566A CN114335172B CN 114335172 B CN114335172 B CN 114335172B CN 202011051566 A CN202011051566 A CN 202011051566A CN 114335172 B CN114335172 B CN 114335172B
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Abstract
一种半导体结构，包括基板、半导体磊晶层、半导体阻障层、第一半导体元件、绝缘掺杂区、及至少一绝缘柱。基板包括基材和复合材料层，半导体磊晶层设置于基板上，半导体阻障层设置于半导体磊晶层上。第一半导体元件设置于基板上，其中第一半导体元件包括位于半导体阻障层上的第一半导体盖层。绝缘掺杂区位于第一半导体元件的一侧。至少部分的绝缘柱位于绝缘掺杂区内，绝缘柱围绕至少部分第一半导体元件且贯穿复合材料层。
A semiconductor structure includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor element, an insulating doped region, and at least one insulating column. The substrate includes a base material and a composite material layer, the semiconductor epitaxial layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor epitaxial layer. The first semiconductor element is disposed on the substrate, wherein the first semiconductor element includes a first semiconductor cap layer disposed on the semiconductor barrier layer. The insulating doped region is located on one side of the first semiconductor element. At least part of the insulating column is located in the insulating doped region, and the insulating column surrounds at least part of the first semiconductor element and penetrates the composite material layer.
Description
Technical Field
The present invention relates to a high voltage semiconductor structure, and more particularly, to a high voltage semiconductor structure having an insulating structure.
Background
With the development of 5G communication and electric vehicle industry, there is an increasing demand for high frequency, high power semiconductor devices, such as high frequency transistors, high power field effect transistors, or high electron mobility transistors (high electron mobility transistor, HEMTs). Semiconductor compounds such as gallium nitride and silicon carbide, which have characteristics such as high frequency, high voltage resistance, and low on-resistance, are generally used for high frequency and high power semiconductor devices.
Among these devices, high electron mobility transistors have advantages such as high output power and high breakdown voltage, and thus they are widely used in high power applications. While existing semiconductor structures and methods of forming the same can cope with their originally intended use, they still present problems that need to be overcome in terms of various techniques, both in terms of structure and in terms of environment of use.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor structure to solve the technical problems faced by the prior art.
According to an embodiment of the present invention, a semiconductor structure is provided, which includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor device, an insulating doped region, and at least one insulating pillar. The substrate comprises a base material and a composite material layer, the semiconductor epitaxial layer is arranged on the substrate, and the semiconductor barrier layer is arranged on the semiconductor epitaxial layer. The first semiconductor element is arranged on the substrate, wherein the first semiconductor element comprises a first semiconductor cover layer arranged on the semiconductor barrier layer. The insulating doped region is located at one side of the first semiconductor element. At least a portion of the insulating pillars are located within the insulating doped region, the insulating pillars surrounding at least a portion of the first semiconductor element and extending through the composite layer.
According to one embodiment of the present invention, a semiconductor structure is provided, the semiconductor structure includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, an insulating doped region, and at least one insulating pillar. The substrate includes a base material and a composite material layer. The semiconductor channel layer is arranged on the substrate, the semiconductor barrier layer is arranged on the semiconductor channel layer, and the semiconductor cover layer is arranged on the semiconductor barrier layer. The insulating doped region is located in the semiconductor channel layer and the semiconductor barrier layer and is located on at least one side of the semiconductor cap layer. The insulating column directly contacts the insulating doped region, and penetrates through the semiconductor barrier layer, the semiconductor channel layer and the composite material layer.
According to another embodiment of the present invention, a chip structure is provided, the chip structure including a substrate, a high voltage semiconductor structure, a low voltage semiconductor structure, and at least one insulating pillar. The substrate includes a base material and a composite material layer. The high-voltage semiconductor structure is arranged on the substrate, and the low-voltage semiconductor structure is arranged on the substrate and separated from the high-voltage semiconductor structure. The insulating column completely surrounds the high voltage semiconductor structure and penetrates the composite material layer.
According to another embodiment of the present invention, a method of operating a high voltage semiconductor structure is provided, the method of operating comprising providing a high voltage semiconductor structure, and applying an electrical signal to the high voltage semiconductor structure at an ambient temperature above 150 ℃. The high-voltage semiconductor structure comprises a substrate, a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cover layer, an insulating doped region and at least two insulating columns. The substrate includes a base material and a composite material layer. The semiconductor channel layer is arranged on the substrate, the semiconductor barrier layer is arranged on the semiconductor channel layer, and the semiconductor cover layer is arranged on the semiconductor barrier layer. The insulating doped region is located in the semiconductor channel layer and the semiconductor barrier layer and is located on at least one side of the semiconductor cap layer. The insulating column directly contacts the insulating doped region, and penetrates through the semiconductor barrier layer, the semiconductor channel layer and the composite material layer.
Drawings
For easier understanding, reference is made to the drawings and their detailed description when reading the present invention. Specific embodiments of the present invention will be described in detail herein with reference to the accompanying drawings and the description is made to the embodiments herein for illustrating the principles of the invention. Moreover, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and thus the dimensions of some features in some of the drawings may be exaggerated or reduced on purpose.
Fig. 1 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a high voltage semiconductor structure along line A-A' of fig. 1 according to an embodiment of the present invention.
Fig. 3 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a high voltage semiconductor structure along line A-A' of fig. 3 according to an embodiment of the present invention.
Fig. 5 and 6 are electrical characteristics of the high voltage semiconductor structure according to the embodiment of the invention at normal temperature.
Fig. 7 and 8 are electrical characteristics of a high voltage semiconductor structure at high temperature in accordance with an embodiment of the present invention.
Fig. 9 is a schematic top view of a chip structure according to an embodiment of the invention.
Fig. 10 is a schematic top view of a chip structure according to an embodiment of the invention.
FIG. 11 is a schematic cross-sectional view of the high voltage semiconductor structure along line B-B' of FIG. 10 according to one embodiment of the present invention.
The reference numerals are explained as follows:
1 chip structure
10 High voltage semiconductor structure
10-1 First high voltage semiconductor element
10-2 Second high voltage semiconductor device
20 High voltage semiconductor device
22 Insulating region
30 Logical operation element
40 Memory element
100 Substrate
100C substrate
100M composite layer
101 Silicon-containing semiconductor layer
102 Semiconductor epitaxial layer
103 Semiconductor buffer layer
104 Semiconductor barrier layer
105 Semiconductor channel layer
110 Insulating doped region
112 Interlayer dielectric layer
120 Insulating column
120_1 First insulating column
120_2 Second insulating column
120_3 Third insulating column
200 Active region
202 Source electrode
204 Gate electrode
206 Drain electrode
210 Semiconductor cap layer
300 Active region
302 Source electrode
304 Gate electrode
306 Drain electrode
310 Semiconductor cap layer
A: chip area
Cutting area B
L 1 width
L 2 width
L 3 width
S 1 spacing
S 2 spacing
S 3 spacing
S 4 spacing
Detailed Description
The invention provides a number of different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way.
The description of "a first element being formed on or over a second element" in the present invention may refer to "the first element being in direct contact with the second element" or may refer to "other elements being present between the first element and the second element" such that the first element and the second element are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference characters and/or text labels. The repeated reference characters and text labels are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.
Additionally, spatially relative terms, such as "under", "above", "low", "high", "below", "above", "below", "over", "above", "bottom", "top" and the like, may be used herein for ease of description to describe one element or feature's relative relationship to another element(s) or feature(s) in the figures. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor structure during fabrication, use, and operation. For example, when the semiconductor structure is rotated 180 degrees, a certain component that was originally disposed "above" other components becomes disposed "below" the other components. Thus, as the orientation of the semiconductor structure changes (rotated 90 degrees or other angles), the spatially relative descriptions describing the orientation should be interpreted in a corresponding manner.
Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, it should be understood that these elements, components, regions, layers and/or sections should not be limited by these terms. Such terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, which does not itself imply any preceding ordinal number or order of arrangement of the element and the other element or method of manufacture. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present invention.
The terms "coupled," "coupled," and "electrically connected" as used herein are intended to encompass any direct or indirect means of electrical connection. For example, if a first element is coupled to a second element, that connection could be directly to the second element or indirectly to the second element through other means of attachment or connection.
In the present invention, "group III-V semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. Among them, the group III element may be boron (B), aluminum (Al), gallium (Ga), or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, "III-V semiconductor" may include gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), the like, or combinations thereof, but is not limited thereto. In addition, dopants may be included in the III-V semiconductor, as desired, as well as III-V semiconductors having a particular conductivity type, such as N-type or P-type III-V semiconductors.
The specific steps or block levels in the steps/flows described below are exemplary. The particular steps or block hierarchy of steps/flows described below may be rearranged according to design preferences. Further, some blocks may be integrated or deleted.
While the invention is described below with specific embodiments, the principles of the invention are applicable to other embodiments as well. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted are within the knowledge of persons of ordinary skill in the art.
Fig. 1 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the invention. As shown in fig. 1, at least one high voltage semiconductor structure 10 may be disposed on a substrate 100, and the high voltage semiconductor structure 10 may include at least one semiconductor device, such as a first high voltage semiconductor device 10-1 and a second high voltage semiconductor device 10-2. According to an embodiment of the present invention, the first high voltage semiconductor element 10-1 and the second high voltage semiconductor element 10-2 may be semiconductor elements operating at a source voltage or a drain voltage of more than 600V, such as high electron mobility transistors, but are not limited thereto. According to an embodiment of the present invention, the first high voltage semiconductor device 10-1 may include an active region 200, a source electrode 202, a gate electrode 204, and a drain electrode 206. The source electrode 202, the gate electrode 204, and the drain electrode 206 may be electrically connected to corresponding regions of the active region 200, respectively. The electronic signal can be input to and output from the active region 200 via the source electrode 202 and the drain electrode 206, and the current conduction degree of the first high-voltage semiconductor device 10-1 can be controlled by applying an appropriate voltage to the gate electrode 204. Similarly, the second high voltage semiconductor device 10-2 may include an active region 300, a source electrode 302, a gate electrode 304, and a drain electrode 306 according to an embodiment of the present invention. The source electrode 302, the gate electrode 304, and the drain electrode 306 may be electrically connected to corresponding regions of the active region 300, respectively. Since the first high voltage semiconductor element 10-1 and the second high voltage semiconductor element 10-2 are operated at a high voltage, the first high voltage semiconductor element 10-1 and the second high voltage semiconductor element 10-2 may be provided with an insulation doped region 110 around to achieve an electrical insulation effect between the first high voltage semiconductor element 10-1 and the second high voltage semiconductor element 10-2.
Fig. 2 is a schematic cross-sectional view of a high voltage semiconductor structure along line A-A' of fig. 1 according to an embodiment of the present invention. As shown in fig. 2, the high voltage semiconductor structure 10 may include, but is not limited to, a substrate 100, a semiconductor epitaxial layer 102, a semiconductor barrier layer 104, an insulating doped region 110, at least two semiconductor cap layers 210, 310, an interlayer dielectric layer 112, and at least two gate electrodes 204, 304.
According to an embodiment of the invention, the substrate 100 may include a substrate 100C and a composite layer 100M covering the substrate 100C. The composition of the substrate 100C may be a ceramic material of silicon carbide (SiC), aluminum oxide (Al 2O3), sapphire (sapphire), aluminum nitride, or a combination thereof. The composite layer 100M may be disposed along the surface of the substrate 100C, for example, but not limited to, on the top surface of the substrate 100C and the bottom surface of the substrate 100C, or even on the side surface of the substrate 100C. Each composite layer 100M may include a stack of insulating layers and a seed layer. According to an embodiment of the present invention, for the composite material layers 100M respectively located on the top surface and the bottom surface of the substrate 100C, the composite material layers 100M may each include a first insulating layer, a seed layer, and a second insulating layer in order along a direction away from the substrate 100C. The first insulating layer and the second insulating layer may be single or multiple insulating material layers, respectively, such as oxide, nitride, oxynitride, or other suitable insulating material, and the seed layer may be a semiconductor material, such as silicon, but is not limited thereto. According to an embodiment of the present invention, each of the composite material layers 100M may include an oxide layer, a semiconductor layer, a nitride layer, and an oxide layer sequentially stacked in a direction away from the substrate 100C, but not limited thereto. In the case where the base material 100C is a ceramic base, since the mechanical strength is higher than that of a single crystal silicon base, the base material 100 is less likely to be broken or bent. In addition, since the ceramic substrate has higher electrical insulation than the monocrystalline silicon substrate, the substrate 100 can withstand higher voltages.
According to an embodiment of the present invention, in the case where the first high voltage semiconductor device 10-1 and the second high voltage semiconductor device 10-2 are both high electron mobility transistors, a nitride layer, a superlattice layer (super LATTICE LAYER), and a high resistance layer may be selectively provided between the semiconductor epitaxial layer 102 and the substrate 100, but not limited thereto. Wherein a nitride layer may be disposed on the substrate 100 with fewer lattice defects, thereby improving the epitaxial quality of a semiconductor layer (e.g., semiconductor epitaxial layer 102) disposed on the nitride layer. The superlattice layer may be used to reduce the degree of lattice mismatch (LATTICE MISMATCH) between the substrate 100 and a semiconductor layer (e.g., the semiconductor epitaxial layer 102) disposed on the superlattice layer, as well as to reduce stress caused by the lattice mismatch. The high-resistance layer has a higher resistivity than other semiconductor layers, and thus can prevent leakage current from occurring between the semiconductor layer (e.g., semiconductor epitaxial layer 102) disposed on the high-resistance layer and the substrate 100.
The semiconductor epitaxial layer 102 may include one or more III-V semiconductor layers, and the III-V semiconductor layers may be GaN, alGaN, inGaN or InAlGaN, but are not limited thereto. According to an embodiment of the present invention, the semiconductor epitaxial layer 102 may include a semiconductor buffer layer and a semiconductor channel layer from bottom to top. The semiconductor channel layer is an undoped III-V semiconductor, for example undoped-GaN (u-GaN). According to an embodiment of the present invention, the semiconductor channel layer may also be one or more doped III-V semiconductor layers, such as a P-type III-V semiconductor layer. The dopant of the P-type group III-V semiconductor layer may be Cd, fe, mg or Zn, but is not limited thereto.
The semiconductor barrier layer 104 may comprise one or more III-V semiconductor layers and may have a composition different from that of the III-V semiconductor of the semiconductor channel layer. For example, the semiconductor barrier layer 104 may include AlN, al yGa(1-y) N (0 < y < 1), or a combination thereof. According to one embodiment, the semiconductor barrier layer 104 may be an N-type III-V semiconductor, such as an AlGaN layer, but is not limited thereto.
In addition, according to an embodiment of the present invention, the semiconductor channel layer on the semiconductor epitaxial layer 102 may directly contact the semiconductor barrier layer 104, so that a carrier flow region, such as a two-dimensional electron gas (2-DEG) region, may be formed in a region of the semiconductor epitaxial layer 102 adjacent to the semiconductor barrier layer 104. The semiconductor cap layers 210, 310 may be separated from each other and may each be one or more P-type III-V semiconductor layers, such as P-type GaN layers, and the dopant may be a metal dopant selected from Mg, cd, or Zn.
The insulating doped region 110 may be located in the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104 on both sides of the semiconductor cap layers 210, 310, and the insulating doped region 110 is preferably located between the two semiconductor cap layers 210, 310 separated from each other without overlapping the semiconductor cap layers 210, 310. In accordance with an embodiment of the present invention, the insulating doped region 110 may be formed, for example, by applying external energy to break the crystal lattice of the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104, or by performing an ion implantation process to implant specific non-semiconductor dopants into the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104. The dopants used to form the insulating doped region 110 may include, but are not limited to, helium, argon, nitrogen, phosphorus, arsenic, oxygen, or combinations thereof.
An interlayer dielectric layer 112 may be disposed on the insulating doped region 110 and covers the semiconductor cap layers 210, 310. An interconnect structure may optionally be further provided in the interlayer dielectric 112 to electrically connect to the semiconductor cap layers 210, 310 or the semiconductor barrier layer 104, but is not limited thereto.
The gate electrodes 204, 304 may be disposed on top of the interlayer dielectric layer 112 and electrically connected to the corresponding semiconductor cap layers 210, 310. According to an embodiment of the present invention, the gate electrodes 204 and 304 and other electrodes, such as source and drain electrodes, disposed in the first high voltage semiconductor device 10-1 and the first high voltage semiconductor device 10-2 are conductive materials, such as Au, ni, pt, pd, ir, ti, cr, W, al, cu, taN, tiN, WSi 2, combinations thereof, or the like.
Fig. 3 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the invention. As shown in fig. 3, the high voltage semiconductor structure 10 shown in fig. 3 includes insulating pillars 120 surrounding the active regions 200, 300 of the high voltage semiconductor elements 10-1, 10-2 in addition to the insulating doped region 110, similar to the high voltage semiconductor structure 10 shown in the embodiment of fig. 2. According to an embodiment of the invention, the insulating pillar 120 may surround the periphery of the active regions 200, 300. According to an embodiment of the present invention, the insulating column 120 may include a plurality of insulating columns (or referred to as sub-insulating columns), so that the insulating columns may be separately disposed and respectively surround the periphery of the active region 200 and the active region 300. In an embodiment of the present invention, the insulating pillars 120 may be formed earlier than the gate electrodes 204, 304, the source electrodes 202, 302, or the drain electrodes 206, 306 are formed to ensure the aspect ratio (aspect ratio) of the insulating pillars 120. By setting the dimensions of the insulating pillars 120 and the insulating doped regions 110 to a specific range, optimal electrical performance can be achieved, as will be further described in table 1 below.
Fig. 4 is a schematic cross-sectional view of a high voltage semiconductor structure along line A-A' of fig. 3 according to an embodiment of the present invention. As shown in fig. 4, the insulating column 120 may include a plurality of insulating columns, such as a first insulating column 120_1, a second insulating column 120_2, and a third insulating column 120_3, according to an embodiment of the present invention. The insulating column 120 may be located between the high voltage semiconductor elements 10-1, 10-2, for example, between the semiconductor cap layers 210, 310. In addition, the insulating pillars 120 are not limited to being located only on one side of the semiconductor cap layer 210 or the semiconductor cap layer 310, and the insulating pillars 120 may be located on both sides of the semiconductor cap layer 210 or the semiconductor cap layer 310, or further around the periphery of the semiconductor cap layer 210 or the semiconductor cap layer 310. According to an embodiment of the present invention, at least one of the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may penetrate the insulating doped region 110 and the composite layer 100M and directly contact the insulating doped region 110 and the substrate 100C. In accordance with an embodiment of the present invention, when the insulating doped region 110 is disposed in the semiconductor barrier layer 104 and the semiconductor epitaxial layer 102, the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may be considered to penetrate through the semiconductor barrier layer 104 and the semiconductor epitaxial layer 102 at the same time. The insulating column 120 may have a single-layer structure or a composite structure, for example, a single-layer structure including only an insulating material, or a composite structure including both an insulating material and a conductive material embedded in the insulating material, but is not limited thereto. According to an embodiment of the present invention, the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may each have a width L 1、L2、L3, and the first insulating pillar 120_1 and the third insulating pillar 120_3 and the semiconductor cap layer 210 and the semiconductor cap layer 310 may have a spacing S 1 and a spacing S 4, respectively, and the first insulating pillar 120_1, The second insulating column 120_2 and the third insulating column 120_3 may have a space S 2 and a space S 3 therebetween. According to an embodiment of the present invention, the first insulating columns 120_1, the second insulating columns 120_2, and the third insulating columns 120_3 may be equally spaced, i.e. the spacing S 2 is equal to the spacing S 3. According to an embodiment of the invention, the width L 1、L2、L3 of the insulating columns 120 may be smaller than the spacing S 2、S3 between the insulating columns 120.
According to an embodiment of the invention, the insulating column 120 may be formed after the formation of the insulating doped region 110, but before the formation of the interlayer dielectric layer 112, but is not limited thereto. For example, after performing an ion implantation process to form the insulating doped region 110, at least one trench may be formed in the insulating doped region 110 by photolithography and etching processes, and the bottom of the trench may be deep enough to reach the top surface of the substrate 100C to expose the substrate 100C in the trench. Thereafter, a suitable deposition process, such as a chemical vapor deposition process or a spin-on process, may be performed to fill the trenches with an insulating material, thereby forming the insulating columns 120 as shown in fig. 4. An interlayer dielectric layer 112 may be further formed on the insulating pillars 120, and at least one electrode, such as gate electrodes 204, 304, may be formed on a surface of the interlayer dielectric layer 112.
In order to further reduce the thickness of the substrate 100, a thinning process (patterning) may be performed on the back surface of the substrate 100 after the electrode is formed on the surface of the interlayer dielectric layer 112 to completely remove the composite layer 100M located on the bottom surface of the substrate 100C or to further remove a portion of the substrate 100C until the substrate 100 is thinned to a predetermined thickness according to an embodiment of the present invention.
According to one embodiment of the present invention, a method of operating a high voltage semiconductor structure is provided. First, a high voltage semiconductor structure, such as the high voltage semiconductor structure 10 shown in fig. 1,2 or3, 4, is provided. Thereafter, an electrical signal may be applied to the high voltage semiconductor structure 10 with the ambient temperature in a specific interval. According to an example, a voltage higher than 200 volts (V) may be applied to the drain electrode 202 of the first high voltage semiconductor element 10-1 under the condition that the ambient temperature falls within the interval of 15 to 300 ℃, and the magnitude of the current transferred from the drain electrode 302 of the second high voltage semiconductor element 10-2 may be measured. According to another example, it is possible to apply a voltage increasing from-800V to within 800V to the drain electrode 202 of the first high voltage semiconductor element 10-1 under the condition that the ambient temperature falls within the interval of 15 to 300 ℃, and measure the relationship of I D and V G of the second high voltage semiconductor element 10-2.
The electrical behavior of the high voltage semiconductor structure of the present invention is described correspondingly below. The high-voltage semiconductor structure may be, for example, the high-voltage semiconductor structure 10 shown in fig. 1, 2, 3, and 4, and the high-voltage semiconductor devices 10-1 and 10-2 are all high-electron mobility transistors.
According to an embodiment of the present invention, a voltage of more than 200V to 800V may be applied to the drain electrode 202 of the first high voltage semiconductor device 10-1 as shown in fig. 2 and 4, respectively, at an ambient temperature of 25 ℃, and the value of the current transferred from the drain electrode 302 of the second high voltage semiconductor device 10-2 may be measured. In addition, for the high voltage semiconductor structure shown in fig. 2, the lateral dimensions of the insulation doped region 110 between adjacent high voltage semiconductor elements 10-1, 10-2 may be adjusted such that the insulation doped region 110 has unequal lateral dimensions, and the above measurements are performed for the corresponding high voltage semiconductor structure 10. Similarly, the number of insulating pillars 120 may be adjusted for the high voltage semiconductor structure shown in fig. 4, and the above measurements may be made for the corresponding high voltage semiconductor structure 10. The results of the above measurement are shown in table 1 below.
TABLE 1
Note 1 the number of insulating columns refers to the number of insulating columns between two adjacent high voltage semiconductor devices 2 the overall insulating region width refers to the overall insulating region width between two adjacent active regions in the high voltage semiconductor structure
Note 3 that when the drain electrode of one high voltage semiconductor device outputs a prescribed current value, the voltage value to be applied to the drain electrode of the adjacent high voltage semiconductor device
From the results shown in table 1, it can be seen that when the high voltage semiconductor structure 10 includes the insulation doped region 110, or includes both the insulation doped region 110 and the insulation column 120, a voltage of at least 950V is applied to the drain electrode 202 of the high voltage semiconductor device 10-1, and the drain electrode 302 of the adjacent high voltage semiconductor device 10-2 generates a current of 1 nA. In addition, the high voltage semiconductor structure 10 including both the insulation doped region 110 and the insulation column 120 has a higher voltage withstand capability than the high voltage semiconductor structure 10 including only the insulation doped region 110. In addition, when the number of the insulating columns 120 reaches 3, the voltage-withstanding capability is saturated, so that the dimensions of the insulating columns 120 and the insulating doped regions 110 can be set within a specific range to achieve the optimal electrical performance in order to avoid the insulating columns 120 occupying excessive die area.
According to an embodiment of the present invention, it is possible to apply voltages of-200V to the drain electrode 202 of the first high voltage semiconductor device 10-1 shown in fig. 2 and 4, respectively, at an ambient temperature of 25 ℃, and measure the relationship of I D and V G of the second high voltage semiconductor device 10-2. The results of the measurement are shown in fig. 5 and 6, respectively. Fig. 5 and 6 are electrical characteristics of the high voltage semiconductor structure according to the embodiment of the invention at normal temperature. Wherein, fig. 5 corresponds to the electrical characteristics of the high voltage semiconductor structure 10 shown in fig. 2, and fig. 6 corresponds to the electrical characteristics of the high voltage semiconductor structure 10 shown in fig. 4. As shown in fig. 5 and 6, the relationship of I D and V G of the second high-voltage semiconductor element 10-2 can be maintained substantially constant regardless of the magnitude of the voltage applied to the drain electrode 202 of the first high-voltage semiconductor element 10-1. In other words, the threshold voltage of the second high voltage semiconductor element 10-2 does not fluctuate due to the voltage applied to the first high voltage semiconductor element 10-1.
Similarly, according to an embodiment of the present invention, a voltage of-500V to 500V may be applied to the drain electrode 202 of the first high voltage semiconductor device 10-1 as shown in fig. 2 and 4, respectively, at an ambient temperature of 150 ℃, and the relationship of I D and V G of the second high voltage semiconductor device 10-2 may be measured. The results of the measurement are shown in fig. 7 and 8, respectively. Fig. 7 and 8 are electrical characteristics of a high voltage semiconductor structure at high temperature in accordance with an embodiment of the present invention. Wherein fig. 7 corresponds to the electrical characteristics of the high voltage semiconductor structure 10 shown in fig. 2, and fig. 8 corresponds to the electrical characteristics of the high voltage semiconductor structure 10 shown in fig. 4. As shown in fig. 7, when a negative voltage or a positive voltage is applied to the drain electrode 202 of the first high voltage semiconductor device 10-1, the relationship between I D and V G of the second high voltage semiconductor device 10-2 fluctuates, in other words, the threshold voltage of the second high voltage semiconductor device 10-2 fluctuates due to the voltage applied to the first high voltage semiconductor device 10-1. Further, as the voltage applied to the first high voltage semiconductor element 10-1 gradually increases, the degree of shift of the threshold voltage of the second high voltage semiconductor element 10-2 becomes more remarkable. In contrast, as shown in fig. 8, the relationship between I D and V G of the second high-voltage semiconductor device 10-2 can be maintained substantially constant regardless of the magnitude of the voltage applied to the drain electrode 202 of the first high-voltage semiconductor device 10-1. In other words, the threshold voltage of the second high voltage semiconductor element 10-2 does not fluctuate due to the voltage applied to the first high voltage semiconductor element 10-1.
Fig. 9 is a schematic top view of a chip structure according to an embodiment of the invention. As shown in fig. 9, the chip structure 1 may be disposed in a chip area a of the wafer, and the periphery of the chip area a may be surrounded by a scribe line area B. The chip structure 1 may include at least one high voltage semiconductor device 20 and a low voltage semiconductor device (e.g., a logic device 30 or a memory device 40), and the high voltage semiconductor device 20 may be surrounded by an insulating region 22. The high voltage semiconductor device 20 may be a high electron mobility transistor as described in the above embodiments, and the insulating region 22 may be provided with the insulating doped region and/or the insulating column.
Fig. 10 is a schematic top view of a chip structure according to an embodiment of the invention. The chip structure 1in fig. 10 and the chip structure 1in fig. 9 mainly differ in that the chip structure 1in fig. 10 may include at least two high-voltage semiconductor elements 20, and the high-voltage semiconductor elements 20 may each be surrounded by an insulating region 22.
FIG. 11 is a schematic cross-sectional view of the high voltage semiconductor structure along line B-B' of FIG. 10 according to one embodiment of the present invention. As shown in fig. 11, according to an embodiment of the present invention, each high voltage semiconductor device 20 may include, from bottom to top, a substrate 100, a silicon-containing semiconductor layer 101, a semiconductor epitaxial layer 102, a semiconductor barrier layer 104, and semiconductor cap layers 210 and 310, and two-dimensional electron gas may exist at an interface between the semiconductor channel layer 105 and the semiconductor barrier layer 104 (as indicated by dotted lines). In addition, the adjacent high voltage semiconductor elements 20 may be connected in series to the source electrode 302 of one high voltage semiconductor element 20 to the drain electrode 206 of another high voltage semiconductor element 20 through the conductive line 320, but is not limited thereto. According to an embodiment of the present invention, the insulating doping region 110 and the insulating column 120 may be disposed between and around the adjacent high voltage semiconductor elements 20. The insulating doped region 110 may be formed by doping or damaging the semiconductor barrier layer 104, the semiconductor channel layer 105, and/or a portion of the semiconductor buffer layer 103. An upper portion of the insulating pillar 120 may be disposed in the insulating doped region 110, and a lower portion of the insulating pillar 120 may penetrate through the semiconductor buffer layer 103 and the silicon-containing semiconductor layer 101, or further penetrate through the composite material layer 100M.
According to the embodiments described above, the high-voltage semiconductor device in the high-voltage semiconductor structure can be prevented from affecting the electrical performance of other high-voltage semiconductor devices and low-voltage semiconductor devices by providing the insulation doped region in the high-voltage semiconductor structure or providing the insulation doped region and the insulation column simultaneously. In addition, for the high-voltage semiconductor structure comprising the insulated doped region and the insulated column, the problem of threshold voltage shift of the high-voltage semiconductor structure is less likely to occur at high temperature.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (11)
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| TWI658586B (en) * | 2018-04-11 | 2019-05-01 | 世界先進積體電路股份有限公司 | Semiconductor structures and method for fabricating the same |
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| US10319716B2 (en) * | 2017-05-05 | 2019-06-11 | Newport Fab, Llc | Substrate isolation for low-loss radio frequency (RF) circuits |
| US10629475B2 (en) * | 2017-12-22 | 2020-04-21 | Vanguard International Semiconductor Corporation | Semiconductor device with two-part insulation structure within non-active region |
| TWI692868B (en) * | 2019-04-16 | 2020-05-01 | 世界先進積體電路股份有限公司 | Semiconductor structure |
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