TWI692868B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed at the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and at the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias.

Description

Semiconductor structure

The present invention relates to a semiconductor structure, and in particular to a semiconductor structure having a pair of via holes in contact with a seed layer.

GaN-based semiconductor materials have many excellent material characteristics, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterointerface structures ).

However, in the operation of the High Electron Mobility Transistor (HEMT) device, the lower epitaxial layer in the device structure contains many negatively charged impurities due to its own material characteristics. At this time, if a high voltage is applied , Then these negative charges will be attracted towards the upper element and affect the operation of the upper element. In order to solve this problem in the prior art, the silicon substrate under the epitaxial layer is usually grounded to discharge negative charges of impurities. However, this method cannot be applied to various substrates.

With the development of gallium nitride-based semiconductor materials, these semiconductor devices using gallium nitride-based semiconductor materials are used in more severe working environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, semiconductor devices with gallium nitride-based semiconductor materials still need to be further improved to overcome the challenges they face.

Some embodiments of the present invention provide a semiconductor structure including: a substrate having an active region and an isolation region, an insulating layer on the substrate, a seed layer on the insulating layer, a compound semiconductor layer on the seed layer, a compound Gate structure on the semiconductor layer and in the active region, isolation structure on the substrate and in the isolation region, a pair of vias in the isolation region and on both sides of the gate structure, on the substrate and in the gate The source structure and the drain structure on both sides of the structure. The pair of vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure are electrically connected to the seed layer through the via holes respectively.

Some embodiments of the present invention provide a semiconductor structure including: a ceramic substrate having an active region and an isolation region, an insulating layer on the substrate, a seed layer on the insulating layer, and a seed layer on the seed layer A compound semiconductor layer, a gate structure on the compound semiconductor layer and in the active region, a source structure and a drain structure on the substrate and on both sides of the gate structure. The source structure and the drain structure are electrically connected to the seed layer respectively.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of components and their configurations are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the first element is formed on the second element in the description, it may include an embodiment where the first and second elements are in direct contact, or may include additional elements formed between the first and second elements , So that they do not directly contact the embodiment. In addition, embodiments of the present invention may repeat reference numerals and/or letters in different examples. This repetition is for conciseness and clarity, not for expressing the relationship between the different embodiments discussed.

In addition, relative terms may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spatial relative terms In order to facilitate the description of the relationship between one or more elements or features in the illustration and the other element or features, these spatial relative terms include different orientations of the device in use or in operation, as well as the description in the drawings Position. When the device is turned to different orientations (rotated 90 degrees or other orientations), the relative adjectives used in the space will also be interpreted according to the turned orientation.

Here, the terms “about”, “approximately” and “approximately” generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the description is an approximate quantity, that is, if there is no specific description of "about", "approximate", "approximately", "about", "approximate", "" The meaning of "approximately".

Although the components in some of the described embodiments are described in a specific order, these descriptions can also be performed in other logical orders. The semiconductor structure in the embodiment of the present invention may incorporate other components. In different embodiments, some components may be replaced or omitted.

The semiconductor structure provided by the embodiments of the present invention electrically connects the source structure and the drain structure in the semiconductor structure to the seed layer on the substrate through a pair of via holes in the isolation region of the substrate. With the configuration of the above-mentioned via holes, a voltage difference (that is, a voltage difference between the source and the drain) can be generated inside the seed layer, so that the power line extends to the film layer (such as an insulating layer) located below the seed layer. The seed layer with a voltage difference inside will not shield the power lines of the high electric field region in the semiconductor structure, thereby redistributing the electric field and raising the breakdown voltage to allow the semiconductor device to be applied to high voltage operation.

FIG. 1A is a schematic cross-sectional view of an exemplary semiconductor structure 100 according to some embodiments of the present invention. According to some embodiments of the present invention, the semiconductor structure 100 includes a substrate 200 having an active region 201 and an isolation region 202, an insulating layer 210 disposed on the substrate 200, a seed layer 220 disposed on the insulating layer 210, and a seed layer Compound semiconductor layer 230 on 220, gate structure 300 disposed on compound semiconductor layer 230 and located in active area 210, source structure 400 and drain structure disposed on substrate 200 and located on both sides of gate structure 300 500, and a pair of vias 601, 602 passing through the isolation structure 240 provided in the isolation region 202.

In some embodiments, the substrate 200 may be a doped (eg, doped with p-type or n-type dopants) or an undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or the like Semiconductor substrate. In other embodiments, the substrate 200 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an alumina substrate (Al ₂ O ₃ ) (or called a sapphire substrate), or other Similar substrate. The above-mentioned ceramic substrate can be formed by powder metallurgy sintering ceramic powder at high temperature.

The insulating layer 210 provided on the substrate 200 is a film layer with good thermal stability and high quality at high temperature. In some embodiments, the insulating layer 210 is, for example, a high-quality silicon oxide insulating layer made of tetraethoxysilane (TEOS). In other embodiments, the insulating layer 210 is a dielectric layer formed by plasma-enhanced chemical vapor deposition (PECVD), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide , Other similar materials or combinations of the foregoing. According to some embodiments of the present invention, the insulating layer 210 may provide a surface of higher quality to facilitate subsequent formation of other film layers of the semiconductor structure on the surface. In some embodiments, the thickness of the insulating layer may range from about 0.5 microns to about 10 microns, such as about 2 microns.

In some embodiments, the material of the seed layer 220 formed on the insulating layer 210 may be silicon. In other embodiments, the seed layer 220 may be doped with other semiconductor materials such as silicon carbide (for example, silicon carbide doped with nitrogen or phosphorus may form an n-type semiconductor, and doped with aluminum, boron, gallium, or beryllium It is formed by forming a p-type semiconductor), a group III-V (III-V) compound semiconductor material, or other similar materials. In other embodiments, the seed layer 220 may include aluminum oxide (Al ₂ O ₃ ). In some embodiments, the seed layer 220 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), A molecular beam epitaxy (MBE), a combination of the foregoing, or a similar method is conformally formed on the insulating layer 210.

In some embodiments, the compound semiconductor layer 230 formed on the seed layer 220 may include a buffer layer 231 disposed on the seed layer 220, a channel layer 232 disposed on the buffer layer 231, and a channel layer 232 Of the barrier layer 233.

The buffer layer 231 can reduce the strain of the channel layer 232 formed subsequently on the buffer layer 231 to prevent defects from being formed in the channel layer 232 above. The strain is caused by the mismatch between the channel layer 232 and the substrate 200. In some embodiments, the material of the buffer layer 231 may be AlN, GaN, Al _x Ga _1-x N (where 0<x<1), a combination of the foregoing, or other similar materials. The buffer layer 231 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or a similar method. In some embodiments, the thickness of the formed buffer layer 231 may range from about 0.5 microns to about 10 microns, such as about 3 microns. It is worth noting that although the buffer layer 231 has a single-layer structure in the embodiment shown in FIG. 1A, the buffer layer 231 may have a multi-layer structure (not shown) in other embodiments.

According to some embodiments of the present invention, two-dimensional electron gas (2DEG) (not shown) is formed on the heterogeneous interface between the channel layer 232 and the barrier layer 233. The semiconductor structure 100 shown in FIG. 1A is a high electron mobility transistor (HEMT) using two-dimensional electron gas (2DEG) as a conductive carrier. In some embodiments, the channel layer 232 may be a gallium nitride (GaN) layer, and the barrier layer 233 formed on the channel layer 232 may be a gallium aluminum nitride (AlGaN) layer, wherein the gallium nitride layer and the nitride The gallium aluminum layer may or may not have dopants (such as n-type dopants or p-type dopants). Both the channel layer 232 and the barrier layer 233 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing Or other similar methods. In some embodiments, the thickness of the formed channel layer 232 may range from about 300 nanometers to about 1 micrometer, such as about 0.6 micrometers. In some embodiments, the thickness of the formed barrier layer 233 may range from about 5 nm to about 30 nm, for example, about 25 nm.

Next, according to some embodiments of the present invention, an isolation structure 240 may be formed in the compound semiconductor layer 230 of the substrate 200 to define the active region 201 and the isolation region 202. In some embodiments, as shown in FIG. 1A, the bottom surface of the isolation structure 240 may be located in the buffer layer 231 included in the compound semiconductor layer 230. In other embodiments, the bottom surface of the isolation structure 240 may be flush with the bottom surface of the buffer layer 231 and in contact with the seed layer 220 (not shown). In some embodiments, the formation of the isolation structure 240 can isolate the two-dimensional electron gas (2DEG) on the heterogeneous interface formed between the channel layer 232 and the barrier layer 233 in the active region 201.

According to some embodiments of the present invention, the isolation structure 204 can be formed by destroying the crystal lattice structure of the compound semiconductor layer 230 at a predetermined position of the isolation structure 240, so that the compound semiconductor layer 230 of this portion loses the piezoelectric effect ( piezoelectricity) and cannot conduct electricity. In these embodiments, nitrogen (N), oxygen (O), or other suitable elements can be implanted into the compound semiconductor layer 230 (eg, a gallium nitride layer) by an ion implantation process, to The lattice structure thereof is destroyed, thereby transforming the compound semiconductor layer 230 at a predetermined position of the isolation structure 240 into the isolation structure 240. In other embodiments, the material of the isolation structure 240 may be a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, similar materials, or a combination of the foregoing, and trench isolation may be formed through an etching process and a deposition process The structure is in the compound semiconductor layer 230.

Next, a gate structure 300 is formed on the compound semiconductor layer 230 (for example, the barrier layer 233) in the active region 201, a source structure 400 and a drain structure 500 are formed on both sides of the gate structure 300, and an interlayer dielectric is formed Electrical layers (such as the first dielectric layer 250, the second dielectric layer 260, and the third dielectric layer 270) are on the compound semiconductor layer 230 to form the semiconductor structure 100. According to some embodiments of the present invention, the semiconductor structure 100 is a high electron mobility transistor (HEMT). In some embodiments, the gate structure 300 includes a gate electrode 301 and a gate metal layer 302, wherein the gate electrode 301 is located on the barrier layer 233, and the gate metal layer 302 is located on the gate electrode 301 and is electrically connection. In other embodiments, an optional doped compound semiconductor layer 234 may be included between the gate electrode 301 and the barrier layer 233, details of which will be further described later. The source structure 400 includes a source electrode 401, a source contact 402, and a source metal layer 403 electrically connected to each other, and the drain structure 500 includes a drain electrode 501, a drain contact 502 electrically connected to each other, And drain metal layer 503. In some embodiments, the source electrode 401 and the drain electrode 501 located on both sides of the gate electrode 301 are located in the active region 201 and pass through the barrier layer 233 to contact the channel layer 232.

In some embodiments, the material of the gate electrode 301 may be a conductive material, such as metal, metal nitride, or semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations of the foregoing, or multilayers of the foregoing. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. The above conductive material may be formed on the barrier layer by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods On 233, the gate electrode 301 is formed through a patterning process.

According to some embodiments of the present invention, before forming the gate electrode 301, a doped compound semiconductor layer 234 may be formed on the barrier layer 233, and then the gate electrode 301 is formed on the doped compound semiconductor layer 234. By disposing the doped compound semiconductor layer 234 between the gate electrode 301 and the barrier layer 233, the generation of two-dimensional electron gas (2DEG) under the gate electrode 301 can be suppressed to achieve the normally-off state of the semiconductor device 100. In some embodiments, the material of the doped compound semiconductor layer 234 may be p-type doped or n-type doped gallium nitride (GaN). The step of forming the doped compound semiconductor region 234 may include depositing a doped compound semiconductor layer (not shown) on the barrier layer 233 through an epitaxial growth process and performing a patterning process thereon to form the doped compound semiconductor layer 234 This corresponds to the position where the gate electrode 301 is to be formed. In some embodiments, the thickness of the formed doped compound semiconductor layer 234 may range from about 50 nm to about 100 nm.

The source electrode 401 and the drain electrode 501 formed on both sides of the gate electrode 301 and located in the active region 201 include materials that are substantially the same as the gate electrode 301, so they are not described here. In some embodiments, as shown in FIG. 1A, the source electrode 401 and the drain electrode 501 pass through the barrier layer 233 and contact the channel layer 231.

In some embodiments, the gate metal layer 302, the source contact 402, the source metal layer 403, the drain contact 502, and the drain metal layer 503 can be formed by a deposition process and a patterning process, and their materials Contains conductive materials, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), Nickel silicide (NiSi), cobalt silicide (CoSi), tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN) 1. Titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), metal oxides, metal alloys, other suitable conductive materials, or a combination of the foregoing.

According to some embodiments of the present invention, as shown in FIG. 1A, the gate electrode 301 is buried in the first dielectric layer 250, and the gate metal layer 302 is buried in the first dielectric layer 250 and formed in the first dielectric In the second dielectric layer 260 on the electrical layer 250. Moreover, the source contacts 402 and the drain contacts 502 located on both sides of the gate structure 300 pass through the first dielectric layer 250 and the second dielectric layer 260 formed on the compound semiconductor layer 230, respectively The electrode 402 is in contact with the drain electrode 502, and the source metal layer 403 and the drain metal layer 503 are formed on the second dielectric layer 260 and are electrically connected to the source contact 402 and the drain contact 502, respectively.

In some embodiments, the first dielectric layer 250 and the second dielectric layer 260 may include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, and tetraethoxysilane (tetraethoxysilane, TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric materials, and/or other suitable dielectric materials. Low dielectric constant dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, and amorphous carbon fluoride (fluorinated carbon), parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma can be used High density plasma CVD (HDPCVD), other suitable methods, or a combination of the foregoing, the above dielectric materials are deposited on the compound semiconductor layer 230 (such as the barrier layer 233) and the isolation structure 240 to form the first dielectric Electrical layer 250 and second dielectric layer 260.

According to some embodiments of the present invention, the pair of vias 601 and 602 included in the semiconductor structure 100 shown in FIG. 1A are disposed in the isolation region 202 and located on both sides of the gate structure 300. In some embodiments, the pair of vias may be through-GaN via (TGV). The via holes 601 and 602 pass through the second dielectric layer 260, the first dielectric layer 250, the isolation structure 240 and the buffer layer 231 in the isolation region 202 and contact the seed layer 220. In the embodiment where the bottom surface of the isolation structure 240 directly contacts the seed layer 220, the via holes 601, 602 passing through the isolation structure 240 may directly contact the seed layer 220 without passing through the buffer layer 231 (not shown). By arranging the via holes 601 and 602 in the isolation region 202, it is possible to prevent the via holes 601 and 602 from contacting the two-dimensional electron gas (2DEG) on the heterogeneous interface formed between the channel layer 232 and the barrier layer 233 to generate electricity Sexual abnormality.

Referring to FIG. 1A, the source structure 400 and the drain structure 500 are electrically connected to the seed layer 220 through via holes 601 and via holes 602, respectively. Specifically, the source structure 400 is electrically connected to the seed layer 220 by contacting the source metal layer 403 and the via hole 601 across the active region 201 and the isolation region 202, and the drain structure 500 is obtained by The drain metal layer 503 across the active region 201 and the isolation region 202 is electrically connected to the seed layer 220 by contact with the via 602. According to some embodiments of the present invention, the voltage difference generated inside the seed layer 220 electrically connected to the source structure 400 and the drain structure 500 may be substantially the same as the voltage between the source electrode 401 and the drain electrode 501 difference.

According to some embodiments of the present invention, the formation of the vias 601 and 602 includes the compound semiconductor layer 230, the isolation structure 240, the first dielectric layer 250, and the second dielectric layer first performing lithography and etching processes on the isolation region 202 260, to form a pair of holes (not shown) located on both sides of the gate structure 300. Next, a conductive material is filled into the pair of holes to form via holes 601, 602. In some embodiments, the conductive material may be selected from the aforementioned materials for forming the gate metal layer 302, the source contact 402, the source metal layer 403, the drain contact 502, and the drain metal layer 503, so I will not repeat them here. According to some embodiments of the present invention, the diameters of the via holes 601 and 602 may be in the range of about 0.5 micrometer (um) to about 5 micrometers. Through the configuration of the vias 601 and 602, a voltage difference (that is, the voltage difference between the source and the drain) can be generated inside the seed layer, so that the power line extends to the film layer (such as an insulating layer) below the seed layer In order to redistribute the electric field and increase the breakdown voltage. Moreover, applying the configuration of the above-mentioned vias 601 and 602 to a semiconductor device using a ceramic substrate can significantly improve its performance under high-voltage operation.

Please refer to FIG. 1B together. The semiconductor structure 100 ′ shown in FIG. 1B is substantially the same as the semiconductor structure 100 shown in FIG. 1A. The difference is that the via 601 included in the semiconductor structure 100 ′, 602 further penetrates the seed layer 220 and contacts the insulating layer 210. In some embodiments, the bottom surfaces of the via holes 601 and 602 may be located in the insulating layer 210 (ie, as shown in FIG. 1B). In other embodiments, the bottom surfaces of the via holes 601 and 602 may contact the top surface of the insulating layer 210 (not shown).

In summary, through the configuration of the via holes 601 and 602, a voltage difference (that is, the voltage difference between the source electrode 401 and the drain electrode 501) can be generated inside the seed layer 220, so that the power line extends to the crystal The insulating layer 210 under the seed layer 220. The seed layer 220 having a voltage difference inside does not shield the power lines of the high electric field region (for example, the compound semiconductor layer 230 under the gate structure 300 in the active region 201) in the semiconductor structures 100, 100', thereby further redistributing the electric field. In this way, the insulating layer 210 in the semiconductor structures 100, 100' can withstand the applied voltage together with the compound semiconductor layer 230 formed on the insulating layer 210, thereby increasing the breakdown voltage to allow the semiconductor device 100 , 100' applies to high voltage operation.

It is worth noting that although only one pair of vias 601 and 602 is shown here, the embodiment of the present invention may also include multiple pairs of vias that are electrically connected to the source structure 400 and the seed layer 220 at the same time. The drain structure 500 and the seed layer 220 (not shown). In other embodiments, the number of vias electrically connecting the source structure 400 and the seed layer 220 may be different from the number of vias electrically connecting the source structure 500 and the seed layer 220 (not shown).

According to some embodiments of the present invention, the semiconductor structure 100 shown in FIG. 1A may include a third dielectric layer 270 formed on the second dielectric layer 260, which covers the source metal layer 403 and the drain metal layer 503, and a metal layer 280 that is electrically connected to the source metal layer 403 and the drain metal layer 503 through the third dielectric layer 270. In some embodiments, the material of the third dielectric layer 270 may be selected from the aforementioned materials used to form the first dielectric layer 250 and the second dielectric layer 260, and the material and formation method of the metal layer 280 are substantially the same as the source The polar metal layer 403 and the drain metal layer 503 are not repeated here. It is worth noting that although the embodiment of the present invention only shows a single third dielectric layer 270 and a single metal layer 280, the embodiment of the present invention is not limited thereto. The number of film layers of the third dielectric layer 270 and the metal layer 280 can be adjusted according to product design.

According to some embodiments of the present invention, the semiconductor structure 100 shown in FIG. 1A may have various configurations in the top view, such as the semiconductor structures 100A, 100B shown in FIGS. 2A, 2B, and 2C. , And 100C. For example, the semiconductor structure 100 shown in FIG. 1A may correspond to the section AA′ shown in FIG. 2A, where the section AA′ does not pass through the opening 700 of the seed layer 220 . In other embodiments, the seed layer 220 of the semiconductor structure 100 shown in FIG. 1A may not have an opening (not shown).

FIG. 2A is a partial top view illustrating an exemplary semiconductor structure 100A according to some embodiments of the present invention. It is worth noting that in order to concisely describe the embodiments of the present invention and highlight its features, not all structures of the semiconductor structure 100A are shown in FIG. 2A. Referring to FIG. 2A, the semiconductor structure 100A includes an active region 201, an isolation region 202 surrounding the active region 201, a gate structure 300 formed in the active region 210, a source structure 400, and a drain structure 500 formed in the isolation region 202 The via holes 601 and 602 in FIG. 2 and the seed layer 220 having a plurality of openings 700 in the active area 201. In some embodiments, the opening 700 of the seed layer 220 may expose the insulating layer 210 under the seed layer 220. According to some embodiments of the present invention, in the top view, the openings 700 in the active area 201 may be arranged in a matrix, as shown in FIG. 2A. For example, the matrix may include five rows and five columns of aligned openings 700.

FIG. 2B is a partial top view illustrating an exemplary semiconductor structure 100B according to other embodiments of the present invention. The semiconductor structure 100B shown in FIG. 2B is substantially similar to the semiconductor structure 100A shown in FIG. 2A, so it will not be repeated here. The difference between the semiconductor structure 100B and the semiconductor structure 100A is that the plurality of openings 700 in the seed layer 220 of the active region 201 in the semiconductor structure 100B are staggered with each other.

FIG. 2C is a partial top view illustrating an exemplary semiconductor structure 100C according to other embodiments of the present invention. The semiconductor structure 100C shown in FIG. 2C is roughly similar to the semiconductor structures 100A and 100B shown in FIGS. 2A and 2B, so they will not be repeated here. The difference between the semiconductor structure 100C and the semiconductor structures 100A, 100B is that the seed layer 220 located in the active region 201 in the semiconductor structure 100C has a plurality of elongated openings 800. As shown in FIG. 2C, the long axis of the elongated opening 800 extends parallel to the direction from the via hole 601 toward the via hole 602, and the elongated opening 800 is along the short axis direction in the active region 201 arrangement.

According to some embodiments of the present invention, the plurality of openings of the seed layer 220 formed in the active region 201 can form a high-impedance region to reduce the leakage current between the drain structure and the source structure. It is worth noting that the shape, number, size, and arrangement of the openings of the seed layer 220 shown in FIGS. 2A, 2B, and 2C are merely exemplary, and the configuration of the openings of the seed layer 220 may be based on The product design is adjusted, so the embodiments of the present invention are not limited to this.

In summary, the semiconductor structure provided by the embodiment of the present invention can generate a voltage difference inside the seed layer by electrically connecting the source structure and the drain structure to the seed layer through a pair of via holes Therefore, the power line can be extended to a film layer (for example, an insulating layer) located under the seed layer. According to an embodiment of the present invention, the seed layer with a voltage difference inside does not shield the power lines of the high electric field region (such as the compound semiconductor layer under the gate) in the semiconductor structure, thereby redistributing the electric field. In this way, the insulating layer in the semiconductor structure can withstand the applied voltage together with the compound semiconductor layer formed on the insulating layer, thereby improving the breakdown voltage and improving the performance of the semiconductor structure.

The above summarizes several embodiments so that those with ordinary knowledge in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention, Make various changes, substitutions and replacements.

100, 100’, 100A, 100B, 100C: semiconductor structure

200: base

201: Active area

202: Quarantine

210: insulating layer

220: Seed layer

230: Compound semiconductor layer

231: Buffer layer

232: channel layer

233: barrier layer

234: Doped compound semiconductor layer

240: Isolation structure

250: first dielectric layer

260: Second dielectric layer

270: third dielectric layer

280: metal layer

300: Gate structure

301: Gate electrode

302: Gate metal layer

400: source structure

401: source electrode

402: Source contact

403: source metal layer

500: Drain structure

501: Drain electrode

502: Drain contact

503: Drain metal layer

601, 602: via hole

700, 800: opening

A-A’: Profile

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale and are used for illustration only. In fact, the size of the element may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. FIG. 1A is a schematic cross-sectional view illustrating an exemplary semiconductor structure according to some embodiments of the present invention. FIG. 1B is a schematic cross-sectional view illustrating an exemplary semiconductor structure according to other embodiments of the present invention. FIG. 2A is a partial top view illustrating an exemplary semiconductor structure according to some embodiments of the present invention. FIG. 2B is a partial top view illustrating an exemplary semiconductor structure according to other embodiments of the present invention. FIG. 2C is a partial top view illustrating an exemplary semiconductor structure according to other embodiments of the present invention.

100: semiconductor structure

200: base

201: Active area

202: Quarantine

210: insulating layer

220: Seed layer

230: Compound semiconductor layer

231: Buffer layer

232: channel layer

233: barrier layer

234: Doped compound semiconductor layer

240: Isolation structure

250: first dielectric layer

260: Second dielectric layer

270: third dielectric layer

280: metal layer

300: Gate structure

301: Gate electrode

302: Gate metal layer

400: source structure

401: source electrode

402: Source contact

403: source metal layer

500: Drain structure

501: Drain electrode

502: Drain contact

503: Drain metal layer

601, 602: via hole

Claims (20)

A semiconductor structure includes: a substrate having an active region and an isolation region; an insulating layer on the substrate; a seed layer on the insulating layer; a compound semiconductor layer on the seed layer; A gate structure on the compound semiconductor layer and in the active region; an isolation structure on the substrate and in the isolation region; a pair of vias in the isolation region and in the gate structure Two sides, wherein the pair of vias pass through the isolation structure and contact the seed layer; and a source structure and a drain structure are located on the substrate and are located on both sides of the gate structure, wherein the source structure And the drain structure are electrically connected to the seed layer through the pair of via holes, respectively. The semiconductor structure as described in item 1 of the patent application scope, wherein the compound semiconductor layer includes: a buffer layer on the seed layer; a channel layer on the buffer layer and in the active region; and a barrier Layer on the channel layer and in the active area. The semiconductor structure as described in item 2 of the patent application range, wherein the thickness of the insulating layer is in the range of 0.5 μm to 10 μm, the thickness of the buffer layer is in the range of 0.5 μm to 10 μm, and the thickness of the channel layer is 300 nm The range of meters to 1 micrometer, and the thickness of the barrier layer is in the range of 5 nanometers to 30 nanometers. The semiconductor structure described in item 1 of the scope of the patent application further includes a dielectric layer on the compound semiconductor layer. The semiconductor structure as described in item 2 of the patent application scope, wherein the gate structure includes: a gate electrode layer on the barrier layer; and a gate metal layer on the gate electrode layer and in contact with the The gate electrode layer is electrically connected. The semiconductor structure as described in item 5 of the patent application scope further includes a doped compound semiconductor layer, the doped compound semiconductor layer is located between the gate electrode layer and the barrier layer. The semiconductor structure as described in item 1 of the patent application range, wherein the pair of vias further penetrates the seed layer and is in contact with the insulating layer. The semiconductor structure as described in item 2 of the patent application scope, wherein the source structure includes: a source electrode located in the active region and in contact with the channel layer through the barrier layer; a source contact located in The active region is in contact with the source electrode through the dielectric layer; and a source metal layer is located on the dielectric layer and is electrically connected to one of the source contact and the pair of vias. The semiconductor structure as described in item 8 of the patent application scope, wherein the drain structure includes: a drain electrode located in the active region and in contact with the channel layer through the barrier layer; a drain contact located in In contact with the drain electrode in the active region and through the dielectric layer; and a drain metal layer on the dielectric layer and electrically connected to the drain contact and the other of the pair of vias . The semiconductor structure as described in item 1 of the patent application scope, wherein the seed layer comprises silicon, silicon carbide, or aluminum oxide. The semiconductor structure as described in item 1 of the patent application scope, wherein the pore diameters of the pair of via holes are each in the range of 0.5 to 5 microns. The semiconductor structure as described in item 1 of the patent application scope, wherein in the top view, the seed layer includes a plurality of openings located in the active region. The semiconductor structure as described in item 12 of the patent application scope, wherein in the top view, the openings are arranged in a matrix. The semiconductor structure as described in item 12 of the patent application scope, wherein in the top view, the openings are staggered with each other. A semiconductor structure includes: a ceramic substrate having an active region and an isolation region; an insulating layer on the substrate; a seed layer on the insulating layer; a compound semiconductor layer on the seed layer A gate structure on the compound semiconductor layer and in the active region; and a source structure and a drain structure on the substrate and on both sides of the gate structure, wherein the source structure and The drain structures are electrically connected to the seed layer respectively. The semiconductor structure as described in item 15 of the patent application scope further includes: an isolation structure located on the substrate and located in the isolation region; and a pair of vias located in the isolation region and located on both sides of the gate structure Side, wherein the pair of vias pass through the isolation structure and contact the seed layer, and the source structure and the drain structure are electrically connected to the seed layer through the pair of vias, respectively. The semiconductor structure as recited in item 16 of the patent application range, wherein the pair of vias further penetrates the seed layer and is in contact with the insulating layer. The semiconductor structure as described in item 15 of the patent application range, wherein the compound semiconductor layer includes: a buffer layer on the seed layer; a channel layer on the buffer layer and in the active region; and a resistor The barrier layer is located on the channel layer and in the active area. The semiconductor structure as described in item 15 of the patent application range, wherein the ceramic substrate is an aluminum nitride substrate, a silicon carbide substrate, or an alumina substrate. The semiconductor structure as described in item 15 of the patent application scope, wherein in the top view, the seed layer includes a plurality of elongated openings located in the active region.

Images