TWI794609B - Semiconductor structures - Google Patents

Abstract

A semiconductor structure includes: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a source structure and a drain structure on opposite sides of the barrier layer; a doped compound semiconductor layer on the barrier layer, and the doped compound semiconductor layer has a first side adjacent to the source structure, a second side adjacent to the drain structure, and at least one opening exposing at least a portion of the barrier layer; a dielectric layer on the doped compound semiconductor layer and the barrier layer; and a gate structure on the doped compound semiconductor layer.

Description

semiconductor structure

The embodiments of the present invention relate to a semiconductor device, in particular to a semiconductor device with a doped compound semiconductor.

Gallium nitride-based (GaN-based) semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, gallium nitride-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, gallium nitride-based semiconductor materials have been widely used in light-emitting diode (light emitting diode, LED) components, high-frequency components, such as high electron mobility transistors (high electron mobility transistors, HEMTs) with heterogeneous interface structures. ).

During the manufacturing process of high electron mobility transistor components, the semiconductor material may be affected by the environment (such as the influence of temperature or elements in the environment), resulting in deactivation (deactivation), resulting in a decrease in the gate control of the device, which in turn affects The current driving capability also deteriorates the electrical uniformity performance of different batches of products with the same or similar process.

With the development of GaN-based semiconductor materials, these devices using GaN-based semiconductor materials are used in more severe working environments, such as higher frequency, higher temperature, or higher voltage. Therefore, semiconductor devices with gallium nitride-based semiconductor materials still need to be further improved to overcome the challenges faced.

An embodiment of the present invention provides a semiconductor structure, including: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer; a source structure and a drain structure located on both sides of the barrier layer; a doped compound semiconductor layer , located on the barrier layer, the doped compound semiconductor layer has a first side adjacent to the source structure, a second side adjacent to the drain structure, and at least one opening, the at least one opening exposes at least a part of the barrier layer; The dielectric layer is located on the doped compound semiconductor layer and the barrier layer; and the gate structure is located on the doped compound semiconductor layer.

An embodiment of the present invention provides a semiconductor structure, including: a substrate; a buffer layer located on the substrate; a channel layer located on the buffer layer; a barrier layer located on the channel layer; a source structure and a drain structure located on the barrier layer On both sides; the doped compound semiconductor layer is located on the barrier layer, wherein at least a part of the doped compound semiconductor layer is discontinuous in the first direction from the source structure to the drain structure; the dielectric layer is located on the doped on the hetero compound semiconductor layer and the barrier layer; and the gate structure on the doped compound semiconductor layer.

The following disclosure provides a number of embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are just examples, not intended to limit the embodiments of the present invention. For example, if a description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, or may include an additional element formed between the first and second elements , so that they are not in direct contact with the example. In addition, the embodiments of the present invention may repeat reference numerals and/or letters in various examples. This repetition is for the purpose of brevity and clarity and not to show the relationship between the different embodiments and/or configurations discussed.

Furthermore, terms relative to space may be used, such as "below", "below", "lower", "above", "higher", etc., for the convenience of description The relationship between one component or feature(s) and another component(s) or feature(s) in a drawing. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein shall also be interpreted in accordance with the turned orientation.

Some embodiments of the invention are described below, and additional steps may be provided before, during and/or after various stages described in these embodiments. Some of the described stages may be replaced or omitted in different embodiments. The semiconductor device structure may add additional components. Some of the described components may be substituted or omitted in different embodiments. Although some embodiments discussed perform steps in a particular order, the steps may be performed in another logical order. In addition, the term "about" as used herein indicates that a given quantity may vary based on the particular technology node associated with the target semiconductor device. In some embodiments, based on a specific technology node, the word "about" can mean that a given quantity is in the range of, for example, 10% to 30% of the value (for example: ±10%, ±20%, or ± 30%).

The semiconductor structure provided by the embodiments of the present invention improves electrical uniformity by reducing the proportion of the doped compound semiconductor layer in the semiconductor structure, thereby improving device performance. In some embodiments, the performance of the device can be further improved through the liner or protection layer disposed on the sidewall of the doped compound semiconductor layer and the barrier layer, and the liner layer disposed under the source electrode and the drain electrode.

FIG. 1 is a partial projected top view of a semiconductor structure according to some embodiments of the present invention. Fig. 2 is a schematic cross-sectional view of AA' in Fig. 1 according to some embodiments of the present invention. The semiconductor structure 200 includes: a substrate 110, a channel layer 112, a barrier layer 113, a source structure composed of a source electrode 114 and a source metal layer 122, a drain structure composed of a drain electrode 115 and a drain metal layer 123, a doped The hetero compound semiconductor layer 116 , the dielectric layer 117 , and the gate structure formed by the gate electrode 118 and the gate metal layer 119 . The substrate 110 may be a doped (eg doped with p-type or n-type dopants) or an undoped semiconductor substrate. For example, the substrate 110 may include: elemental semiconductors, including silicon or germanium; compound semiconductors, including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and/or or indium antimonide (InSb); alloy semiconductors, including silicon germanium alloys, phosphorus gallium arsenic alloys, arsenic aluminum indium alloys, arsenic aluminum gallium alloys, indium gallium arsenic alloys, indium gallium phosphorus alloys and/or indium arsenic gallium alloys, or A combination of the aforementioned materials. In some embodiments, the substrate 110 may also be a semiconductor on insulator (semiconductor on insulator) substrate, such as silicon on insulator or silicon germanium on insulator (SGOI). In other embodiments, the substrate 110 can be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al ₂ O ₃ ) substrate (or called a sapphire (Sapphire) substrate), or other similar base. In some embodiments, the substrate 110 may include a ceramic substrate and a pair of barrier layers respectively disposed on upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may include a ceramic material, and the ceramic material may include a metal-inorganic material. For example, the ceramic substrate may include silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be alumina.

The channel layer 112 is located on the substrate 110 . In some embodiments, the material of the channel layer includes a binary III-V compound semiconductor material, such as III-nitride. For example, the material of the channel layer can be gallium nitride. In some embodiments, the channel layer can be doped with n-type dopants or p-type dopants. The channel layer can be formed by epitaxial growth processes, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), combinations thereof, or similar methods. In some embodiments, the breakdown voltage of the high electron mobility transistor mainly depends on the thickness of the GaN channel layer. For example, increasing the thickness of the GaN channel layer by 1 µm can increase the breakdown voltage of the high electron mobility transistor by about 100V. During the epitaxial growth process for forming the GaN layer, it is necessary to use a substrate with high thermal conductivity and high mechanical strength to deposit the GaN material on it, otherwise the substrate may be bent or even cracked. Compared with the silicon substrate, the aluminum nitride substrate has higher thermal conductivity and higher mechanical strength, so a thicker gallium nitride layer can be formed on the aluminum nitride substrate. For example, the thickness of the GaN layer formed on the surface of the silicon substrate may be about 2 µm to about 4 µm, and the thickness of the GaN channel layer formed on the surface of the AlN substrate may be about 5 µm to about 15 µm.

Since the channel layer 112 and the substrate 110 may have lattice differences or different thermal expansion coefficients, the channel layer 112 may generate strain at or near the interface with the substrate 110, and cracks may easily form in the channel layer 112. Or warping and other defects. In some embodiments, the semiconductor structure 200 may include a buffer layer 111 between the substrate 110 and the channel layer 112 , as shown in FIG. 2 . The buffer layer 111 can relieve the strain of the channel layer 112 formed thereon to prevent defects from forming in the channel layer 112 . The material of the buffer layer 111 may include: AlN, GaN, _{AlxGa1 -xN} (where 0>x>1), a combination of the foregoing, or other similar materials, and may be formed by an epitaxial growth process, such as: metal organic Chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations of the foregoing, or similar methods.

Although the buffer layer 111 shown in FIG. 2 is a single-layer structure, the buffer layer 111 may also be a multi-layer structure (not shown). For example, the buffer layer 111 may include a superlattice buffer layer and/or a graded buffer layer, wherein the superlattice buffer layer is disposed on the substrate 110, and the graded buffer layer is disposed on the superlattice buffer layer, which can effectively avoid Dislocations within the substrate 110 enter the channel region, further enhancing the crystalline quality of other films and/or layers above. In addition, the superlattice buffer layer and the graded buffer layer can also be a multilayer structure. For example, the superlattice buffer layer can include multiple sets of alternating layers, and each set of alternating layers includes at least one aluminum nitride (AlN) layer in a staggered arrangement. layer and at least one aluminum gallium nitride (Al _x Ga _(1-x) N) layer, and can be represented by Al _x Ga _(1-x) N according to different aluminum contents, where 0≦x>1; gradient buffer The layer may comprise a plurality of aluminum gallium nitride ( _{AlyGa (1-y)} N) layers, and may be represented by _{AlyGa (1-y)} N according to different aluminum contents, where 0≦y>1.

In some embodiments, a seed layer (not shown) may be formed between the substrate 110 and the buffer layer 111 . The material of the seed layer may include: AlN, Al ₂ O ₃ , AlGaN, SiC, Al, combinations thereof, or similar materials. The seed layer can be a single-layer or multi-layer structure, and can be formed through the aforementioned epitaxial growth process or similar processes. In some embodiments, the material of the buffer layer 111 depends on the material of the seed layer and the gas introduced during the epitaxy process.

The barrier layer 113 is disposed on the channel layer 112 . The material of the barrier layer 113 may include ternary group III-V compound semiconductors, such as group III nitrides. For example, the material of the barrier layer can be AlGaN, AlInN, or a combination thereof. In other embodiments, the barrier layer 113 may also include: GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other appropriate III-V materials, or combinations thereof. In some embodiments, the barrier layer 113 may have dopants, such as n-type dopants or p-type dopants. The barrier layer can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations of the foregoing, or similar methods. According to some embodiments of the present invention, the materials of the channel layer 112 and the barrier layer 113 are different, and the interface thereof is a heterojunction structure, where stress is generated due to lattice mismatch between the channel layer 112 and the barrier layer 113 , resulting in a piezoelectric polarization effect, and the bonding of Group III metals (such as Al, Ga, or In) to nitrogen is highly ionic, resulting in spontaneous polarization. Due to the difference in energy gap between the channel layer 112 and the barrier layer 113 and the aforementioned piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (two-dimensional electron gas, 2DEG) (not shown) is formed in the On the heterointerface between the channel layer 112 and the barrier layer 113 . Some semiconductor devices in the embodiments of the present invention are high electron mobility transistors (HEMTs) using two-dimensional electron gas (2DEG) as conductive carriers.

Referring to FIG. 2 , the doped compound semiconductor layer 116 is disposed on the barrier layer 113 . The doped compound semiconductor layer 116 has a side E ₁ adjacent to the source structure, a side E ₂ adjacent to the drain structure, and an opening OP ₁ . The distance between the side E ₁ and the side E ₂ is D ₁ , the width of the opening OP ₁ is W ₁ and part of the barrier layer 113 is exposed. Doping the compound semiconductor layer 116 can suppress the generation of two-dimensional electron gas (2DEG) under the gate electrode 118 formed thereon to achieve a normally-off state of the semiconductor device. During the manufacturing process, the doped compound semiconductor layer 116 may be affected by the environment (such as temperature or elements in the environment) to cause deactivation (deactivation). In the embodiment of the present invention, the doped compound semiconductor layer 116 having the opening _OP1 Reducing the area of the doped compound semiconductor layer 116 in the semiconductor structure 200, so as to reduce the proportion of the doped compound semiconductor layer 116 in the device design, thereby improving the effect of the doped compound semiconductor layer 116 being affected by environmental factors during the manufacturing process. result in reduced component performance. In some embodiments, the width W ₁ of the opening OP ₁ is 1/3 to 2/3 of the distance D ₁ between the side E ₁ and the side E ₂ . In the case of the functions and characteristics of the doped compound semiconductor layer 116 being affected by environmental factors during the manufacturing process, the degradation of device performance is improved. In addition, since the area of the doped compound semiconductor layer 116 is reduced, the control ability of the gate electrode 118 caused by the influence of environmental factors in the manufacturing process of the doped compound semiconductor layer can be avoided, thereby improving the current driving ability.

According to some embodiments of the present invention, the material of the doped compound semiconductor layer 116 may be p-type doped or n-type doped GaN. The thickness of the doped compound semiconductor layer 116 may be about 50 nm to about 150 nm. The step of forming the doped compound semiconductor layer 116 may include: depositing a doped compound semiconductor on the barrier layer 113 through an epitaxial growth process and forming a patterned mask layer on the doped compound semiconductor, and then performing An etching process is performed to remove the portion of the doped compound semiconductor not covered by the patterned mask layer, thereby forming the doped compound semiconductor layer 116 corresponding to the predetermined position for forming the gate electrode 118 . Afterwards, the patterned mask is removed. The foregoing patterned mask layer can be a hard mask or a photoresist. In some embodiments, the doped compound semiconductor layer can be deposited in-situ in the same deposition chamber as the seed layer, the buffer layer 111 , the channel layer 112 , and the barrier layer 113 . In addition, the doped compound semiconductor layer 116 may have a rectangular cross-section as shown in FIG. 2 , or may have other shapes, such as a trapezoidal cross-section. Furthermore, the upper surface of the doped compound semiconductor layer 116 may not be flat.

In other embodiments, the doped compound semiconductor layer 116 may include other p-type doped III-V semiconductors, such as AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs. In addition, the doped compound semiconductor layer 108 may also include p-type doped II-VI semiconductors, such as CdS, CdTe, or ZnS. In some embodiments, the doped compound semiconductor layer 116 can be doped with elements such as Li, Be, C, Na, Mg, Zn, Ca, Sr, Ba, Ra, Ag, Au, so that the doped compound semiconductor layer 116 is p-type doping.

Continuing to refer to FIG. 2, the dielectric layer 117 is located on the barrier layer 113 and the doped compound semiconductor layer 116, the gate electrode 118 is disposed on the doped compound semiconductor layer 116 and embedded in the dielectric layer 117, and the gate The metal layer 119 is disposed on the dielectric layer 117 and serves as a gate field plate. As mentioned above, the gate electrode 118 is disposed on the doped compound semiconductor layer 116, and the doped compound semiconductor layer 116 can suppress the generation of two-dimensional electron gas (2DEG) under the gate electrode 118 to achieve a normally-off state of the semiconductor device. . The dielectric layer 117 may include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (tetraethoxysilane, TEOS), phosphosilicate glass (PSG) , borophosphosilicate glass (BPSG), low dielectric constant dielectric material, and/or other suitable dielectric materials. Low-k dielectric materials may include (but are not limited to): fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous Fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, the dielectric layer may be formed using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, other suitable methods, or combinations thereof 117.

The material of the gate electrode 118 can be a conductive material, such as: metal, metal nitride or semiconductor material, for example, the metal can be: Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, Similar materials, combinations of the foregoing, or multilayer structures of the foregoing; metal nitrides can be: MoN, WN, TiN, TaN, or similar materials; semiconductor materials can be: polycrystalline silicon or polycrystalline germanium. The aforementioned conductive material can be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (such as sputtering or evaporation), and then the conductive material is patterned , to form the gate electrode 118 . In some embodiments, the gate metal layer 119 can be formed by a similar method. The gate metal layer 119 may include the same or similar material as the gate electrode 118 and may be formed by the same process or by a different process. The material of the gate metal layer 119 may include: NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, metal oxide, metal alloy, other suitable conductive materials, or a combination thereof.

As shown in FIG. 2 , the source structure and the drain structure are disposed on both sides of the barrier layer 113 . The source structure may include a source electrode 114 and a source metal layer 122 disposed on the source electrode 114 , and the drain structure may include a drain electrode 115 and a drain metal layer 123 disposed on the drain electrode 115 . In some embodiments, the method for forming the source electrode 114 and the drain electrode 115 includes: performing a patterning process on the barrier layer to form a pair (or more) of openings in the barrier layer, and then filling the conductive material into the barrier layer. A planarization process (such as chemical mechanical polishing) or an etch back process is performed in the opening to remove excess material outside the opening, thereby forming the source electrode 114 and the drain electrode 115 . In other embodiments, the source electrode 114 and the drain electrode 115 can be formed by performing a similar process after forming the dielectric layer 117 . The aforementioned conductive material and its forming method are similar to the aforementioned conductive material of the gate electrode 118 . In some embodiments, the source metal layer 122 or the drain metal layer 123 can be formed in a subsequent process by a similar method. According to some embodiments of the present invention, the formation method of the aforementioned gate electrode 118 may be similar to the formation method of the source electrode 114 and the drain electrode 115 .

In some embodiments, the source metal layer 122 may be directly located on the source electrode 114 and in direct contact with it, or be electrically connected to the source electrode 114 through a contact. Similarly, the drain metal layer 123 can be directly located on and in contact with the drain electrode 115 , or electrically connected to the drain electrode 115 through a contact. For example, the source electrode 114 of the source structure is buried in the dielectric layer 117, and the source metal layer 122 of the source structure can be disposed on the dielectric layer 117, wherein the source electrode 114 and the source metal layer 122 is electrically connected by a source contact embedded in dielectric layer 117 . The potential of the source metal layer 122 electrically connected to the source electrode 114 is different from the potential of the gate metal layer 119 electrically connected to the gate electrode 118. The direction from the source structure to the drain structure extends and acts as a source field plate, thereby reducing the electric field strength. In other embodiments, the source electrode 114 and the drain electrode 115 may pass through the barrier layer 113 and contact the channel layer 112 . The source metal layer 122 and the drain metal layer 123 may include the same or similar materials as the source electrode 114 and the drain electrode 115 , and may be formed by the same process or by different processes. In some embodiments, the materials of the source metal layer 122 and the drain metal layer 123 may include: NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, metal oxides, metal alloys, other suitable conductive materials, or the aforementioned combination.

In addition, as mentioned above, deactivation may occur in the doped compound semiconductor layer 116 affected by the environment (such as temperature or elements in the environment) during the process. The deactivation may cause the control capability of the gate electrode 118 to deteriorate, thereby affecting the current driving capability. Therefore, in order to reduce the proportion of the doped compound semiconductor layer 116 in the device design, the embodiment of the present invention uses the doped compound semiconductor layer 116 with the opening _OP1 to reduce the proportion of the doped compound semiconductor layer 116 in the semiconductor structure 200. The area can improve the control ability of the gate electrode 118 caused by the influence of environmental factors on the doped compound semiconductor layer 116 during the manufacturing process, thereby improving the current driving ability and electrical uniformity. For example, under the same conditions (eg, the same voltage), the doped compound semiconductor layer 116 with the opening OP ₁ can increase the driving current of the device by more than 25%. According to some embodiments, the width W ₁ of the opening OP ₁ is 1/3 to 2/3 of the distance D ₁ between the side E ₁ and the side E ₂ , without substantially affecting the original functions and characteristics of the compound semiconductor layer 116. In this case, the deterioration of the control ability of the gate electrode 118 due to the influence of environmental factors on the doped compound semiconductor layer 116 during the manufacturing process is improved, thereby improving the current driving ability.

In some embodiments, the semiconductor structure 200 may further include a protection layer and a liner layer (not shown). The protective layer may be disposed on sidewalls and a portion of the upper surface of the doped compound semiconductor layer 116 and a portion of the upper surface of the barrier layer 113 . In some embodiments, the passivation layer can repair the lattice defects caused by the aforementioned etching process on the sidewall of the doped compound semiconductor layer 116 , thereby reducing the gate leakage current of the formed device. In addition, the protective layer formed on a part of the upper surface of the barrier layer 113 can be used to prevent the oxidation of the surface of the barrier layer 113 and improve the performance of the formed device. Depending on the requirement of the process or the design of the device, the thickness of the passivation layer may be about 0.5 nm to about 500 nm. The material of the protective layer may include insulating or dielectric materials, such as SiO ₂ , SiN, SiON, Al ₂ O ₃ , AlN, MgO, Mg ₃ N ₂ , ZnO, TiO ₂ , combinations thereof, or similar materials.

In some embodiments, the protection layer is made of nitride, such as silicon nitride or aluminum nitride, which can preferably repair the lattice defects of the sidewall of the doped compound semiconductor layer 116 . In some embodiments, the foregoing material layer may be formed on the substrate 110 by chemical vapor deposition, such as plasma-assisted chemical vapor deposition, atomic layer deposition, physical vapor deposition (such as sputtering), or the like, and pattern it to form a protective layer. In other embodiments, the patterning process can completely remove the protective layer on the upper surface of the doped compound semiconductor layer 116 , so that the protective layer is located on the sidewalls of the doped compound semiconductor layer 116 and the upper surface of the barrier layer 113 .

In some embodiments, the liner may be disposed on the bottom and part of the sidewalls of the source electrode 114 and the drain electrode 115 , and part of the upper surface of the barrier layer 113 . In some embodiments, the liner helps to generate more two-dimensional electron gas (2DEG) on the heterointerface of the source electrode 114 and the drain electrode 115, so as to reduce the contact between the source electrode 114 and the drain electrode 115 and the channel layer. The contact resistance (R _contact ) between 112, thereby reducing the on-resistance of the semiconductor structure. In addition, the liner formed on part of the upper surface of the barrier layer 113 can be used to prevent the surface oxidation of the barrier layer 113 and improve the performance of the formed device.

In some embodiments, the material of the lining layer may include a hexagonal crystal binary (binary) compound semiconductor, such as: AlN, ZnO, InN, a combination of the foregoing, or similar materials, and may be deposited by atomic layer deposition or epitaxial growth process (such as metal organic chemical vapor deposition) to deposit. In one embodiment, the liner layer is formed by metal-organic chemical vapor deposition. Since metal-organic chemical vapor deposition is a selective area growth (SAG) process, the liner layer is formed on the upper surface of the barrier layer 113 On the area covered by the protective layer, so as to be in contact with the protective layer without forming on the protective layer. In another embodiment, the liner layer formed by atomic layer deposition is not only formed on the upper surface of the barrier layer 113 not covered by the passivation layer, but also extends to the passivation layer. In addition, in some other embodiments, the material of the lining layer may also include graphene having a hexagonal crystal system, and the lining layer may be formed by chemical vapor deposition or atomic layer deposition. In some embodiments, the material of the liner layer and the protection layer may be the same, for example, both are AlN. In some other embodiments, the material of the lining layer is different from that of the protective layer, for example, the lining layer is AlN, and the protective layer is aluminum silicide SiN.

FIG. 3 is a partial projected top view illustrating a semiconductor structure according to some embodiments of the present invention. Fig. 4 is a schematic cross-sectional view of AA' of Fig. 3 according to some embodiments of the present invention. The semiconductor structure 400 is similar to the semiconductor structure 200. The difference is that the doped compound semiconductor layer 316 of the semiconductor structure 400 has two openings. For the sake of simplicity, the same components in FIG. 4 and FIG. Its description is omitted. As shown in FIG. 4 , the doped compound semiconductor layer 316 has a side E ₃ adjacent to the source structure, a side E ₄ adjacent to the drain structure, and openings OP _{3 a} and OP _{3 b} . The distance between the side E ₃ and the side E ₄ is D ₃ , the width of the opening OP _3a is W _3a and the width of the opening OP _3b is W _3b , and the aforementioned two openings expose part of the barrier layer 113 . The semiconductor structure 400 includes a doped compound semiconductor layer 316 having openings OP _3a and OP _3b . As mentioned above, since the area of the doped compound semiconductor layer 316 in the semiconductor structure 400 is reduced, the area of the doped compound semiconductor layer 316 can be improved. Influenced by environmental factors during the manufacturing process, the control capability of the gate electrode 118 is deteriorated, thereby improving the current driving capability.

According to some embodiments, the sum of the width W _3a of the opening OP _3a and the width W _3b of the opening OP _3b is 1/3 to 2/3 of the distance D ₃ between the side E ₃ and the side E ₄ , which may be without substantially affecting In the case of original functions and characteristics of the compound semiconductor layer 316 , the poor control ability of the gate electrode 118 caused by the influence of environmental factors during the manufacturing process of the doped compound semiconductor layer 316 is improved, thereby improving the current driving ability. It should be noted that the number of openings shown in FIG. 4 is only an example, and the number of openings in the compound semiconductor layer of the embodiment of the present invention may be more than two. In some embodiments where the compound semiconductor layer has more than two openings, the width of the opening is 1/3 to 2/3 of the distance between the side of the doped compound semiconductor layer adjacent to the source structure and the side of the drain structure. As mentioned above, the control ability of the gate electrode can be improved without substantially affecting the original functions and characteristics of the compound semiconductor layer, thereby improving the current driving ability. In some embodiments, the semiconductor structure 400 may also include, for example, a protective layer and/or a liner layer, so as to reduce the gate leakage current of the formed element and/or reduce the on-resistance of the semiconductor structure 400, and prevent the surface of the barrier layer 113 from Oxidation improves the performance of the formed components. In addition, as shown in FIG. 3 of the top view, the doped compound semiconductor layer 316 has a rectangular opening OP _3a and an elliptical opening OP _3b . Specifically, from the source electrode 114 to the drain electrode 115 (or from the source structure to In the AA' direction of the drain structure), the doped compound semiconductor layer 316 has two openings OP _3a and OP _3b , and the openings OP _3a and OP _3b have a maximum width sum (W _3a +W _3b ) in the AA' direction . In some embodiments, in order to maintain the original functions and characteristics of the doped compound semiconductor layer 316, the sum of the maximum widths of the openings OP _3a and OP _3b in the A-A' direction (W _3a +W _3b ) is the doped compound semiconductor layer 316 in The maximum width D ₃ in the A-A' direction is 1/3 to 2/3, and the minimum distance between the openings OP _3a and OP _3b in the A-A' direction is the distance between the openings OP _3a and OP _3b in A-A' The average value of the width in the direction, that is, (W _3a +W _3b )/2. The doped compound semiconductor layer 316 with openings, as mentioned above, can improve the controllability of the gate electrode and enhance the current driving capability.

5-11 are partial projected top views of semiconductor structures according to some variant embodiments of the present invention. Referring to Fig. 5, which includes the source electrode 114, the drain electrode 115, and the doped compound semiconductor layer 516, as shown in the top view, the doped compound semiconductor layer 516 has a rectangular opening _OP5a , an oval opening _OP5b , and a triangular opening OP5b. Opening OP _5c , in the AA' direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), the doped compound semiconductor layer 516 has three openings, and the openings OP _5a , OP _5b and OP _5c have a maximum width sum (W _5a + W _5b + W _5c ) in the A-A' direction. In some embodiments, in order to maintain the original functions and characteristics of the doped compound semiconductor layer 516, the maximum width sum (W _5a + W _5b + W _5c ) of the openings OP _5a , OP _5b , and OP _5c in the A-A' direction is doped The maximum width _D5 of the hybrid compound semiconductor layer 516 in the AA' direction is 1/3 to 2/3, and the adjacent minimum distance between the openings _OP5a , _OP5b , and _OP5c in the AA' direction is 1/3 to 2/3. The average value of the widths of OP _5a , OP _5b , and OP _5c in the A-A' direction is (W _5a +W _5b +W _5c )/3. The doped compound semiconductor layer 516 with openings can improve the control capability of the gate electrode and enhance the current driving capability.

Referring to Fig. 6, which includes source electrode 114, drain electrode 115, and doped compound semiconductor layer 616, as shown in the top view, doped compound semiconductor layer 616 has rectangular openings OP _6a and OP _6b , from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure) in the AA' direction, at least a part of the doped compound semiconductor layer 616 is discontinuous, and the opening OP _6a is parallel to the AA' direction The opening OP 6b has a width W _6a in one direction, and the opening OP _6b has a width W _6b in the AA' direction, wherein W _6b is larger than W _6a . In some embodiments, in order to maintain the original functions and characteristics of the doped compound semiconductor layer 616, the larger width W6b of the opening OP _6b is 1/ of the maximum width _D6 of the doped compound semiconductor layer 616 in the AA' direction. 3 to 2/3, and the minimum distance S ₁ between the opening OP _6a and the opening OP _6b in the BB' direction perpendicular to the AA' direction is the distance between the doped compound semiconductor layer 616 in the AA' direction 1/2 of the maximum width D ₆ . The doped compound semiconductor layer 616 with openings, as mentioned above, can improve the controllability of the gate electrode and enhance the current driving capability.

Referring to Fig. 7, which includes source electrode 114, drain electrode 115, and doped compound semiconductor layer 716, as shown in the top view, doped compound semiconductor layer 716 has a rectangular opening OP _7a , a trapezoidal opening OP _7b and a circular opening OP _7c , in the AA' direction from the source electrode 114 to the drain electrode 115 (or from the source structure to the drain structure), at least a part of the doped compound semiconductor layer 716 is discontinuous, and the rectangular opening The OP _7a has a width W _7a in one direction parallel to the A-A' direction, the larger base of the trapezoidal opening OP _7b has a width W _7b in the A-A' direction, and the circular opening OP _7c has a width W 7b in the direction parallel to the A-A' direction. The other direction has a width W _7c , wherein W _7b is larger than W _7a and W _7c . In some embodiments, in order to maintain the original functions and characteristics of the doped compound semiconductor layer 716, the width W _7b of the larger bottom side of the opening OP _7b is the maximum width D ₇ of the doped compound semiconductor layer 716 in the AA' direction 1/3 to 2/3 of , and the minimum value of the spacing S ₂ between the opening OP _7a and the opening OP _7b in the BB' direction perpendicular to the AA' direction, and the opening OP _7b and the opening OP _7c in the vertical The minimum value of the spacing S ₃ in the BB' direction in the AA' direction is 1/2 of the maximum width D ₇ of the doped compound semiconductor layer 716 in the AA' direction. The doped compound semiconductor layer 716 with openings, as mentioned above, can improve the controllability of the gate electrode and enhance the current driving capability.

The opening shape of the above-mentioned doped compound semiconductor layer is just an example and not intended to limit the embodiment of the present invention. The shape of the opening may include: rectangle, rhombus, trapezoid, circle, ellipse, triangle, or a combination thereof. In addition, the embodiments of the present invention are also applicable to openings with irregular shapes.

In addition to the opening, the doped compound semiconductor layer may also have a gap on at least one of its two sides _E5 , _E6 parallel to the AA' direction, as shown in Figure 8, which contains the source electrode 114, the drain electrode 115, and the doped compound semiconductor layer 816, the doped compound semiconductor layer 816 has a rectangular gap N ₈ , between the source electrode 114 and the drain electrode 115 (or from the source structure to the drain structure) In the AA' direction, at least a part of the doped compound semiconductor layer 816 is discontinuous, the orientation of the notch N ₈ is perpendicular to the AA' direction, and the maximum width of the notch N ₈ in the AA' direction is W ₈ . In some embodiments, in order to maintain the original functions and characteristics of the doped compound semiconductor layer 816, the maximum width _W8 of the gap _N8 in the AA' direction is the maximum width of the doped compound semiconductor layer 816 in the AA' direction 1/3 to 2/3 of D ₈ . The doped compound semiconductor layer 816 with openings can improve the controllability of the gate electrode because the doped compound semiconductor layer is affected by environmental factors during the manufacturing process due to the reduction of the area of the doped compound semiconductor layer in the semiconductor structure. become worse, thereby improving the current driving capability.

The doped compound semiconductor layer may also have more than one notch on at least one of its two sides E ₇ , E ₈ parallel to the AA' direction, so as to form an M-type or a comb shape (comb shape), as shown in the first 9, it includes source electrode 114, drain electrode 115, and doped compound semiconductor layer 916. The doped compound semiconductor layer 916 has local elliptical notches _N9a and triangular notches _N9b . 114 to the drain electrode 115 (or from the source structure to the drain structure) in the AA' direction, at least a part of the doped compound semiconductor layer 916 is discontinuous, and the direction of the two gaps is perpendicular to A- The partially elliptical notch N _9a and the triangular notch N _9b in the A' direction have a maximum width sum (W _9a +W _9b ) in the A-A' direction. In some embodiments, in order to maintain the original functions and characteristics of the doped compound semiconductor layer 916, the maximum width (W _9a + W _9b ) of the partial elliptical notch N _9a and the triangular notch N _9b in the A-A' direction is the doped The maximum width _D9 of the hybrid compound semiconductor layer 916 in the AA' direction is 1/3 to 2/3, and the adjacent minimum distance between the elliptical notch _N9a and the triangular notch _N9b in the AA' direction is an ellipse The average value of the width of the notch N _9a and the notch N _9b in the A-A' direction is (W _9a +W _9b )/2. The doped compound semiconductor layer 916 with gaps, as mentioned above, can improve the controllability of the gate electrode and enhance the current driving capability.

Referring to FIG. 10, it includes a source electrode 114, a drain electrode 115, and a doped compound semiconductor layer 1016. As shown in the top view, the doped compound semiconductor layer 1016 is U-shaped, and is formed from the source electrode 114 to the drain electrode. In the A-A' direction of the electrode 115 (or from the source structure to the drain structure), at least a part of the doped compound semiconductor layer 1016 is discontinuous, and the direction of the gap in the doped compound semiconductor layer 1016 is perpendicular to the A-A' direction. A' direction and the notch has a maximum width W ₁₀ in the A-A' direction. In some embodiments, in order to maintain the original functions and characteristics of the doped compound semiconductor layer 1016, the maximum width W ₁₀ of the gap in the AA' direction is the maximum width D of the doped compound semiconductor layer 1016 in the AA' direction 1/3 to 2/3 of ₁₀ . The doped compound semiconductor layer 1016 with gaps, as mentioned above, can improve the controllability of the gate electrode and enhance the current driving capability.

The aforementioned shape of the notch in the doped compound semiconductor layer is only an example and not intended to limit the embodiment of the present invention. The shape of the notch may include: rectangle, trapezoid, partial circle, partial ellipse, triangle, or a combination of the foregoing . The embodiments of the present invention also do not limit the shape of the doped compound semiconductor layer with notches, which may include: M-shape, U-shape, comb-shape, or a combination thereof.

Referring to FIG. 11, it includes a source electrode 114, a drain electrode 115, and a doped compound semiconductor layer 1116 composed of a plurality of separated doped compound semiconductor islands. As shown in the top view, these doped compound semiconductor islands Including a rectangular doped compound semiconductor island 1116a, an elliptical doped compound semiconductor island 1116b, and an elliptical doped compound semiconductor island 1116c, between the source electrode 114 and the drain electrode 115 (or from the source structure to the drain structure) In the AA' direction, the doped compound semiconductor layer 1116 is discontinuous, and the doped compound semiconductor islands 1116a, 1116b, and 1116c have a maximum width sum (W _11a +W _11b +W _11c ) in the AA' direction. In some embodiments, in order to maintain the original functions and characteristics of the doped compound semiconductor layer 1116, the maximum width sum (W _11a + W _11b + W _11c ) of the doped compound semiconductor islands 1116a, 1116b, and 1116c in the A-A' direction is: Adjacent doped compound semiconductor islands are separated by 1/2 to 2 times the distance sum (S ₄ +S ₅ ) in the AA' direction. The doped compound semiconductor layer 1116 composed of a plurality of isolated doped compound semiconductor islands can also reduce the area of the doped compound semiconductor layer in the semiconductor structure, thereby improving the current driving capability. The above-mentioned shapes of the doped compound semiconductor islands are only examples and are not intended to limit the embodiments of the present invention. The shapes of the doped compound semiconductor islands may include: rectangle, trapezoid, circle, ellipse, triangle, or a combination of the foregoing .

Fig. 12 is a comparison of the experimental data between the comparative example and the embodiment in Fig. 6. The Y-axis is the electric field strength between the channel layer and the barrier layer near the surface of the semiconductor structure, and the X-axis is the electric field strength in the horizontal direction of the semiconductor structure. For the corresponding position, the origin of the X-axis is the position close to the source in the semiconductor structure, and as the coordinate of the X-axis increases, it moves away from the source and approaches the drain. In the comparative example, the doped compound semiconductor layer does not have any openings or gaps. The embodiment in FIG. 6 effectively reduces the electric field close to the surface by reducing the area of the doped compound semiconductor layer.

The doped compound semiconductor layer with openings or gaps, or the doped compound semiconductor layer with a discontinuous structure provided by the embodiments of the present invention can improve the doped compound semiconductor layer because of the reduced area of the doped compound semiconductor layer in the semiconductor structure. The hybrid compound semiconductor layer is affected by environmental factors during the manufacturing process, which leads to poor control ability of the gate electrode, and improves current driving ability and electrical uniformity, further improving device performance. In addition, reducing the area of the doped compound semiconductor layer in the semiconductor structure can further reduce the electric field near the surface to achieve the effect of reducing the surface electric field (REduced SURface Field, RESURF).

The features of several embodiments are summarized above, so that those skilled in the art of the present invention can better understand various aspects of the present invention. Those who have ordinary knowledge in the technical field of the present invention should understand that they can easily use the present invention as a basis to design or modify other processes and structures to achieve the same purpose and/or advantages as the embodiments described herein . Those with ordinary knowledge in the technical field of the present invention should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and substitutions can be made here without departing from the present invention. spirit and scope.

200,400: semiconductor structure 110: substrate 112: channel layer 111: buffer layer 113: barrier layer 114: source electrode 115: drain electrode 116,316,516: doped compound semiconductor layer 117: dielectric layer 118: gate electrode 119: gate Pole metal layer 122: source metal layer 123: drain metal layer 616, 716, 816, 916, 1016, 1116: doped compound semiconductor layers 1116a, 1116b, 1116c: doped compound semiconductor islands E ₁ , E ₂ , E ₃ , E ₄ , E ₅ , E ₆ , E ₇ , E ₈ : side OP ₁ , OP _3a , OP _3b , OP _5a , _{OP 5b, OP 5c: opening OP 6a, OP 6b, OP 7a, OP 7b , OP 7c : opening N 8} , N _9a , N _9b : Gap D ₁ , D ₃ , S 1 , S ₂ , S _{3 ,} S ₄ , S ₅ : Spacing D ₅ , D ₆ , D 7 , D ₈ , D _{9 ,} D ₁₀ : Width W ₁ ,W _3a ,W _3b ,W _5a ,W _5b ,W _5c ,W _6a ,W _6b : Width W _7a ,W _7b ,W _7c ,W ₈ ,W _9a ,W _9b ,W ₁₀ ,W _11a ,W _11b ,W _11c : Width

Embodiments of the present invention are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the invention. FIG. 1 is a partial projected top view illustrating a semiconductor structure according to some embodiments of the present invention. FIG. 2 is a schematic cross-sectional view showing A-A' of the semiconductor structure in FIG. 1 according to some embodiments of the present invention. FIG. 3 is a partial projected top view illustrating a semiconductor structure according to some embodiments of the present invention. FIG. 4 is a schematic cross-sectional view showing A-A' of the semiconductor structure in FIG. 3 according to some embodiments of the present invention. 5-11 are partial projected top views illustrating semiconductor structures according to other embodiments of the present invention. FIG. 12 is a diagram illustrating electric field strength near a surface of a semiconductor structure according to some embodiments of the present invention.

200: Semiconductor Structures

110: base

111: buffer layer

112: Channel layer

113: barrier layer

114: source electrode

115: drain electrode

116: doped compound semiconductor layer

117: dielectric layer

118: gate electrode

119: gate metal layer

122: source metal layer

123: drain metal layer

D ₁ : Spacing

OP ₁ : Opening

W ₁ : width

E ₁ , E ₂ : side

Claims (14)

A semiconductor structure comprising: a base; a channel layer located on the substrate; a barrier layer located on the channel layer; A source structure and a drain structure are located on both sides of the barrier layer; a doped compound semiconductor layer located on the barrier layer, the doped compound semiconductor The layer has a first side adjacent to the source structure, a second side adjacent to the drain structure, and at least one opening exposing at least a portion of the barrier layer; a dielectric layer on the doped compound semiconductor layer and the barrier layer; and A gate structure is located on the doped compound semiconductor layer. The semiconductor structure according to claim 1, wherein the width of the at least one opening is 1/3 to 2/3 of the distance between the first side and the second side of the doped compound semiconductor layer. The semiconductor structure according to claim 1, wherein the at least one opening is plural, and the sum of the widths of the openings is 1/3 to 2 of the distance between the first side and the second side of the doped compound semiconductor layer /3. The semiconductor structure according to claim 1, further comprising a buffer layer located between the substrate and the channel layer. A semiconductor structure comprising: a base; a buffer layer located on the substrate; a channel layer located on the buffer layer; a barrier layer located on the channel layer; A source structure and a drain structure are located on both sides of the barrier layer; a doped compound semiconductor layer on the barrier layer, wherein at least a portion of the doped compound semiconductor layer is discontinuous in a first direction from the source structure to the drain structure; a dielectric layer on the doped compound semiconductor layer and the barrier layer; and A gate structure is located on the doped compound semiconductor layer. The semiconductor structure according to claim 5, wherein the doped compound semiconductor layer has at least one opening. The semiconductor structure according to claim 6, wherein the at least one opening has a maximum opening width in the first direction, and the maximum opening width is 1/3 to the maximum width of the doped compound semiconductor layer along the first direction 2/3. The semiconductor structure according to claim 6, wherein the at least one opening is plural, and the openings have a maximum width sum in the first direction, and the maximum width sum is the maximum of the doped compound semiconductor layer along the first direction 1/3 to 2/3 of the width. The semiconductor structure according to claim 6, wherein the at least one opening is plural, and the minimum distance between adjacent adjacent openings in a second direction perpendicular to the first direction is that the doped compound semiconductor layer is along the first direction 1/2 of the maximum width of the opening, one of the openings has a maximum opening width in the first direction, and the maximum opening width is 1 of the maximum width of the doped compound semiconductor layer along the first direction /3 to 2/3. The semiconductor structure according to claim 5, wherein the doped compound semiconductor layer has two sides parallel to the first direction, and at least one gap is formed on at least one of the two sides. The semiconductor structure according to claim 10, wherein the at least one gap has a maximum gap width in the first direction, and the maximum gap width is 1/3 to the maximum width of the doped compound semiconductor layer along the first direction 2/3. The semiconductor structure according to claim 10, wherein the at least one gap is plural, and the gaps have a maximum width sum in the first direction, and the maximum width sum is the maximum of the doped compound semiconductor layer along the first direction 1/3 to 2/3 of the width. The semiconductor structure according to claim 7, wherein the doped compound semiconductor layer is composed of a plurality of separated doped compound semiconductor islands. The semiconductor structure as claimed in claim 13, wherein the doped compound semiconductors have a maximum width sum in the first direction, and the maximum width sum is the sum of the distances between adjacent doped compound semiconductor islands in the first direction 1/2 to 2 times of that.

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