TWI755091B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method of forming the same are provided. The method includes providing a substrate on which a buffer layer, a channel layer, and a barrier layer are sequentially formed; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a dielectric layer on the second etch stop layer; forming an etch protection layer on the dielectric layer; performing a first etch process etching through the etch protection layer and partially through the dielectric layer to form a recess in the dielectric layer; performing a second etch process to etch the dielectric layer under the recess to form an opening, wherein the etch protection layer protects the underlying dielectric layer from etching during the second etch process; performing a removal process to remove a remaining portion of the etch protection layer on the dielectric layer.

Description

Semiconductor device and method of forming the same

Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having a doped compound semiconductor and a method for forming the same.

GaN-based semiconductor materials have many excellent material properties, such as high thermal resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistor (HEMT) with a heterointerface structure. ).

High electron mobility transistors may be affected by processes (eg, etching processes) during processing, resulting in poor electrical performance or uniformity. While existing high electron mobility transistors have generally been satisfactory, they are not satisfactory in all respects.

An embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate on which a buffer layer, a channel layer, and a barrier layer are formed in sequence; forming a doped compound semiconductor layer on part of the barrier layer; forming a first An etching stop layer is formed on the doped compound semiconductor layer; a second etching stop layer is formed on the first etching stop layer; a dielectric layer is formed on the second etching stop layer and the dielectric layer covers part of the doped compound semiconductor layer and the doping The barrier layer exposed by the compound semiconductor layer; forming an etching protection layer on the dielectric layer; performing a first etching process, etching through the etching protection layer and partially through the dielectric layer to form a notch in the dielectric layer; performing a second etching process, etching the dielectric layer under the notch to form an opening, the opening exposes a portion of the second etch stop layer, during the second etching process, the etching protection layer protects the underlying dielectric layer from etching; performing removal In the process, the remaining etch protection layer on the dielectric layer is removed; and a gate metal layer is formed to fill the opening.

An embodiment of the present invention provides a semiconductor device, comprising: a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier layer on the channel layer; a doped compound semiconductor layer on part of the barrier layer The first etching stop layer is located on the doped compound semiconductor layer; the second etching stop layer is located on the first etching stop layer; the dielectric layer is located on the second etching stop layer, wherein the dielectric layer covers part of the doped compound a barrier layer exposed by the semiconductor layer and the doped compound semiconductor layer; and a gate metal layer on a portion of the second etch stop layer.

The following disclosure provides numerous embodiments, or examples, for implementing various elements of the provided subject matter. Specific examples of elements and their configurations are described below to simplify the description of embodiments of the invention. Of course, these are only examples, and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements , so that they are not in direct contact with the examples. Additionally, embodiments of the invention may have repeated reference numerals in various instances. This repetition is for the purpose of brevity and clarity and is not intended to represent a relationship between the different embodiments and/or configurations discussed.

In addition, in some embodiments of the present invention, terms related to joining and connecting, such as "connected", "interconnected", etc., unless otherwise defined, may mean that the two structures are in direct contact, or may also mean that the two structures are not in contact with each other. Direct contact, where there are other structures placed between the two structures. And the terms of joining and connecting can also include the case where both structures are movable, or both structures are fixed.

Furthermore, spatially relative terms such as "below", "below", "lower", "above", "higher" and the like may be used for ease of description The relationship between one element(s) or feature(s) in the drawings and another element(s) or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is turned in a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

The terms "about", "approximately" and "approximately" as used herein generally mean within ±20%, preferably within ±10%, and more preferably within ±5% of a given value, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. For example, the term "about 5 nm" can encompass a size range from 4.5 nm to 5.5 nm. The numerical value given in the text is an approximate numerical value, that is, the given numerical value may still imply “about”, “approximately” and “approximately” without specifying “about”, “approximately” or “approximately”. ' meaning.

Some embodiments of the invention are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages described may be replaced or omitted in different embodiments. Additional components may be added to the semiconductor device of the embodiments of the present invention. Some of the components described may be replaced or omitted in different embodiments. Although some of the embodiments discussed are performed in a particular order of steps, the steps may be performed in another logical order.

Embodiments of the present invention provide a method for forming a semiconductor device, in which an etching protection layer is formed on a dielectric layer, so as to reduce damage to the device caused by the etching process, and further prevent short circuit of the device. In addition, the semiconductor device provided by the embodiment of the present invention has an etch stop layer. In addition to the effect of etch stop and protection of other components, the configuration of the etch stop layer can be adjusted according to different design requirements.

1-8 are schematic cross-sectional views illustrating a process of a semiconductor device according to some embodiments of the present invention. Referring to FIG. 1 , a substrate 100 is provided, and a buffer layer 102 , a channel layer 104 , and a barrier layer 106 are sequentially formed on the substrate 100 . The substrate 100 may include: elemental semiconductors including silicon or germanium; compound semiconductors including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and/or indium antimonide (InSb); alloy semiconductors, including silicon-germanium alloys, phosphorus-gallium-arsenide alloys, arsenic-aluminum-indium alloys, arsenic-aluminum-gallium alloys, arsenic-indium-gallium alloys, phosphorus-indium-gallium alloys and/or phosphorus-indium-arsenide-gallium alloys, or combinations of the foregoing materials .

In some embodiments, the substrate 100 may be a semiconductor on insulator substrate, such as silicon on insulator or silicon germanium on insulator (SGOI). In other embodiments, the substrate 100 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al ₂ O ₃ ) substrate (or referred to as a sapphire substrate), a glass substrate , or other similar substrates. In some embodiments, the substrate 100 may include a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may include a ceramic material, and the ceramic material includes a metal inorganic material. For example, the ceramic substrate may comprise: silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be alumina.

The lattice or thermal expansion coefficient of the substrate 100 may be different from that of the upper component (eg, the channel layer 104 ), so strain may be generated at or near the interface between the substrate 100 and the upper component, and defects such as cracks or warpage may be easily formed. As shown in FIG. 1, a buffer layer 102 may be formed on the substrate 100 to relieve the strain of components formed above the buffer layer 102 (eg, the channel layer 104) and prevent defects from forming in the above components. The material of the buffer layer 102 can include: AlN, GaN, AlxGa1 _- xN (wherein 0<x<1), a combination of the foregoing, or other similar materials, and can be formed by an epitaxial growth process, such as metal organic chemical gas Phase deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations of the foregoing, or similar methods. In some embodiments, the buffer layer 102 may be a multi-layer structure (not shown). For example, the buffer layer 102 may include a superlattice buffer layer and/or a graded buffer layer, wherein the superlattice buffer layer is disposed on the substrate 100 and the graded buffer layer is disposed on the superlattice buffer layer, which can effectively avoid Dislocations within the substrate 100 enter the upper components, further improving the crystalline quality of other films and/or layers above.

In some embodiments, a seed layer (not shown) may be optionally formed between the substrate 100 and the buffer layer 102 . In such embodiments, the seed layer can alleviate the lattice difference between the substrate 100 and the films and/or layers grown thereover to improve crystal quality. The material of the seed layer may include: AlN, Al ₂ O ₃ , AlGaN, SiC, Al, a combination of the foregoing, or the like. The single-layer or multi-layer structure of the seed layer can be formed by a suitable process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, other processes, or a combination of the foregoing. In some embodiments, the material of the buffer layer 102 depends on the material of the seed layer and the gas introduced in the epitaxial process.

The channel layer 104 is formed on the buffer layer 102 . In some embodiments, the material of the channel layer 104 includes a binary III-V compound semiconductor material, such as a III-nitride. For example, the material of the channel layer 104 may be gallium nitride. In some embodiments, the channel layer 104 may be doped with n-type dopants or p-type dopants. The channel layer 104 may be formed by an epitaxial growth process such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), combinations of the foregoing, or the like. In some embodiments, the breakdown voltage of the high electron mobility transistor mainly depends on the thickness of the GaN channel layer. For example, increasing the thickness of the GaN channel layer by 1µm can increase the breakdown voltage of the high electron mobility transistor by about 100V. During the epitaxial growth process for forming the gallium nitride layer, in order to deposit the gallium nitride material on the substrate, a substrate with high thermal conductivity and high mechanical strength needs to be used, otherwise the substrate may be bent or even cracked. Compared with the silicon substrate, the aluminum nitride substrate has higher thermal conductivity and mechanical strength, so a thicker gallium nitride layer can be formed on the aluminum nitride substrate.

The barrier layer 106 is formed on the channel layer 104 . The material of the barrier layer 106 may include a ternary group III-V compound semiconductor, such as a group III nitride. For example, the material of the barrier layer 106 may be AlGaN, AlInN, or a combination thereof. In other embodiments, the barrier layer 106 may also include: GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V materials, or a combination of the foregoing. In some embodiments, the barrier layer 106 may be doped, eg, with an n-type dopant or a p-type dopant. The barrier layer 106 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations of the foregoing, or the like. According to some embodiments of the present invention, the material of the channel layer 104 and the barrier layer 106 are different, and the interface of the channel layer 104 and the barrier layer 106 is a heterojunction structure. Since the lattice of the channel layer 104 and the barrier layer 106 do not match, stress may be generated This results in piezoelectric polarization effect, and the bonding between group III metals (eg, Al, Ga, or In) and nitrogen is highly ionic, resulting in spontaneous polarization. Due to the difference in energy gap between the channel layer 104 and the barrier layer 106 and the aforementioned piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (2DEG) (not shown) is formed in the On the hetero interface between the channel layer 104 and the barrier layer 106 . Some semiconductor devices of embodiments of the present invention are high electron mobility transistors (HEMTs) utilizing two-dimensional electron gas (2DEG) as conductive carriers.

The doped compound semiconductor layer 108 is formed on the barrier layer 106 . According to some embodiments of the present invention, the material of the doped compound semiconductor layer 108 includes a doped compound semiconductor material, such as GaN doped with a p-type dopant or an n-type dopant. The step of forming the doped compound semiconductor layer 108 may include: depositing a doped compound semiconductor material layer on the barrier layer 106 through an epitaxial growth process, forming a patterned mask layer on the doped compound semiconductor material layer, An etching process is performed on the semiconductor material layer to remove the portion of the doped compound semiconductor material layer not covered by the patterned mask layer, and to remove the patterned mask. The aforementioned patterned mask layer can be a hard mask or a photoresist. In some embodiments, the doped compound semiconductor layer may be deposited in-situ in the same deposition chamber as the seed layer (optional), buffer layer 102, channel layer 104, and barrier layer 106 . The doped compound semiconductor layer 108 may have a rectangular cross-section as shown in FIG. 1 . In other embodiments, the doped compound semiconductor layer 108 may have a cross-section of other shapes, such as a trapezoidal cross-section.

Referring to FIG. 1 , a first etch stop layer 111 is formed on the doped compound semiconductor layer 108 . The material of the first etch stop layer 111 may include nitrides, such as silicon nitride, silicon oxynitride, silicon carbonitride, oxycarbonitride, gallium nitride, aluminum nitride, metal nitride, metal silicide nitride, or a combination of the foregoing. The aforementioned metal nitrides, for example, may include: titanium nitride, molybdenum nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, tantalum silicon nitride, aluminum titanium nitride or other suitable materials, or the aforementioned combination. The step of forming the first etch stop layer 111 may include depositing and patterning a layer of etch stop material. For example, the deposition process may include: chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (eg, sputtering or evaporation), other suitable processes, or a combination of the foregoing . In some embodiments, during subsequent processes, the first etch stop layer 111 can protect the underlying doped compound semiconductor layer 108 to reduce or prevent the doped compound semiconductor layer 108 from being subjected to an etchant (eg, plasma) used in the etching process. Or poor electrical uniformity caused by the influence of gas in the environment. The thickness of the first etch stop layer 111 may be about 100 Å to 1000 Å, eg, 300 Å. The second etch stop layer 112 is formed on the first etch stop layer 111 , as shown in FIG. 1 . The second etch stop layer 112 can serve as an etch stop layer and protect the first etch stop layer 111 in the subsequent etching process, so as to prevent the etchant from damaging the first etch stop layer 111 and affecting the threshold voltage of the device. The material of the second etch stop layer 112 is different from that of the first etch stop layer 111 . For example, the material of the second etch stop layer 112 may include: doped or undoped silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, oxycarbonitride Silicon, metal silicide, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials ( The dielectric constant is less than 4), other suitable materials, or a combination of the foregoing.

A deposition process may be used to deposit and pattern a layer of etch stop material to form the second etch stop layer 112, which may be about 2 nm to about 50 nm thick, eg, about 10 to 20 nm thick. Deposition processes may include: chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition ( RPCVD), plasma assisted chemical vapor deposition (PECVD), electroplating, other suitable processes, or a combination of the foregoing. In some embodiments, the second etch stop layer 112 and the first etch stop layer 111 can protect the doped compound semiconductor layer 108 to reduce or prevent the doped compound semiconductor layer 108 from being affected by the etching process and cause poor electrical performance.

In a particular embodiment, the first etch stop layer 111 includes titanium nitride and the second etch stop layer 112 includes doped or undoped silicon. The first etch stop layer 111 including titanium nitride can form a Schottky barrier with the doped compound semiconductor layer 108 to increase the threshold voltage. In this embodiment, in addition to protecting the doped compound semiconductor layer 108 from subsequent processes, the second etch stop layer 112 can be doped or undoped polysilicon according to the application and design requirements of the product. The widths of the first etch stop layer 111 and the second etch stop layer 112 are substantially the same as the width of the doped compound semiconductor layer 108 . In one embodiment, the widths of the first etch stop layer 111 and the second etch stop layer 112 and the width of the doped compound semiconductor layer 108 may be different.

As shown in FIG. 1 , the dielectric layer 110 is formed on the second etch stop layer 112 , and the dielectric layer 110 covers part of the doped compound semiconductor layer 108 and the barrier layer 106 exposed by the doped compound semiconductor layer 108 . The dielectric layer 110 may include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), Borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials. The aforementioned low-k dielectric materials may include (but are not limited to): fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous Fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The dielectric layer 110 may be formed using a deposition process, such as spin coating, chemical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, other suitable processes, or a combination of the foregoing.

Referring to FIG. 2 , an etching protection layer 114 is formed on the dielectric layer 110 . The material of the etching protection layer 114 includes: silicon nitride, titanium nitride, other suitable materials, or a combination of the foregoing, and can be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, or physical vapor deposition (such as sputtering or evaporation), other suitable processes, or a combination of the foregoing. In other embodiments, the etch protection layer 114 may be a photoresist material. The thickness of the etch protection layer 114 may be from about 100 Å to about 1000 Å, eg, 300 Å. In some embodiments, the etch protection layer 114 can protect the underlying dielectric layer 110 during subsequent etching processes to avoid defects in the dielectric layer 110 and ensure an aperture ratio of the openings 116O to be formed subsequently.

Referring to FIG. 3 , a first etching process is performed to etch through the etch protection layer 114 and partially through the dielectric layer 110 to form a recess 116R in the dielectric layer 110 . The position of the notch 116R corresponds to the position where the gate metal layer will be formed later. In detail, the first etching process etches through the etch protection layer 114 above the second etch stop layer 112 but does not completely etch through the dielectric layer 110 above the second etch stop layer 112, so that part of the dielectric layer 110 remains in the Below notch 116R. In some embodiments, after the first etching process, the thickness of the remaining dielectric layer 110 under the bottom surface of the recess 116R is about 300 Å to 1000 Å, eg, about 300 Å. In these embodiments, the dielectric layer 110 above the second etch stop layer 112 is not completely removed, which can prevent the etchant from the first etching process from adversely affecting the components below the dielectric layer 110 . According to some embodiments of the present invention, when the material of the etching protection layer 114 includes silicon nitride or titanium nitride and the material of the dielectric layer 110 includes silicon oxide, the first etching process is a dry etching process, and the used etchant includes a The plasma is composed of argon (Ar) or fluorine (F) gas, but the present invention is not limited thereto. In other embodiments, the material of the etching protection layer 114 includes organic materials, such as photoresist, spin on glass (SOG), resin, polyimide. In one embodiment, the material of the etching protection layer 114 includes inorganic materials, such as silicon oxide, titanium nitride, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, and phosphosilicate glass (phosphosilicate glass). glass, PSG), borophosphosilicate glass (BPSG), low-k dielectric materials (dielectric coefficient less than 4), silicon, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide , silicon oxycarbonitride, metal silicide, and/or other suitable dielectric materials.

When the material of the dielectric layer 110 includes silicon oxide, the first etching process is a wet etching process, and the etchant used includes hydrofluoric acid (HF) or buffered silicon oxide etching solution (BOE), but the present invention does not use this as a limit.

Referring to FIG. 4 , a second etching process is performed to remove the dielectric layer 110 under the notch 116R to expose the second etch stop layer 112 and form an opening 116O. According to some embodiments of the present invention, when the material of the dielectric layer 110 includes silicon oxide, the second etching process is preferably a wet etching process, wherein the etchant used includes a buffered silicon oxide etchant (BOE). During the second etching process, the etch protection layer 114 may protect the underlying dielectric layer 110 from etching to avoid defects in the dielectric layer 110 and to prevent defects (if any) from expanding in the dielectric layer 110 . The second etch stop layer 112 can protect the doped compound semiconductor layer 108 during the etching process.

In the aforementioned deposition process of the dielectric layer 110 , since the dielectric layer 110 is conformally deposited on the second etch stop layer 112 , the corners generated by the dielectric layer 110 may be caused by the topographical relief in the dielectric layer 110 . Defects, such as holes and seams, are created. In the conventional manufacturing process, the etching process may also cause defects in the dielectric layer, or the etchant may enter into the apertures of the dielectric layer to expand the apertures, thus causing the gate metal to be subsequently filled when the gate metal is subsequently filled. Fill in the holes of the dielectric layer, causing device short circuit (eg gate-drain short circuit). The method for forming a semiconductor device provided by the embodiment of the present invention includes forming an etch protection layer 114 over the dielectric layer 110, protecting the dielectric layer 110 during the etching process, and preventing the etching process from forming defects in the dielectric layer 110 or causing the dielectric layer The apertures are expanded to avoid short-circuiting of the device.

Referring to FIG. 5 , a removal process is performed to remove the remaining etch protection layer 114 on the dielectric layer 110 . During the removal process, the second etch stop layer 112 may protect the underlying first etch stop layer 111 and the doped compound semiconductor layer 108 . For example, when the etch protection layer 114 and the first etch stop layer 111 comprise the same material, and the second etch stop layer 112 is different from the first etch stop layer 111, the second etch stop layer 112 during the removal process The first etch stop layer 111 may be protected from etching. In some embodiments, when the material of the etching protection layer 114 includes silicon nitride or titanium nitride, the removal process includes a wet etching process, and the etchant used includes an acid such as hydrochloric acid or sulfuric acid combined with hydrogen peroxide. However, the present invention does not This is the limit.

Referring to FIG. 6, a gate metal layer 118 is formed to fill the opening 116O. The material of the gate metal layer 118 may include: metals, metal nitrides, metal oxides, metal alloys, other suitable conductive materials, a combination of the foregoing, or a multilayer structure of the foregoing. For example, metals may include: Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, or other similar materials; metal nitrides may include: MoN, WN, TiN, TaN, TaSiN, TaCN , TiAlN, or other similar materials. In other embodiments, the conductive material of the gate metal layer 118 may include: NiSi, CoSi, TaC, TiAl, or other similar materials. The aforementioned material layers can be formed by deposition processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (eg, sputtering or evaporation), and then patterned , to form the gate metal layer 118 .

Referring to FIGS. 7 and 8, source/drain structures 124/126 may be formed on both sides of the doped compound semiconductor layer 108 after the removal process. In some embodiments, the source/drain structures 124/126 are formed by performing a patterning process to form a pair (or more) through the dielectric layer 110 and the barrier layer 106 and into the channel layer 104. (a) openings 120, depositing a layer of conductive material in the openings 120, patterning the layer of conductive material to form source/drain structures 124/126. The conductive material layer may include the materials of the gate metal layer 118 described above, a combination thereof, or the aforementioned multi-layer structure. In other embodiments, the materials of the source/drain structures 124/126 may include: NiSi, CoSi, TaC, TaSiN, TaCN, TiAl, TiAlN, metal oxides, metal alloys, other suitable conductive materials, combinations of the foregoing, or the aforementioned multilayer structure. In some embodiments, the source/drain structures 124/126 may comprise the same or similar materials as the gate metal layer 118, and may be formed by the same process or by different processes.

In another embodiment, another dielectric layer (not shown) is formed on the gate metal layer 118, and the source/drain structures 124/126 are formed on the other dielectric layer. Openings 120 extend through the further dielectric layer, dielectric layer 110 and barrier layer 106 and into the channel layer 104 with source/drain structures 124/126 filling the openings 120 . In this embodiment, the gate metal layer 118 and the source/drain structures 124/126 are formed in different steps.

In other embodiments, the source/drain structures 124/126 may be formed on both sides of the doped compound semiconductor layer 108 after the dielectric layer 110 is formed on the second etch stop layer 112 and before the removal process is performed. For example, referring to FIG. 9, the source/drain structures 124/126 may be formed after the dielectric layer 110 is formed on the second etch stop layer 112 and before the etch protection layer 114 is formed on the dielectric layer 110. Methods of forming source/drain structures 124/126 include performing a patterning process to form a pair (or more) of openings through dielectric layer 110 and barrier layer 106 and extending into channel layer 104, depositing A layer of conductive material is in the opening, and the layer of conductive material is patterned to form source/drain structures 124/126. The material of the conductive material layer is the same as or similar to the material of the above-mentioned source/drain structures 124/126. In one embodiment, another dielectric layer may be formed on the dielectric layer 110 . Then, as shown in FIG. 10, an etching protection layer 114 is formed on the dielectric layer 110 and the source/drain structures 124/126, or an etching protection layer 114 is formed on another dielectric layer and the source/drain structures on 124/126. Processes similar to those shown in FIGS. 3 to 6 may then be performed to form the semiconductor device 10 shown in FIG. 8 . In such embodiments, the etching protection layer 114 also has the aforementioned effect of protecting the dielectric layer 110 to avoid short circuiting of the device.

Referring to FIG. 11 , compared with the semiconductor device 10 shown in FIG. 8 , the semiconductor device 20 further includes a third etch stop layer 113 located between the doped compound semiconductor layer 108 and the first etch stop layer 111 . In some embodiments, the material of the third etch stop layer 113 may be the same as or similar to the material of the second etch stop layer 112 . The third etch stop layer 113 can be formed by a method similar to the above-described formation method of the first etch stop layer 111 or the second etch stop layer 112 . The thickness of the third etch stop layer 113 may be about 2 nm to about 50 nm, eg, about 10 to 20 nm. In some embodiments of the present invention, the first etch stop layer 111 includes titanium nitride and the second etch stop layer 112 and the third etch stop layer 113 include doped or undoped silicon, which may be a single crystal ( single crystal), poly-crystal, or amorphous. In these embodiments, in addition to some advantages of the first etch stop layer 111 and the second etch stop layer 112 described above, the third etch stop layer 113 can be doped or undoped depending on the desired threshold voltage miscellaneous polysilicon. In further embodiments, the doping concentration of the third etch stop layer 113 can be changed to adjust the threshold voltage.

In some embodiments of the p-type doped doped compound semiconductor layer 108 , due to the low activation rate of the dopant after doping, the unactivated dopant may generate many Charged defects, which in turn affect the performance of semiconductor devices. In these embodiments, in addition to the above-mentioned effects and the ability to protect the underlying doped compound semiconductor layer 108 from being adversely affected by subsequent processes, the undoped silicon in the third etch stop layer 113 can be more compatible with the aforementioned unactivated silicon The dopants compensate each other to further improve the characteristics of the semiconductor device and enable the semiconductor device to provide a higher saturation current. In addition, compared with the p-type doped doped compound semiconductor layer 108, the undoped silicon in the third etch stop layer 113 is an n-type semiconductor material, so the undoped silicon in the third etch stop layer 113 can be combined with The p-type doped doped compound semiconductor layer 108 forms an NP junction. The NP junction is reverse biased when the semiconductor device is on-state, which can reduce the gate leakage current of the semiconductor device and increase the gate breakdown voltage.

The method for forming a semiconductor device provided by an embodiment of the present invention includes forming an etching protection layer on a dielectric layer to protect the dielectric layer during the etching process and prevent the etching process from forming defects in the dielectric layer or making holes in the dielectric layer The expansion prevents the metal in the subsequent process from filling the holes of the dielectric layer and causes the short circuit of the device, thereby improving the electrical properties of the device. The semiconductor device provided by the embodiment of the present invention can avoid device damage during the manufacturing process, for example, during the etching process, the influence of the etchant on the components can be reduced, and the configuration of the device can be adjusted according to the desired threshold voltage. In some embodiments, the device characteristics of the semiconductor device can be further improved and a higher saturation current can be obtained.

The features of several embodiments are summarized above so that those of ordinary skill in the art to which the invention pertains may better understand the various aspects of the invention. Those skilled in the art to which the present invention pertains should appreciate that they can readily utilize the present invention as a basis to design or modify other processes and structures to achieve the same objects and/or advantages of the embodiments described herein . Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and substitutions can be made herein without departing from the present invention spirit and scope.

10,20: Semiconductor devices

100: Substrate

102: Buffer layer

104: Channel Layer

106: Barrier layer

108: Doping compound semiconductor layer

110: Dielectric layer

111: first etch stop layer

112: Second etch stop layer

113: Third etch stop layer

114: Etch protection layer

116R: Notch

116O: Opening

118: gate metal layer

120: Opening

124/126: Source/Drain Structure

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are illustrative only. In fact, the dimensions of elements may be arbitrarily enlarged or reduced to clearly characterize the embodiments of the invention. 1-8 are schematic cross-sectional views illustrating a process of a semiconductor device according to some embodiments of the present invention. FIGS. 9-10 are schematic cross-sectional views illustrating a process of a semiconductor device according to other embodiments of the present invention. FIG. 11 is a schematic cross-sectional view illustrating a process of a semiconductor device according to further embodiments of the present invention.

10: Semiconductor device

100: Substrate

102: Buffer layer

104: Channel Layer

106: Barrier layer

108: Doping compound semiconductor layer

110: Dielectric layer

111: first etch stop layer

112: Second etch stop layer

114: Etch protection layer

116O: Opening

Claims (13)

A method of forming a semiconductor device, comprising: providing a substrate on which a buffer layer, a channel layer and a barrier layer are formed in sequence; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a dielectric layer on the second etch stop layer, wherein the dielectric layer covers part of the doped compound semiconductor layer and the barrier layer exposed by the doped compound semiconductor layer; forming an etching protection layer on the dielectric layer; performing a first etching process to etch through the etch protection layer and partially through the dielectric layer to form a recess in the dielectric layer; performing a second etching process, etching the dielectric layer under the recess to form an opening exposing a portion of the second etch stop layer, wherein during the second etching process, the etching protection layer protects the underlying The dielectric layer is free from etching; performing a removal process to remove the etch protection layer remaining on the dielectric layer; and A gate metal layer is formed to fill the opening. The method for forming a semiconductor device of claim 1, further comprising: forming a third etch stop layer on the doped compound semiconductor layer before forming the first etch stop layer. The method for forming a semiconductor device according to claim 1, wherein the material of the etching protection layer includes: organic material, inorganic material, photoresist, spin-on glass, resin, polyimide, silicon oxide, silicon oxynitride, tetraethyl ether Tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, silicon, silicon carbide, silicon oxynitride , silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, metal silicide, silicon nitride, titanium nitride, or a combination of the foregoing. The method for forming a semiconductor device of claim 1, further comprising: forming a source/drain structure on the dopant compound after forming the dielectric layer on the second etch stop layer and before performing the removing process both sides of the semiconductor layer. The method for forming a semiconductor device of claim 1, wherein the first etching process is a dry etching process and the second etching process is a wet etching process. The method for forming a semiconductor device of claim 1, wherein the first etching process is a first wet etching process and the second etching process is a second wet etching process. The method for forming a semiconductor device of claim 1, further comprising: after the removing process, forming a source/drain structure on both sides of the doped compound semiconductor layer. A semiconductor device, comprising: a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier layer on the channel layer; a doped compound semiconductor layer on a part of the on the barrier layer; a first etch stop layer on the doped compound semiconductor layer; a second etch stop layer on the first etch stop layer; a dielectric layer on the second etch stop layer , wherein the dielectric layer has an opening exposing a portion of the second etch stop layer; and a gate metal layer on a portion of the second etch stop layer. The semiconductor device of claim 8, further comprising a third etch stop layer located between the doped compound semiconductor layer and the first etch stop layer. The semiconductor device of claim 9, wherein the material of the third etch stop layer comprises doped or undoped silicon. The semiconductor device of claim 8, wherein the material of the first etch stop layer comprises: nitride, metal nitride, silicon nitride, titanium nitride, silicon oxynitride, silicon carbonitride, oxycarbonitride, gallium nitride , Aluminum Nitride, Metal Nitride, Molybdenum Nitride, Tungsten Nitride, Tantalum Nitride, Tantalum Silicon Nitride, Tantalum Silicon Nitride, Aluminum Titanium Nitride, or a combination of the foregoing. The semiconductor device of claim 8, wherein the material of the second etch stop layer comprises: doped or undoped silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide , silicon oxycarbonitride, metal silicide, tetraethoxysilane, phosphosilicate glass, borophosphosilicate glass, low-k dielectric materials, or a combination of the foregoing. The semiconductor device of claim 8, further comprising a source/drain structure located on both sides of the doped compound semiconductor layer, and the source/drain structure passes through the dielectric layer and the barrier layer, and into the channel layer.

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