TWI775027B - Semiconductor structure - Google Patents

Abstract

Embodiments provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate having a first region and a second region. The semiconductor structure also includes an epitaxial layer above the substrate. The semiconductor structure also includes a first device on the first region of the substrate, and a second device on the second region of the substrate. The first device includes a first gate electrode, a first source electrode and a first drain electrode disposed at two opposite sides of the first gate electrode, wherein a dielectric layer is disposed on the epitaxial layer and covers the first gate electrode. The second device includes a second gate electrode disposed on the dielectric layer, a second source electrode and a second drain electrode disposed at two opposite sides of the second gate electrode, wherein the second source electrode is electrically connected to the first drain electrode. The semiconductor structure also includes an isolation structure disposed on the substrate, so that the portions of the epitaxial layer respectively disposed in the first region and the second region are isolated from each other by the isolation structure.

Description

semiconductor structure

The present disclosure relates to a semiconductor structure and a method of fabricating the same, and more particularly, to a semiconductor structure and a method of fabricating the same suitable for high voltage operation.

In recent years, semiconductor structures have developed rapidly in the fields of computers and consumer electronics. At present, the semiconductor structure technology has been widely accepted in the product market of metal oxide semiconductor field effect transistors, and has a high market share. Semiconductor structures are used in various electronic applications such as high power devices, personal computers, cell phones, digital cameras and other electronic devices. These semiconductor structures are generally fabricated by depositing insulating or dielectric layers, conductive layer materials, and semiconductor layer materials on a semiconductor substrate, followed by patterning the various material layers using a photolithography process. Thus, circuit devices and components are formed on semiconductor substrates.

Among these devices, high-electron mobility transistors (HEMTs) have advantages such as high output power and high breakdown voltage, so they are widely used in high-power applications. Although existing semiconductor structures and methods of forming them can cope with their original intended use, they still have problems to be overcome in various technical aspects of their structures and fabrications.

Taking system in a package (SiP) as an example, it is to directly package several chips with different functions into an integrated circuit with complete functions (IC), and use wire bonding to electrically connect different chips and then package them to form a SiP semiconductor structure. Although the SoC process is much easier than integrating integrated circuits with different functions into a system on a chip (SoC), the use of wire bonding to connect two components will generate parasitic inductance and parasitic capacitance, which will cause more serious noise. For example, when the change rate of input current (L*di/dt) is very fast, it will cause a spike of current, which in turn limits the operating frequency of the semiconductor structure. Furthermore, if the up and down swing of the peak current is too large, the threshold voltage of the device may be exceeded and the device may be damaged.

Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, and the substrate has a first region and a second region. The above-mentioned semiconductor structure also includes an epitaxial layer above the substrate. The above-mentioned semiconductor structure also includes a first element disposed on the first region of the substrate, and a second element disposed on the second region of the substrate. In some embodiments, the first element includes a first gate electrode located on the epitaxial layer, and a first source electrode and a first drain electrode respectively located on opposite sides of the first gate electrode, wherein a dielectric layer It is formed on the epitaxial layer and covers the first gate electrode. In some embodiments, the second element includes a second gate electrode located on the dielectric layer, and a second source electrode and a second drain electrode respectively located on opposite sides of the second gate electrode, wherein the second source electrode The first drain electrode is electrically connected. The above-mentioned semiconductor structure further includes an isolation structure disposed on the substrate, and the epitaxial layers in the first region and the second region are isolated from each other by the isolation structure.

According to some embodiments, the first gate in the semiconductor structure comprises p-type doped gallium nitride, and the second gate comprises metal or polysilicon.

According to some embodiments, the second gate electrode of the second element in the semiconductor structure is electrically connected to the first source electrode of the first element.

According to some embodiments, the isolation structure in the semiconductor structure penetrates the epitaxial layer and contacts the top surface of the substrate.

According to some embodiments, the semiconductor structure further includes a seed layer on the substrate, wherein the epitaxial layer is on the seed layer.

According to some embodiments, the isolation structure in the semiconductor structure penetrates the epitaxial layer and the seed layer, and the isolation structure contacts the top surface of the substrate.

According to some embodiments, the first source electrode in the semiconductor structure includes two first conductive portions electrically connected to each other, and the first element further includes a first through hole and one of the aforementioned two first conductive portions electrically connected, and the first through hole passes through the epitaxial layer and contacts the seed layer.

According to some embodiments, the second source electrode in the semiconductor structure includes two second conductive portions electrically connected to each other, and the second element further includes a second through hole and one of the aforementioned two second conductive portions electrically connected, and the second through hole passes through the epitaxial layer and contacts the seed layer.

According to some embodiments, the first element in the semiconductor structure is an enhancement mode high voltage transistor and the second element is a depletion mode high voltage transistor.

According to some embodiments, the semiconductor structure further includes an interlayer dielectric layer located on the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer includes the aforementioned dielectric layer covering the first gate and covering the second gate Another dielectric layer of the pole.

According to some embodiments, the semiconductor structure further includes a third element disposed on the second region of the substrate, the third element including a third gate on the dielectric layer, a first gate on opposite sides of the third gate, respectively Three source electrodes and a third drain electrode, wherein the third source electrode of the third element is electrically connected to the second drain electrode of the second element.

According to some embodiments, the third gate electrode of the third element in the semiconductor structure is electrically connected to the second source electrode of the second element.

According to some embodiments, the semiconductor structure further includes another isolation structure disposed on the substrate, and the isolation structure isolates the epitaxial layers corresponding to the second element and the third element from each other.

According to some embodiments, the first element in the semiconductor structure is an enhancement mode high voltage transistor and the second and third elements are depletion mode high voltage transistors.

According to some embodiments, the substrate in the semiconductor structure includes a base and an insulating layer disposed on the base, and the epitaxial layer is located over the insulating layer.

Some embodiments of the present disclosure provide a method of fabricating a semiconductor structure, including providing a substrate having a first region and a second region. The above manufacturing method also includes forming an epitaxial layer over the substrate, and forming an isolation structure on the substrate, wherein the isolation structure isolates the epitaxial layers in the first region and the second region from each other. The above manufacturing method further includes forming a first element in the first region of the substrate, and forming a second element in the second region of the substrate. In some embodiments, the first element includes a first gate electrode located on the epitaxial layer, and a first source electrode and a first drain electrode respectively located on opposite sides of the first gate electrode, wherein a dielectric layer It is formed on the epitaxial layer and covers the first gate electrode. In some embodiments, the second element includes a second gate electrode located on the dielectric layer, and a second source electrode and a second drain electrode respectively located on opposite sides of the second gate electrode, wherein the second source electrode The first drain electrode is electrically connected.

In some embodiments, the above-mentioned manufacturing method of the semiconductor structure further includes electrically connecting the second gate electrode of the second element to the first source electrode of the first element.

In some embodiments, in the above-mentioned manufacturing method of the semiconductor structure, the formed isolation structure penetrates the epitaxial layer and contacts the top surface of the substrate.

In some embodiments, the above-mentioned manufacturing method of the semiconductor structure further includes forming a seed layer on the substrate, wherein the epitaxial layer is formed on the seed layer.

In some embodiments, in the above-mentioned manufacturing method of the semiconductor structure, the isolation structure penetrates the epitaxial layer and the seed layer, and the isolation structure contacts the top surface of the substrate.

In some embodiments, in the above-mentioned manufacturing method of the semiconductor structure, the first source electrode includes two first conductive portions that are electrically connected to each other, and the step of forming the first element further includes forming a first via hole and the aforementioned two first conductive portions. One of the conductive parts is electrically connected, and the first via hole penetrates the epitaxial layer and contacts the seed layer.

In some embodiments, in the above-mentioned manufacturing method of the semiconductor structure, the second source electrode includes two second conductive portions that are electrically connected to each other, and the step of forming the second element further includes forming a second via hole and the aforementioned two first conductive portions. One of the two conductive parts is electrically connected, and the second conductive hole penetrates the epitaxial layer and contacts the seed layer.

According to some embodiments, in the above-mentioned manufacturing method of the semiconductor structure, the manufactured first element is an enhancement type high voltage transistor, and the second element is a depletion type high voltage transistor.

According to some embodiments, in the above-mentioned manufacturing method of the semiconductor structure, the prepared semiconductor structure further includes an interlayer dielectric layer located on the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer includes covering the first element and the second element. A gate dielectric layer and another dielectric layer covering the second gate.

According to some embodiments, the above-mentioned method for fabricating the semiconductor structure further includes forming a third element on the second region of the substrate, the third element including a third gate on the dielectric layer, respectively located at the third gate A third source electrode and a third drain electrode on opposite sides of the . Wherein, the third source electrode is electrically connected with the second drain electrode.

According to some embodiments, in the above-mentioned manufacturing method of the semiconductor structure, all The third gate electrode of the prepared third element is electrically connected to the second source electrode of the second element.

According to some embodiments, the above-mentioned manufacturing method of the semiconductor structure further includes forming another isolation structure on the substrate, and the isolation structure isolates the epitaxial layers corresponding to the second element and the third element from each other.

According to some embodiments, in the above-mentioned manufacturing method of the semiconductor structure, the manufactured first element is an enhancement type high voltage transistor, and the second element and the third element are depletion type high voltage transistors.

In order to make the features and advantages of the embodiments of the present disclosure more obvious and easy to understand, preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

10, 20, 30, 40, 50, 60: Semiconductor structures

100A: The first area

100B: Second area

DE ₁ : first element

DE ₂ : Second element

DE ₃ : The third element

100: Substrate

101: Substrate

102: Insulation layer

102a: Top surface

104: seed layer

106: Buffer layer

108: Channel Layer

110: Barrier layer

111: epitaxial layer

112h: Groove

112: Isolation Structure

113: The first gate

114: first dielectric layer

115: The second gate

115-2: The third gate

115-n: (n+1)th gate

116: Second Dielectric Layer

118: The third dielectric layer

121h, 123h, 125h, 127h: Opening

121: first source electrode

1211: The first conductive part

1212: Second conductive part

123: first drain electrode

124, 129: connecting part

125: Second source electrode

1251: The third conductive part

1252: Fourth conductive part

125-2: Third source electrode

125-n: (n+1)th source electrode

127: Second drain electrode

127-2: Third drain electrode

127-n: (n+1)th drain electrode

125-21, 125-22, 125-n1, 125-n2: Conductive part

113V, 115V, 121V, 127V: Via

S, G, D: endpoints

151: The first through hole

152: Second through hole

152-n: (n+1)th through hole

FIGS. 1A-1G are schematic cross-sectional views showing various intermediate stages of forming the semiconductor structure 100 of FIG. 1G according to some embodiments of the present disclosure.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure, wherein two depletion transistors are connected in series in the second region of the substrate.

3 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure, wherein n depletion transistors are connected in series in the second region of the substrate, and n is a positive integer greater than or equal to 3.

FIG. 4 is an equivalent circuit diagram of a semiconductor structure according to some embodiments of the present disclosure.

FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure, wherein each element has through holes to electrically connect the source electrode and the seed layer.

FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure, wherein each element has through holes to electrically connect the source electrode and the seed layer.

The following disclosure provides numerous embodiments or examples for implementing various elements of the provided semiconductor structures. Specific examples of elements and their configurations are described below to simplify the description of embodiments of the invention. Of course, these are only examples, and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements , so that they are not in direct contact with the examples. Furthermore, embodiments of the present invention may repeat reference numerals and/or letters in different instances. This repetition is for brevity and clarity and is not intended to represent the relationship between the different embodiments discussed.

Furthermore, spatially relative terms such as "below", "below", "below", "above", "above" and the like may be used in the following description A term to simplify the presentation of the relationships between one element or component and other elements or other components as shown in the figures. In addition to the directions depicted in the figures, such spatially relative terms include different orientations of the device in use or operation. The device may be oriented in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

Some variations of the embodiments are described below. Similar reference numerals are used to designate similar elements in the different drawings and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, and after the method, and some of the recited steps may be replaced or deleted for other embodiments of the method.

Embodiments of the present disclosure provide semiconductor structures and methods of fabricating the same. In some embodiments, a plurality of devices connected in series are fabricated on the same substrate, and the epitaxial layers corresponding to different devices are isolated from each other by the isolation structure and the substrate. According to some implementations The device series connection method proposed in the example can also enable the semiconductor structure to realize the application of high-voltage components or ultra-high-voltage components without forming a very thick epitaxial layer. The epitaxial layer with reduced thickness not only reduces the time of the epitaxial process, but also greatly reduces the weight of the epitaxial layer on the substrate and reduces the stress on the substrate caused by the epitaxial layer. Furthermore, each element of the semiconductor structure proposed in some embodiments may be an element that withstands a lower voltage, and a high-voltage application can be realized through the series connection method of the above-mentioned embodiments. In some embodiments, the semiconductor structure includes an enhancement mode transistor and one or more depletion mode transistors in series. In addition, the manufacturing process of the semiconductor structure proposed in some embodiments is a system on a chip (SoC) process, and the fabricated semiconductor structure can avoid the parasitic inductance and parasitic capacitance caused by traditionally using wire bonding to connect different components. The resulting noise further reduces the peak current (spike of current) caused by the high current change rate of input current (di/dt), so as to further improve the electrical performance of the semiconductor structure. Therefore, some embodiments of the present disclosure provide semiconductor structures and fabrication methods thereof with improved electronic properties and good reliability.

In some of the following embodiments, a high-electron mobility transistor (HEMT) is used as an example of the device structure in the semiconductor structure, but the present disclosure is not limited to this, and some other embodiments are also Other types of semiconductor elements can be used.

FIGS. 1A-1G are schematic cross-sectional views showing various intermediate stages of forming the semiconductor structure 10 of FIG. 1G according to some embodiments of the present disclosure.

1A, according to some embodiments, a substrate 100 is provided. The substrate 100 includes a base 101 and an insulating layer 102 disposed on the base 101 . The insulating layer 102 may provide an insulating surface of the substrate 100 . In some embodiments, the substrate 100 includes a substrate 101 and a composite layer that encapsulates the substrate 101 . The composite material layer, for example, covers all surfaces (including upper and lower surfaces and all sides) of the substrate 101 to provide the insulating layer 102 on the substrate 101 as shown in FIG. 1A . In some embodiments, the substrate 101 comprises a ceramic material. Ceramic materials include metallic inorganic materials. In some embodiments, the substrate 101 may be made of silicon carbide (SiC), aluminum nitride (AlN), sapphire (Sapphire), or other suitable materials. The above-mentioned sapphire substrate is alumina. In some embodiments, the composite material layer covering the periphery of the substrate 101 may include a single or multiple layers of insulating material and/or other suitable material layers, wherein the insulating material layer is, for example, oxide, nitride, oxynitride, or other suitable insulating materials. In addition, in some other embodiments, the substrate 101 may be formed of, for example, silicon (Si), silicon carbide, gallium nitride (GaN), silicon dioxide (SiO 2 ), sapphire, or a combination thereof. For example, the substrate 100 is a silicon-on-insulator (SOI) substrate, that is, the substrate 100 includes a silicon base and an insulating layer formed on the silicon base. To simplify the drawings, the substrate 100 in the drawings only shows a portion of the insulating layer 102 above the base 101 . In some embodiments, the substrate 100 may be a single-layer substrate or a multi-layer substrate. The substrate 100 is not limited to a silicon-on-insulator (SOI) substrate, and can also be a silicon wafer or a ceramic substrate. Furthermore, the substrate 100 includes a first region 100A and a second region 100B. According to some embodiments, the first region 100A is a region where the first element D _E1 will be formed later, and the second region 100B is a region where the second element D _E2 will be formed later. In some of the following embodiments, a high-electron mobility transistor (HEMT) is used as an example of the structure of the devices formed in the first region 100A and the second region 100B. In addition, the positions of the first region 100A and the second region 100B can also be arbitrarily adjusted according to the configuration requirements of the semiconductor structure. In some embodiments, the first region 100A is adjacent to the second region 100B.

Next, referring to FIG. 1A , a seed layer 104 is formed over the substrate 100 , and an epitaxial layer 111 is formed over the seed layer 104 .

In some embodiments, the seed layer 104 may be silicon (Si) or other suitable formed of materials. In some embodiments, the method for forming the seed layer 104 may include a selective epitaxy growth (SEG) process, a chemical vapor deposition (CVD) process, and a molecular-beam epitaxy process (molecular-beam). epitaxy, MBE), deposition of doped amorphous semiconductor (eg, Si) followed by solid-phase epitaxial recrystallization (SPER) step, by direct seeding, or other suitable processes . The chemical vapor deposition process is, for example, a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and an ultra-high vacuum chemical vapor deposition (ultra-high vacuum chemical) process. vapor deposition, UHV-CVD) process, or other suitable processes.

As shown in FIG. 1A , in some embodiments, the epitaxial layer 111 includes a buffer layer 106 , a channel, and a structure in which a high electron mobility transistor is used as an element formed in the first region 100A and the second region 100B as an example. layer 108 and barrier layer 110 .

In some embodiments, the buffer layer 106 is formed by epitaxial growth on the seed layer 104 . The buffer layer 106 may help relieve the strain of a channel layer 108 formed over the buffer layer 106 subsequently, and prevent defects from forming in the channel layer 108 above. In some embodiments, the material of the buffer layer 106 is a group III-V semiconductor, such as AlN, GaN, AlxGa1-xN (1<x<1), a combination of the foregoing, or the like. In some embodiments, the buffer layer 106 may be formed by hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), a combination of the foregoing, or formed in a similar way. Although in the embodiment shown in FIG. 1A, the buffer layer 106 is a single-layer structure, in other embodiments, the buffer layer 106 may also be a multi-layer structure.

Next, a channel layer 108 is epitaxially formed on the buffer layer 106 . in some In an embodiment, the channel layer 108 includes an undoped III-V semiconductor material. For example, the channel layer 108 may be formed of undoped gallium nitride (GaN), but the invention is not limited thereto. In some other embodiments, the channel layer 108 includes aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium arsenide (GaAs), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), Indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or combinations thereof. In some embodiments, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metal-organic chemical vapor deposition (MOCVD), other suitable methods, or a combination thereof may be used, while A channel layer 108 is formed.

After that, a barrier layer 110 is epitaxially formed on the channel layer 108 . In some embodiments, barrier layer 110 includes undoped III-V semiconductor material. For example, the barrier layer 110 is formed of undoped aluminum gallium nitride (AlxGa1-xN, where 0<x<1), but the invention is not limited thereto. In some other embodiments, the barrier layer 110 may also include aluminum gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs) ), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or combinations thereof. For example, the barrier layer 110 may be formed over the channel layer 108 using molecular beam epitaxy, metal organic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination thereof.

In some embodiments, the channel layer 108 and the barrier layer 110 comprise dissimilar materials to form a heterogeneous interface between the channel layer 108 and the barrier layer 110 . A two-dimensional electron gas (2DEG) (not shown) can be formed on the hetero interface through the band gap of the hetero materials. Semiconductor structures formed in accordance with some embodiments, such as high electron mobility transistors (HEMTs), may utilize a two-dimensional electron gas as conductive carriers.

Although as in the above-mentioned embodiment, the epitaxial layer 111 is a composite layer containing gallium nitride, However, this disclosure is not limited to this. In addition to the buffer layer 106 , the channel layer 108 and the barrier layer 110 , the epitaxial layer 111 may also include other layers; for example, in some other embodiments, a carbon doped layer ( carbon-doped layer) to increase the breakdown voltage of the semiconductor structure.

Next, referring to FIG. 1B , in some embodiments, a trench 112 h is formed that penetrates the epitaxial layer 111 and contacts the top surface of the substrate 100 . As shown in FIG. 1B , the trenches 112 h pass through the barrier layer 110 , the channel layer 108 , the buffer layer 106 and the seed layer 104 and contact the insulating layer 102 on the substrate 101 . In this example, the top surface 102 a of the insulating layer 102 is used as the top surface of the substrate 100 . Furthermore, in some embodiments, when viewed from above the substrate 100 , the trench 112 h is a part of a connected closed trench, and the closed trench can separate the first area 100A and the second area 100B of the substrate 100 .

A method of forming the trench 112h may include forming a mask layer (not shown) on the barrier layer 110 . Then, the mask layer is patterned by performing a patterning process to form a patterned mask (not shown). The patterning process includes a lithography process and an etching process. The lithography process includes photoresist coating (eg spin coating), soft bake, mask alignment, exposure, post exposure bake, photoresist development, washing and drying (eg hard bake). The etching process includes dry etching or wet etching. As a result, the patterned mask exposes a portion of the barrier layer 110 . Then, using the patterned mask as a mask, a dry etching process, a wet etching process, or a combination of both dry and wet processes is used to form the trench 112h.

Then, referring to FIG. 1C, in some embodiments, one or more insulating materials are filled in the trench 112h to form the isolation structure 112, and on the epitaxial layer 111 (eg, on the barrier layer 110) in the first region 100A ) to form the first gate electrode 113 .

In some embodiments, the insulating material filled in the trench 112 h includes, for example, a nitride, an oxide, or a combination thereof to form the isolation structure 112 . isolation junction The material of the structure 112 can be selected from atomic layer deposition (ALD), chemical vapor deposition, spin-on glass (SOG), flowable chemical vapor deposition (FCVD), high The isolation structure 112 is formed by density plasma chemical vapor deposition or a similar process. In some other embodiments, the isolation structure 112 may include a liner on the sidewalls of the trench 112h. The liner material used depends on the requirements of the process and components, including metal and/or dielectric materials.

Furthermore, in some embodiments, when viewed from above the substrate 100 , the isolation structure 112 is a part of a connected closed structure, and the closed structure formed can separate the first region 100A and the second region of the substrate 100 . The second area 100B. For example, as shown in FIG. 1C, the leftmost isolation structure 112 and the middle isolation structure 112 are respectively a part of the left and right side walls of the closed structure surrounding the first region 100A, and the middle isolation structure 112 is isolated from the rightmost one The structures 112 are part of the left and right side walls, respectively, of the enclosed structure surrounding the second region 100B. In some embodiments, the top-view shape of the closed structure is square, rectangular, or other suitable shapes. The present disclosure does not specifically limit the top-view shape of the closed structure and the area of the surrounding area (ie, the size of the first area 100A and the second area 100B), which may be arbitrarily changed according to the configuration requirements of the semiconductor structure in practical applications. Adjustment.

Then, referring to FIG. 1C again, in some embodiments, a first gate 113 is formed on the barrier layer 110 in the first region 100A, and a first dielectric layer 114 is formed on the barrier layer 110 . The first dielectric layer 114 conformally covers the isolation structure 112 and the first gate electrode 113 . As shown in FIG. 1C , the first gate electrode 113 directly contacts the barrier layer 110 .

In some embodiments, the first gate 113 may be made of p-type doped gallium nitride (p-GaN). In some other embodiments, the first gate 113 may include P-type doping aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide ( InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or a combination of the foregoing. In addition, the method for forming the first gate 113 may include the aforementioned deposition or epitaxial process, and ion implantation or in-situ doping process.

In some embodiments, the first dielectric layer 114 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or other suitable dielectric materials, wherein the thickness of the first dielectric layer 114 is about 1 Angstrom (Å). ) ~ about 1000 angstroms (Å). Furthermore, the first dielectric layer 114 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and high-density plasma chemical vapor deposition (HDPCVD) processes or a combination of the foregoing.

Then, referring to FIG. 1D , in some embodiments, a second gate 115 is formed on the first dielectric layer 114 in the second region 100B, and a second dielectric layer 116 is formed on the first dielectric layer 114 . The second gate electrode 115 directly contacts the first dielectric layer 114 . The second dielectric layer 116 conformally covers the isolation structure 112 and the second gate electrode 115 .

In some embodiments, the second gate 115 may include metal materials, metal silicides, polysilicon, other suitable conductive materials, or combinations thereof. Metal materials such as nickel (Ni), gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper ( Cu) a combination of the foregoing or other suitable materials. In some embodiments, the second gate 115 may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (eg, sputtering), or a similar process. In addition, in some embodiments, the process and materials of the second dielectric layer 116 may be similar or the same as those of the first dielectric layer 114 , which will not be repeated here.

In some embodiments, the first gate 113 is a p-GaN gate, and the first gate 113 and the first source electrode 121 and the first drain electrode 123 subsequently formed on both sides of the first gate 113 (FIG. 1F) can constitute an enhanced mode (E-mode) device. The second gate electrode 115 is a metal gate electrode, and the second gate electrode 115 and the second source electrode 125 and the second drain electrode 127 (FIG. 1F) formed subsequently on both sides of the second gate electrode 115 can be formed A depletion mode (D-mode) device.

Next, as shown in FIG. 1E , in some embodiments, a patterning step is performed on the aforementioned material layers including the second dielectric layer 116 , the first dielectric layer 114 , and the barrier layer 110 , so that in the first region 100A, a patterning step is performed. Openings 121h and 123h are formed and openings 125h and 127h are formed in the second region 100B.

In this example, the openings 121h and 123h in the first region 100A are located on opposite sides of the first gate electrode 113, respectively, so as to form the source electrode and the drain electrode of the _first element DE1 later. In this example, the openings 125h and 127h in the second region 100B are located on opposite sides of the second gate 115, respectively, so as to form the source and drain of the second element DE ₂ later. In some embodiments, openings 121h , 123h , 125h and 127h extend into barrier layer 110 and expose channel layer 108 .

In some embodiments, openings 121h, 123h, 125h, and 127h may be formed simultaneously through a mask layer (not shown) and an etching process. Etching process such as dry etching process, such as reactive ion etching (RIE), electron cyclotron resonance (ERC) etching, inductively-coupled plasma (ICP) etching or similar dry etching etching process.

In some embodiments, an etching apparatus including an etching chamber can be used to provide a gas supply system for an etchant used in the etching process, a bias power generator that can apply bias power to the etching chamber, a crystal Round stage, can be divided evenly A spray head for dispersing etchant and an etch endpoint detector that can monitor the etch signal of the material layer desired to be removed in real time during the etch process. During the etching process, the etchant is accelerated by the bias electric field in the etching chamber, and the second dielectric layer 116 , the first dielectric layer 114 , and the barrier layer 110 are subjected to non-equalization in the direction of the wafer stage. Anisotropic etching.

After the openings 121h, 123h, 125h and 127h are formed, an ashing process may be performed to remove the mask layer.

Next, as shown in FIG. 1F, in some embodiments, appropriate conductive materials are deposited in openings 121h, 123h, 125h, and 127h, in conjunction with a patterning step, to form the source electrodes of the first and second elements, respectively and the drain electrode.

In some embodiments, the deposited conductive material is, for example, gold (Au), nickel (Ni), platinum (Pt), target (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W ), aluminum (Al), copper (Cu), tantalum nitride (TaN), titanium nitride (TiN), tungsten silicide (WSi ₂ ), a combination of the foregoing, or similar materials, to be used in the openings 121h of the first region 100A, The first source electrode 121 and the first drain electrode 123 are respectively formed at 123h, and the second source electrode 125 and the second drain electrode 127 are respectively formed at the openings 125h and 127h of the second region 100B.

As shown in FIG. 1F, in some embodiments, the first source electrode 121 and the first drain electrode 123 in the first region 100A are located on the channel layer 108 and are in electrical contact with the channel layer 108; the second region 100B The second source electrode 125 and the second drain electrode 127 are located on the channel layer 108 and are in electrical contact with the channel layer 108 .

In some embodiments, conduction may be performed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam evaporation, sputtering, or the like deposition of materials. In some embodiments, after depositing the material layers for forming the source/drain electrodes, a high temperature thermal process such as rapid thermal annealing is further included. process to form source-drain ohmic contacts.

As shown in FIG. 1F , the first element DE ₁ formed in the first region 100A includes, for example, a first gate electrode 113 , a first source electrode 121 and a first drain electrode 123 , and the first element DE 1 formed in the second region 100B The two-element DE ₂ includes, for example, a second gate electrode 115 , a second source electrode 125 and a second drain electrode 127 . According to some embodiments, the first element DE ₁ is an enhancement type (E-mode, normally-off) high electron mobility transistor, and the second element DE ₂ is a depletion type (D-mode) high electron mobility transistor.

It should be noted that, according to some embodiments of the present disclosure, the first drain electrode 123 of the first element DE ₁ (in the first region 100A) and the second source electrode 125 of the second element DE ₂ (in the second region 100B) in) electrical connection. In some embodiments, as shown in FIG. 1F, after the conductive material is deposited in the openings 121h, 123h, 125h, and 127h, after an appropriate patterning step, the first drain electrode 123 in the first region 100A can be connected to the The second source electrode 125 in the second region 100B is electrically connected through the connecting portion 124 . In some embodiments, the connection portion 124 , the first drain electrode 123 and the second source electrode 125 have the same conductive material.

Afterwards, referring to FIG. 1G , in some embodiments, a third dielectric layer 118 is formed on the second dielectric layer 116 . As shown in FIG. 1G, the third dielectric layer 118 compliantly covers the _first element DE1 and the _second element DE2. The first dielectric layer 114 , the second dielectric layer 116 and the third dielectric layer 118 may constitute an interlayer dielectric layer (ILD) over the epitaxial layer 111 . In some embodiments, the process and materials of the third dielectric layer 118 may be similar or the same as those of the second dielectric layer 116 and the first dielectric layer 114 , which will not be repeated here.

Next, as shown in FIG. 1G, in some embodiments, via holes 121V and 113V are formed on the first source electrode 121 and the first gate electrode 113 of the first element DE ₁ , respectively, and via holes 121V and 113V are formed on the second element DE ₂ Conductive holes 115V and 127V are formed on the second gate electrode 115 and the second drain electrode 127 respectively, wherein the second gate electrode 115 of the second element DE ₂ and the first source electrode 121 of the first element DE ₁ are connected via the connecting part 129 Complete the electrical connection. It is worth noting that although FIG. 1G shows the connection portion 129 , the connection portion 129 is not in electrical contact with the via hole 113V above the first gate electrode 113 . The process and materials of the via holes 121V, 113V, 115V, 127V and the connecting portion 129 may be similar or the same as the aforementioned source and drain electrodes (filled at the openings 121h, 123h, 125h and 127h) and the connecting portion 124, here The description will not be repeated.

According to some embodiments of the present disclosure, the second gate electrode 115 of the second device DE ₂ in the second region 100B is electrically connected to the first source electrode 121 of the first device DE ₁ in the first region 100A. As shown in FIG. 1G , the second gate electrode 115 and the first source electrode 121 are electrically connected through the connection portion 129 . In some embodiments, the vias 121V, 113V, 115V, 127V and the connection portion 129 have the same conductive material.

According to some embodiments, the above proposed semiconductor structure connects multiple elements to each other in a cascade manner to realize the possibility of high voltage applications. In some embodiments, the elements formed in the first region 100A are, for example, enhancement mode transistors (eg, the first element DE ₁ is an enhancement mode high electron mobility transistor), and the elements formed in the second region 100B are, for example, A depletion type transistor (eg, the second element DE ₂ is a depletion type high electron mobility transistor), and the first drain electrode 123 of the first region 100A is electrically connected to the second source electrode 125 of the second region 100B. Furthermore, in some embodiments, the second gate electrodes 115 of the elements in the second region 100B are electrically connected to the first source electrodes 121 of the elements in the first region 100A. When operating the semiconductor structure 10 shown in FIG. 1G, voltages are applied to the terminals S, G, and D, respectively. For example, in some embodiments, a source voltage is applied to the terminal S through the via 121V to the first The source electrode 121 applies a gate voltage at the terminal G to the first gate 113 via the via hole 113V, and applies a drain voltage to the terminal D via the via hole 127V to the second drain electrode 127 . As shown in the semiconductor structure 10 shown in FIG. 1G , the first element DE ₁ is used as a switching element of the semiconductor structure 10 , and the second element DE ₂ can be turned off (Vgs is less than 0) through the first element DE ₁ .

According to some embodiments of the present disclosure, the epitaxial layer 111 only needs to have the ability to withstand about 650V through the series connection method as shown in the semiconductor structure 10 in FIG. 1G, and can be fabricated on the same substrate to withstand The first element DE ₁ of about 650V and the second element DE ₂ that can withstand about 650V can realize a high voltage application of 1200V. In addition, when 0V and 1200V are respectively applied to the first source electrode 121 and the second drain electrode 127, the electrically connected first drain electrode 123 and the second source electrode 125 are respectively 600V.

Therefore, according to the series connection method of the semiconductor structures 10 proposed by some embodiments of the present disclosure, the semiconductor structure 10 can be applied to a high-voltage device or an ultra-high-voltage device without forming a very thick epitaxial layer 111 . For example, connecting a first element DE ₁ in series with a second element DE ₂ can reduce the thickness of the epitaxial layer 111 originally required to be about 5-10 micrometers (μm) to about 1-5 micrometers (μm). The reduced thickness of the epitaxial layer 111 not only reduces the time of the epitaxial process, but also greatly reduces the weight of the epitaxial layer 111 on the substrate 100 and reduces the stress on the substrate caused by the epitaxial layer 111 to avoid the epitaxial layer. 111 is peeled off from the substrate. Therefore, the fabrication process of the semiconductor structure proposed by some embodiments of the present disclosure can reduce manufacturing cost and improve product reliability.

Furthermore, some embodiments of the present disclosure provide a system-on-a-chip (SoC) semiconductor structure process that is easy to implement and has a low manufacturing cost. As shown in the above-mentioned manufacturing method of the semiconductor structure shown in FIGS. 1A-1G , the first element DE ₁ and the second element DE ₂ are fabricated on the same substrate 100 , and the isolation structure 112 and the insulating layer 102 on the substrate are used to make the corresponding different The epitaxial layers of the elements are isolated from each other, and the elements in different regions are connected in series by connecting parts (eg, metal wires) 124 and 129 in the aforementioned connection manner. Furthermore, compared with the traditional method of fabricating components separately and then using wire bonding to achieve electrical connection (ie, system-in-package, SiP), the semiconductor structures proposed in some embodiments of the present disclosure can avoid the traditional use of wire bonding to connect different components ( For example, the parasitic inductance and parasitic capacitance generated by the transistor) reduce the peak current (spike of current) caused by the high current rate of change (di/dt). The smaller the peak current swing, the less likely the component will be damaged. Therefore, the semiconductor structures proposed by some embodiments of the present disclosure have improved electronic properties and good reliability.

According to some embodiments of the present disclosure, a plurality of depletion-mode (D-mode) transistors can be connected in series in the second region 100B, so that the semiconductor structure formed after the serial connection can realize high voltage or ultra-high voltage operation.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. The difference between the semiconductor structure 20 in FIG. 2 and the semiconductor structure 10 in FIG. 1G is that two depletion transistors are connected in series in the second region 100B of the semiconductor structure 20 , which can reduce the voltage that each transistor needs to withstand, Alternatively, the applicable voltage of the semiconductor structure 20 may be increased. Components in Fig. 2 that are the same as those in Figs. 1A-1G described above are assigned the same or similar reference numerals and their descriptions are omitted.

As shown in FIG. 2 , in some embodiments, the semiconductor structure 20 includes an enhancement mode (E-mode) transistor such as the _first element DE1 disposed in the first region 100A, and two depletion mode (D-mode) transistors. Crystals such as the second element DE ₂ and the third element DE ₃ are disposed in the second region 100B. And the semiconductor structure 20 further includes another isolation structure 112 on the substrate 100, and the isolation structure 112 isolates the epitaxial layers 111 corresponding to the second element DE ₂ and the third element DE ₃ from each other. In some embodiments, the first element DE ₁ is an enhancement-mode high electron mobility transistor (E-mode HEMT), and the second element DE ₂ and the third element DE ₃ are depletion-type high electron mobility transistors (D- mode HEMT).

In some embodiments, the third element DE ₃ includes a third gate electrode 115-2, a third source electrode 125-2, and a third drain electrode 127-2. The third gate electrode 115-2 is located on the first dielectric layer 114, and the third source electrode 125-2 and the third drain electrode 127-2 are located on opposite sides of the third gate electrode 115-2 and extend to in barrier layer 110 and in contact with channel layer 108 . The components included in the third element DE ₃ , the materials used and the related processes are the same as or similar to those included in the second element DE ₂ , and the details are not repeated here.

Furthermore, the concatenation of the three elements is similar to the concatenation of the above examples. For example, in some embodiments, the first drain electrode 123 of the first element DE ₁ is electrically connected to the second source electrode 125 of the second element DE ₂ , and the second drain electrode 127 of the second element DE ₂ is electrically connected The _third source electrode 125-2 of the third element DE3 is connected.

Furthermore, the gate electrode of the element (eg, a depletion transistor) located on the second region 100B of the substrate 100 is electrically connected to the source electrode of the next transistor. For example, in some embodiments, the second gate 115 of the second element DE ₂ is electrically connected to the first source electrode 121 of the first element DE ₁ , and the third gate 115-2 of the third element DE ₃ is electrically connected is electrically connected to the second source electrode 125 of the _second element DE2. When operating the semiconductor structure 20 shown in FIG. 2, a source voltage is applied to the first source electrode 121 at the terminal S, a gate voltage is applied to the first gate 113 at the terminal G, and the terminal S is respectively applied to the first source electrode 121. The point D applies a drain voltage to the third drain electrode 127-2. As shown in the semiconductor structure 20 in FIG. 2 , the first element DE ₁ is used as a switching element of the semiconductor structure 20 , and the second element DE ₂ and the third element DE ₃ can be turned off through the first element DE ₁ .

According to the semiconductor structure 20 of FIG. 2, through the series connection method as shown in the above-mentioned FIG. 2, if a high voltage application of 1200V needs to be realized, the epitaxial layer 111 only needs to have the ability to withstand about 450V, and the same A first element DE ₁ capable of withstanding about 450V, a second element DE ₂ capable of withstanding about 450V, and a third element DE ₃ capable of withstanding about 450V are fabricated on the substrate, and a high voltage application of 1200V can be realized. In addition, when 0V and 1200V are respectively applied to the first source electrode 121 and the third drain electrode 127-2, the first drain electrode 123 and the second source electrode 125 which are electrically connected are respectively 800V and are electrically connected The second drain electrode 127 and the third source electrode 125-2 are respectively 400V.

Furthermore, in the semiconductor structure of some embodiments, n depletion-mode (D-mode) transistors are connected in series in the second region 100B, and n is a positive integer greater than or equal to 3. FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. The components in Fig. 3 that are the same as those in Figs. 1A-1G and Fig. 2 of the previous embodiment are designated by the same or similar reference numerals, and the description thereof is omitted.

As shown in FIG. 3 , in some embodiments, the semiconductor structure 30 includes an enhancement transistor such as a first element DE ₁ disposed in the first region 100A, and n depletion transistors such as a second element DE ₂ , a third The elements DE ₃ , . . . and the (n+1)th element DE _(n+1) are disposed in the second region 100B, where n is a positive integer greater than or equal to 3. And the semiconductor structure 30 includes a plurality of isolation structures 112 to isolate the epitaxial layers 111 corresponding to the elements from each other. In some embodiments, the first element DE ₁ is, for example, an enhancement-mode high electron mobility transistor (E-mode HEMT), the second element DE ₂ , the third element DE ₃ , . . . and the (n+1)th element The element DE _(n+1) is, for example, a depletion type high electron mobility transistor (D-mode HEMT).

Furthermore, in some embodiments, the plurality of elements disposed in the second region 100B have similar components and configurations. For example, the (n+1)th element DE _(n+1) includes the (n+1)th gate electrode 115-n, the (n+1th)th source electrode 125-n, and the (n+1th)th drain electrode 127-n. The (n+1)th gate electrode 115-n is located on the first dielectric layer 114, the (n+1)th source electrode 125-n and the (n+1)th drain electrode 127-n are located on the (n+1)th gate electrode 125-n n+1) Opposite sides of gate 115 - n and extend into barrier layer 110 and contact channel layer 108 . The structures disposed in the second region 100B, the materials used, and the related processes are the same as or similar to the components, materials, and related processes of the second device DE ₂ in the foregoing embodiment, and will not be repeated here.

Furthermore, the concatenation of the three elements is similar to the concatenation of the above examples. For example, in some embodiments, the first drain electrode 123 of the first element DE ₁ is electrically connected to the second source electrode 125 of the second element DE ₂ , and the second drain electrode 127 of the second element DE ₂ is electrically connected The _third source electrode 125-2 of the third element DE3 is connected, and the nth drain electrode 127-(n-1) of the nth element DEn is electrically connected to the (n+1)th element DE( _{n +1)} of the (n+1)th source electrode 125-n, and so on.

Furthermore, the gate electrode of the element (eg, a depletion transistor) located on the second region 100B of the substrate 100 is electrically connected to the source electrode of the next transistor. For example, in some embodiments, the second gate 115 of the second element DE ₂ is electrically connected to the first source electrode 121 of the first element DE ₁ , and the third gate 115-2 of the third element DE ₃ is electrically connected is electrically connected to the second source electrode 125 of the _second element DE2, and the (n+1)th gate 115-n of the (n+1)th element DE _{(n+1) is} electrically connected to the nth element DEn The nth source electrode 125-(n-1), and so on.

When operating the semiconductor structure 30 shown in FIG. 3, a source voltage is applied to the first source electrode 121 at the terminal S, a gate voltage is applied to the first gate 113 at the terminal G, and The point D applies a drain voltage to the (n+1)th drain electrode 127-n. As shown in the semiconductor structure 30 shown in FIG. 3 , the first element DE ₁ is used as the switching element of the semiconductor structure 20 , and the second element DE ₂ , the third element DE 3 , the third element DE 3 , the second element DE ₂ , the third element DE ₃ , the ...and the (n+1)th element DE _(n+1) .

According to the semiconductor structure 30 of FIG. 3, through the series connection method as shown in the above-mentioned FIG. 3, if a high voltage application of 1200V needs to be realized, the epitaxial layer 111 only needs to have a resistance slightly greater than (1200/(n+1) ) V's ability. For example, when n=4, and there are 1 enhancement type transistor and 4 depletion type transistors on the substrate, the epitaxial layer 111 only needs to have the ability to withstand, for example, about 280V~300V (1200/5=240V) to be stable The semiconductor structure 30 is operated. In addition, the first element DE ₁ to the fifth element DE ₅ which can withstand about 280V-300V can be fabricated on the same substrate, and a high-voltage application of 1200V can be realized after being connected in series.

4 is an equivalent circuit diagram of a semiconductor structure 40 according to some embodiments of the present disclosure, wherein the semiconductor structure 40 is connected in series with one enhancement mode transistor (the first region 100A) and five depletion mode transistors (the second region). 100B). For the structure of each component of the semiconductor structure 40, please refer to the first element DE ₁ , the second element DE ₂ , and the third element DE ₃ shown in FIGS. 1G , 2 and 3 in the above-mentioned embodiments.

In addition, although the thickness of the epitaxial layer 111 can be reduced, the more elements connected in series on the substrate 100, the lower the voltage required for each element is. However, the area of the substrate 100 is also increased. Therefore, in practical applications, the thickness of the epitaxial layer can be reduced due to the increased number of components, the increased area of the substrate, the size of the applied product, and other factors to make a trade-off to decide whether to connect the substrates in series. the number of components.

In addition, the present disclosure is not limited to the semiconductor structures proposed in the above embodiments. In some other embodiments, the semiconductor structure may include other components to further improve the electrical performance of the semiconductor structure.

For example, the seed layer 104 under the epitaxial layer 111 may generate parasitic charges accumulated in the seed layer 104 due to the plasma etching process. The parasitic charges accumulated in the seed layer 104 will increase the dynamic on-resistance (dynamic R-on) and cause the current (I-on) to decrease, thereby causing circuit failure and affecting the electrical properties of the semiconductor structure. The semiconductor structures of some other embodiments are proposed below to solve the problem of parasitic charges accumulated in the seed layer 104 .

FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure. The components in Fig. 5 that are the same as those in Fig. 1G above are marked with the same or similar symbols. Please refer to the above for the related structures, materials, processes, and connection between components. The description of the embodiment will not be repeated here.

The difference between the semiconductor structure 50 in FIG. 5 and the semiconductor structure 10 in FIG. 1G is that the source electrodes of each element of the semiconductor structure 50 include two conductive parts that are electrically connected to each other, and one of the conductive parts passes through an additionally formed conductive part. The through-hole is electrically connected to the seed layer 104 to discharge parasitic charges accumulated in the seed layer 104 , which are generated due to the plasma etching process, for example.

As shown in FIG. 5, in some embodiments, the first source electrode 121 of the first element DE ₁ includes a first conductive portion 1211 and a second conductive portion 1212 that are electrically connected to each other, and the first conductive portion 1211 and/ Or the second conductive portion 1212 passes through the epitaxial layer 111 and contacts the seed layer 104 .

Similarly, in some embodiments, the second source electrode 125 of the second element DE ₂ includes two third conductive parts 1251 and a fourth conductive part 1252 that are electrically connected to each other, and the third conductive part 1251 and/or The fourth conductive portion 1252 passes through the epitaxial layer 111 and contacts the seed layer 104 . In this example, the third conductive portion 1251 passes through the epitaxial layer 111 and contacts the seed layer 104 to discharge parasitic charges accumulated in the seed layer 104 .

When operating at high voltage (eg, the operating voltage is above 600V) such as the semiconductor structure 50 in FIG. 5 , the conductive material filled in the through holes 151 and 152 of the epitaxial layer 111 provides a reduction in parasitic charges accumulated in the seed layer 104 . Therefore, the problem that parasitic charges move freely under high voltage and affect the electrical performance of the semiconductor structure can be further solved.

In the semiconductor structures of some other embodiments, two or more depletion transistors may be connected in series in the second region 100B. FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the present disclosure. The components in Fig. 6 that are the same as those in Fig. 3 and Fig. 5 of the previous embodiment are designated by the same or similar reference numerals, and the description thereof is omitted.

As shown in FIG. 6, the second region 100B of the semiconductor structure 60 can be n depletion-type transistors are connected in series, and n is, for example, a positive integer greater than or equal to 3. Furthermore, in some embodiments, the source electrode of each element of the semiconductor structure 60 includes two conductive parts (for example, the first conductive part 1211 and the second conductive part 1212 , the third conductive part 1251 and the fourth conductive part 1251 and the fourth conductive part 1251 and the fourth conductive part conductive part 1252, conductive parts 125-21 and 125-22, ..., conductive parts 125-n1 and 125-n2). And one of the conductive parts of each source electrode can be electrically connected to the seed layer 104 through the through holes (eg, 151 , 152 , 152 - 2 , . . . , 152 - n ) passing through the epitaxial layer 111 .

Therefore, when operating at high voltage (for example, the operating voltage is above 600V) such as the semiconductor structure 60 shown in FIG. 6, the thickness of the epitaxial layer can be reduced, the voltage required by each element can be reduced, and the process can be performed on the same substrate. The aforementioned advantages such as component fabrication enable high-voltage or ultra-high-voltage applications. The conductive material filled in the through-holes of each component provides a release path for parasitic charges accumulated in the seed layer 104. Therefore, the high-voltage operation is shown in FIG. 6 When the semiconductor structure 60 is formed, the random movement of parasitic charges under high voltage can be avoided, and the electrical performance of the semiconductor structure can be further improved.

To sum up, the semiconductor structures proposed by some embodiments of the present disclosure have a plurality of transistor elements connected in series. According to the device series connection method proposed in some embodiments, the semiconductor structure can be applied to a high-voltage device or an ultra-high-voltage device without forming a very thick epitaxial layer. The epitaxial layer with reduced thickness not only reduces the time of the epitaxial process, but also greatly reduces the weight of the epitaxial layer on the substrate and reduces the stress on the substrate caused by the epitaxial layer. Furthermore, each element of the semiconductor structure proposed in some embodiments may be an element that withstands a lower voltage, and a high-voltage application can be realized through the series connection method of the above-mentioned embodiments. In addition, the process of the semiconductor structure proposed in some embodiments is a system-on-chip (SoC) process that is easy to implement and has low manufacturing cost. Multiple components are fabricated on the same substrate, for example, an enhancement transistor and one or more depletion transistors are connected in series, and the epitaxial layers corresponding to different components are isolated from each other by an isolation structure and an insulating layer on the substrate. Through the above-mentioned embodiment The series connection of the components can avoid the noise caused by the parasitic inductance and parasitic capacitance generated by the traditional use of bonding wires to connect different components (such as transistor components), thereby reducing the peak value caused by the high current change rate (di/dt). current (spike of current). The smaller the peak current swing, the less likely the component will be damaged. In addition, according to some other embodiments, the proposed semiconductor structure may further include other components, such as conductive parts connecting the source electrodes of each element in the through holes, so as to provide the release of parasitic charges accumulated in the seed layer. path to further improve the electrical performance of the semiconductor structure. Therefore, some embodiments of the present disclosure provide semiconductor structures and fabrication methods thereof with improved electronic properties and good reliability.

Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can learn some implementations from the present disclosure. In the disclosure of the examples, it is understood that processes, machines, manufactures, compositions of matter, devices, methods and steps developed in the present or in the future, as long as substantially the same functions can be implemented or substantially the same results can be obtained in the embodiments described herein. Some embodiments of the present disclosure are used. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods and steps. In addition, each claimed scope constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each claimed scope and the embodiments.

10: Semiconductor structure

100A: The first area

100B: Second area

DE ₁ : first element

DE ₂ : Second element

100: Substrate

101: Substrate

102: Insulation layer

102a: Top surface

104: seed layer

106: Buffer layer

108: Channel Layer

110: Barrier layer

111: epitaxial layer

112: Isolation Structure

113: The first gate

114: first dielectric layer

115: The second gate

116: Second Dielectric Layer

118: The third dielectric layer

121: first source electrode

123: first drain electrode

124, 129: connecting part

125: Second source electrode

127: Second drain electrode

113V, 115V, 121V, 127V: Via

S, G, D: endpoints

Claims (11)

A semiconductor structure, comprising: a substrate including a first region and a second region; an epitaxial layer located above the substrate; a first element disposed on the first region of the substrate, the first The device comprises: a first gate electrode located on the epitaxial layer, and a dielectric layer formed on the epitaxial layer and covering the first gate electrode, and the dielectric layer does not include III-V semiconductor material; a A first source electrode and a first drain electrode are respectively located on opposite sides of the first gate electrode; a second element is disposed on the second region of the substrate, and the second element comprises: a second gate electrode, located on the dielectric layer; a second source electrode and a second drain electrode are respectively located on opposite sides of the second gate electrode, wherein the second source electrode of the second element and the first The first drain electrode of the element is electrically connected, and the second gate of the second element is electrically connected to the first source electrode of the first element, wherein the second drain electrode, the first source The electrode and the first gate are respectively applied with a drain voltage, a source voltage and a gate voltage, the first gate comprises p-type doped gallium nitride, the second gate comprises metal or polysilicon ; and an isolation structure disposed on the substrate, and the epitaxial layers in the first region and the second region are isolated from each other by the isolation structure. The semiconductor structure of claim 1, wherein the isolation structure penetrates the epitaxial layer and contacts the substrate. The semiconductor structure as described in claim 1, wherein the substrate It comprises a substrate, an insulating layer arranged on the substrate, and a seed crystal layer arranged on the insulating layer, and the epitaxial layer is located above the seed layer. The semiconductor structure of claim 3, wherein the isolation structure penetrates the epitaxial layer and contacts the seed layer. The semiconductor structure of claim 3, wherein the first source electrode includes two first conductive parts that are electrically connected to each other, the first element further includes a first through hole and the aforementioned two first conductive parts One of the conductive parts is electrically connected, and the first through hole passes through the epitaxial layer and contacts the seed layer. The semiconductor structure of claim 1, wherein the dielectric layer comprises silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or a combination thereof. The semiconductor structure described in item 1 of the claimed scope further comprises an interlayer dielectric layer located on the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer comprises covering the first element The dielectric layer of the gate and another dielectric layer covering the second gate. The semiconductor structure described in claim 1 of the claimed scope further comprises: a third element disposed on the second region of the substrate, the third element comprising: a third gate located on the dielectric layer ; A third source electrode and a third drain electrode are respectively located on opposite sides of the third gate; wherein, the third source electrode of the third element and the second drain of the second element Electrodes are electrically connected. The semiconductor structure of claim 8, wherein the third gate of the third element is electrically connected to the second source electrode of the second element, and the third drain of the third element electrode, the first source electrode of the first element, and the first gate The drain voltage, the source voltage and the gate voltage are respectively applied to the electrodes. The semiconductor structure described in claim 8, wherein the isolation structure penetrates the epitaxial layer and contacts the substrate, and the semiconductor structure further comprises: another isolation structure disposed on the substrate so as to correspond to the first isolation structure. The epitaxial layers of the second element and the third element are isolated from each other. The semiconductor structure of claim 8, wherein the first element is an enhancement type high voltage transistor, and the second element and the third element are depletion type high voltage transistors.

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