CN113078098A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN113078098A
CN113078098A CN202010004028.8A CN202010004028A CN113078098A CN 113078098 A CN113078098 A CN 113078098A CN 202010004028 A CN202010004028 A CN 202010004028A CN 113078098 A CN113078098 A CN 113078098A
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substrate
semiconductor structure
layer
gate
source electrode
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林鑫成
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Vanguard International Semiconductor Corp
Vanguard International Semiconductor America
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Vanguard International Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having first and second regions. The semiconductor structure also includes an epitaxial layer over the substrate, a first element and a second element respectively located on the first and second regions of the substrate. The first element comprises a first grid electrode positioned on the epitaxial layer, a first source electrode and a first drain electrode which are respectively positioned at two opposite sides of the first grid electrode, and a dielectric layer is formed on the epitaxial layer and covers the first grid electrode. The second element comprises a second grid electrode positioned on the dielectric layer, and a second source electrode and a second drain electrode which are respectively positioned on two opposite sides of the second grid electrode, wherein the second source electrode is electrically connected with the first drain electrode. The semiconductor structure further comprises an isolation structure arranged on the substrate to isolate the epitaxial layers in the first and second regions from each other. The invention can avoid the noise caused by the parasitic inductance and the parasitic capacitance generated by connecting different elements by the traditional routing.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor structure suitable for high voltage operation and a method for fabricating the same.
Background
In recent years, semiconductor structures have been rapidly developed in the fields of computers, consumer electronics, and the like. Currently, the semiconductor structure technology has been widely accepted in the product market of the metal oxide semiconductor field effect transistor, and has a high market share. Semiconductor structures are used in a variety of electronic applications such as high power devices, personal computers, cell phones, digital cameras, and other electronic devices. These semiconductor structures are typically fabricated by depositing an insulating or dielectric layer, a conductive layer material, and a semiconductor layer material on a semiconductor substrate, followed by patterning the various material layers using a photolithographic (photolithography) process. Thus, circuit devices and components are formed on the semiconductor substrate.
Among these devices, high-electron mobility transistors (HEMTs) have advantages such as high output power and high breakdown voltage, and thus they are widely used in high-power applications. Although existing semiconductor structures and methods for forming the same may be capable of coping with their intended use, there are still problems that need to be overcome in various aspects of structure and fabrication techniques.
Taking system in a package (SiP) as an example, a plurality of chips with different functions are directly packaged into an Integrated Circuit (IC) with complete functions, and then the different chips are electrically connected by wire bonding and then packaged to form a SiP semiconductor structure. Although the process of system on a chip (SoC) is much easier than the process of integrating integrated circuits with different functions into a SoC, the use of wire bonding to connect two devices can generate parasitic inductance and parasitic capacitance, which can generate serious noise. For example, when the current change rate (L × di/dt) is fast, a peak current (spike of current) is generated, which limits the operating frequency of the semiconductor structure. Furthermore, if the swing of the peak current is too large, the threshold voltage of the device may be exceeded, and the device may be damaged.
Disclosure of Invention
Some embodiments of the present invention provide a semiconductor structure. The semiconductor structure comprises a substrate, and the substrate is provided with a first area and a second area. The semiconductor structure also includes an epitaxial layer over the substrate. The semiconductor structure also includes a first element disposed on the first region of the substrate and a second element disposed on the second region of the substrate. In some embodiments, the first element includes a first gate on the epitaxial layer, and a first source electrode and a first drain electrode on opposite sides of the first gate, respectively, wherein a dielectric layer is formed on the epitaxial layer and covers the first gate. In some embodiments, the second element comprises a second gate on the dielectric layer, and a second source electrode and a second drain electrode respectively on opposite sides of the second gate, wherein the second source electrode is electrically connected to the first drain electrode. The semiconductor structure further comprises an isolation structure arranged on the substrate, and the epitaxial layers in the first region and the second region are isolated from each other through the isolation structure.
According to some embodiments, the first gate in the semiconductor structure comprises p-type doped gallium nitride and the second gate comprises metal or polysilicon.
According to some embodiments, the second gate of the second element in the semiconductor structure is electrically connected to the first source electrode of the first element.
According to some embodiments, an isolation structure in the semiconductor structure extends through the epitaxial layer and contacts a top surface of the substrate.
According to some embodiments, the semiconductor structure further comprises a seed layer disposed on the substrate, wherein the epitaxial layer is disposed on the seed layer.
According to some embodiments, an isolation structure in the semiconductor structure extends through the epitaxial layer and the seed layer, and the isolation structure contacts the top surface of the substrate.
According to some embodiments, the first source electrode in the semiconductor structure comprises two first conductive portions electrically connected to each other, the first element further comprises a first via electrically connected to one of the two first conductive portions, and the first via penetrates the epitaxial layer and contacts the seed layer.
According to some embodiments, the second source electrode in the semiconductor structure comprises two second conductive portions electrically connected to each other, the second element further comprises a second via electrically connected to one of the two second conductive portions, and the second via passes through the epitaxial layer and contacts the seed layer.
According to some embodiments, the first element in the semiconductor structure is an enhancement mode high voltage transistor and the second element is a depletion mode high voltage transistor.
According to some embodiments, the semiconductor structure further comprises an interlayer dielectric layer disposed on the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer comprises the dielectric layer covering the first gate and another dielectric layer covering the second gate.
According to some embodiments, the semiconductor structure further comprises a third element disposed on the second region of the substrate, the third element comprising a third gate disposed on the dielectric layer, a third source electrode and a third drain electrode disposed on opposite sides of the third gate, wherein the third source electrode of the third element is electrically connected to the second drain electrode of the second element.
According to some embodiments, the third gate of the third element in the semiconductor structure is electrically connected to the second source electrode of the second element.
According to some embodiments, the semiconductor structure further comprises another isolation structure disposed on the substrate, the isolation structure isolating the epitaxial layers corresponding to the second and third elements from each other.
According to some embodiments, the first element in the semiconductor structure is an enhancement mode high voltage transistor, and the second element and the third element are depletion mode high voltage transistors.
According to some embodiments, the substrate in the semiconductor structure comprises a substrate and an insulating layer disposed on the substrate, and the epitaxial layer is disposed above the insulating layer.
Some embodiments of the present invention provide a method for fabricating a semiconductor structure, which includes providing a substrate having a first region and a second region. The method also includes forming an epitaxial layer over the substrate, and forming an isolation structure on the substrate, wherein the isolation structure isolates the epitaxial layer from each other in the first region and the second region. The method further includes forming a first element in the first region of the substrate and forming a second element in the second region of the substrate. In some embodiments, the first element includes a first gate on the epitaxial layer, and a first source electrode and a first drain electrode on opposite sides of the first gate, respectively, wherein a dielectric layer is formed on the epitaxial layer and covers the first gate. In some embodiments, the second element comprises a second gate on the dielectric layer, and a second source electrode and a second drain electrode respectively on opposite sides of the second gate, wherein the second source electrode is electrically connected to the first drain electrode.
In some embodiments, the method further includes electrically connecting the second gate of the second device to the first source electrode of the first device.
In some embodiments, in the method for fabricating a semiconductor structure, the isolation structure is formed to penetrate the epitaxial layer and contact the top surface of the substrate.
In some embodiments, the method further includes forming a seed layer on the substrate, wherein the epitaxial layer is formed on the seed layer.
In some embodiments, in the method of fabricating a semiconductor structure, the isolation structure penetrates through the epitaxial layer and the seed layer, and the isolation structure contacts the top surface of the substrate.
In some embodiments, the method further includes forming a second via electrically connected to one of the two first conductive portions, the second via penetrating the epitaxial layer and contacting the seed layer.
In some embodiments, the second source electrode comprises two second conductive portions electrically connected to each other, and the step of forming the second element further comprises forming a second via electrically connected to one of the two second conductive portions, the second via penetrating the epitaxial layer and contacting the seed layer.
According to some embodiments, in the method for manufacturing a semiconductor structure, the first device is an enhancement-mode high-voltage transistor, and the second device is a depletion-mode high-voltage transistor.
According to some embodiments, the semiconductor structure further includes an interlayer dielectric layer on the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer includes a dielectric layer covering the first gate and another dielectric layer covering the second gate.
According to some embodiments, the method further includes forming a third element on the second region of the substrate, the third element including a third gate on the dielectric layer, a third source electrode and a third drain electrode on opposite sides of the third gate. Wherein the third source electrode is electrically connected to the second drain electrode.
According to some embodiments, in the method of fabricating a semiconductor structure, the third gate of the fabricated third device is electrically connected to the second source electrode of the second device.
According to some embodiments, the method further comprises forming another isolation structure on the substrate, the isolation structure isolating the epitaxial layers corresponding to the second element and the third element from each other.
According to some embodiments, in the method for manufacturing a semiconductor structure, the first device is an enhancement-type high-voltage transistor, and the second device and the third device are depletion-type high-voltage transistors.
The invention can avoid the noise caused by parasitic inductance and parasitic capacitance generated by connecting different elements by wire bonding, thereby reducing the peak current caused by high current change rate, and the elements are not easy to be damaged.
In order to make the features and advantages of the embodiments of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A-1G are schematic cross-sectional views illustrating various intermediate stages in forming the semiconductor structure 100 of fig. 1G, in accordance with some embodiments of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor structure in which 2 depletion-type transistors are connected in series in a second region of a substrate according to some embodiments of the present invention.
FIG. 3 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention, wherein n depletion-type transistors are connected in series in a second region of a substrate, n being a positive integer greater than or equal to 3.
Fig. 4 is an equivalent circuit diagram of a semiconductor structure according to some embodiments of the invention.
FIG. 5 is a cross-sectional view of a semiconductor structure in which elements have vias to electrically connect a source electrode and a seed layer in accordance with some other embodiments of the present invention.
FIG. 6 is a cross-sectional view of a semiconductor structure in which elements have vias to electrically connect a source electrode and a seed layer in accordance with some other embodiments of the present invention.
Reference numerals
10. 20, 30, 40, 50, 60-semiconductor structures;
100A to a first region;
100B to a second region;
DE1-a first element;
DE2-a second element;
DE3-a third element;
100 to a substrate;
101-a substrate;
102-an insulating layer;
102a to the top surface;
104-seed crystal layer;
106 buffer layers;
108-channel layer;
110-barrier layer;
111-epitaxial layer;
112 h-groove;
112-an isolation structure;
113 to a first gate;
114 to a first dielectric layer;
115 to a second gate;
115-2 to a third gate;
115-n to (n +1) th gates;
116 to a second dielectric layer;
118 to a third dielectric layer;
openings are 121h, 123h, 125h and 127 h;
121-a first source electrode;
1211 to a first conductive portion;
1212 to a second conductive portion;
123 to a first drain electrode;
124. 129-connecting part;
125 to a second source electrode;
1251 to a third conductive portion;
1252 to a fourth conductive portion;
125-2 to a third source electrode;
125-n to (n +1) th source electrodes;
127 to a second drain electrode;
127-2 to a third drain electrode;
127-n to (n +1) th drain electrodes;
125-21, 125-22, 125-n1, 125-n 2-conductive portions;
guide holes 113V, 115V, 121V and 127V;
s, G, D-end point;
151-first through hole;
152-second through hole;
152-n to the (n +1) th through hole.
Detailed Description
The following disclosure provides many embodiments, or examples, for implementing various components of the provided semiconductor structures. Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.
Also, spatially relative terms, such as "below … …," "below … …," "below," "above … …," "above," and other similar terms, may be used in the following description to simplify the presentation of the relationship between an element or component and other elements or components as shown. This spatially relative term includes different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional steps may be provided before, during, or after the method, and that some of the recited steps may be substituted or deleted for other embodiments of the method.
Embodiments of the present disclosure provide semiconductor structures and methods of fabricating the same. In some embodiments, a plurality of series-connected devices are fabricated on the same substrate, and the epitaxial layers corresponding to different devices are isolated from each other by using the isolation structures and the substrate. According to the device serial connection method provided by some embodiments, the semiconductor structure can be applied to high-voltage devices or ultra-high-voltage devices without forming a thick epitaxial layer. The epitaxial layer with the reduced thickness not only reduces the time of the epitaxial process, but also greatly lightens the weight of the epitaxial layer born by the substrate and reduces the stress of the epitaxial layer on the substrate. Furthermore, the elements of the semiconductor structure proposed by some embodiments may be elements that withstand lower voltages, and high voltage applications are realized by the series connection of the above embodiments. In some embodiments, the semiconductor structure includes an enhancement transistor and one or more depletion transistors connected in series. In addition, some embodiments of the present invention provide a process for manufacturing a semiconductor structure, which is a system on a chip (SoC) process, and the manufactured semiconductor structure can avoid the noise caused by the parasitic inductance and the parasitic capacitance generated by the conventional wire bonding for connecting different devices, thereby reducing the peak current (spike of current) caused by the high current change rate (di/dt) to further improve the electrical performance of the semiconductor structure. Accordingly, embodiments of the present invention provide semiconductor structures and methods for fabricating the same with improved electrical characteristics and good reliability.
In the following embodiments, a high-electron mobility transistor (HEMT) is used as an example of the device structure in the semiconductor structure, but the invention is not limited thereto, and other types of semiconductor devices may be used in other embodiments.
Fig. 1A-1G are schematic cross-sectional views illustrating various intermediate stages in forming the semiconductor structure 10 of fig. 1G, in accordance with some embodiments of the present invention.
Referring to fig. 1A, a substrate 100 is provided, according to some embodiments. The substrate 100 includes a base 101 and an insulating layer 102 disposed on the base 101. The insulating layer 102 may provide an insulating surface of the substrate 100. In some embodiments, the substrate 100 comprises a composite layer of the base 101 and the encapsulating base 101. The composite material layer, for example, coats all surfaces (including the upper and lower surfaces and all sides) of the substrate 101 to provide the insulating layer 102 on the substrate 101 as shown in fig. 1A. In some embodiments, the substrate 101 comprises a ceramic material. The ceramic material comprises a metallic inorganic material. In some embodiments, the substrate 101 may be a material comprising silicon carbide (SiC), aluminum nitride (AlN), Sapphire (Sapphire), or other suitable material. The sapphire substrate is alumina. In some embodiments, the composite material layer surrounding the substrate 101 may comprise a single layer or multiple layers of insulating material, such as oxide, nitride, oxynitride, or other suitable insulating material, and/or other suitable materials. In addition, in some othersIn an embodiment, the substrate 101 may be formed of, for example, silicon (Si), silicon carbide, gallium nitride (GaN), silicon dioxide (SiO2), sapphire, or a combination thereof. For example, the substrate 100 is a Silicon On Insulator (SOI) substrate, that is, the substrate 100 includes a silicon substrate and an insulating layer formed on the silicon substrate. To simplify the drawing, the substrate 100 in the drawing only shows a portion of the insulating layer 102 over the base 101. In some embodiments, the substrate 100 may be a single layer substrate or a multi-layer substrate. The substrate 100 is not limited to a Silicon On Insulator (SOI) substrate, and may be a silicon wafer or a ceramic substrate. Further, the substrate 100 includes a first region 100A and a second region 100B. According to some embodiments, the first region 100A is a region where a first element D is to be subsequently formedE1A second region 100B where a second element D is to be subsequently formedE2The area of (a). In some embodiments below, a high-electron mobility transistor (HEMT) is exemplified as a structure of an element formed in the first region 100A and the second region 100B. In addition, the positions of the first region 100A and the second region 100B may be arbitrarily adjusted according to the configuration requirement of the semiconductor structure. In some embodiments, the first region 100A is adjacent to the second region 100B.
Next, referring to fig. 1A, a seed layer (seed layer)104 is formed over the substrate 100, and an epitaxial layer 111 is formed over the seed layer 104.
In some embodiments, the seed layer 104 may be formed of silicon (Si) or other suitable material. In some embodiments, the seed layer 104 may be formed by a Selective Epitaxial Growth (SEG) process, a Chemical Vapor Deposition (CVD) process, a molecular-beam epitaxy (MBE) process, a solid-phase epitaxial recrystallization (SPER) step after depositing a doped amorphous semiconductor (e.g., Si), by directly attaching a seed, or other suitable processes. The chemical vapor deposition process is, for example, a vapor-phase epitaxy (VPE) process, a Low Pressure Chemical Vapor Deposition (LPCVD) process, an ultra-high vacuum chemical vapor deposition (UHV-CVD) process, or other suitable processes.
As shown in fig. 1A, in some embodiments, taking high electron mobility transistors as an example of the structure of the devices formed in the first region 100A and the second region 100B, the epitaxial layer 111 includes a buffer layer 106, a channel layer 108, and a barrier layer 110.
In some embodiments, the buffer layer 106 is epitaxially grown on the seed layer 104. The buffer layer 106 may help to relieve strain (strain) in a channel layer 108 subsequently formed over the buffer layer 106 and prevent defects from forming in the overlying channel layer 108. In some embodiments, the material of the buffer layer 106 is a group III-V semiconductor, such as AlN, GaN, AlxGa1-xN (1< x <1), combinations of the foregoing, or the like. In some embodiments, the buffer layer 106 may be formed by Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), a combination thereof, or the like. Although the buffer layer 106 has a single-layer structure in the embodiment shown in fig. 1A, the buffer layer 106 may have a multi-layer structure in other embodiments.
Next, a channel layer 108 is epitaxially formed on the buffer layer 106. In some embodiments, the channel layer 108 comprises an undoped group III-V semiconductor material. For example, the channel layer 108 may be formed of undoped gallium nitride (GaN), but the invention is not limited thereto. In some other embodiments, the channel layer 108 includes aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable group III-V materials, or combinations thereof. In some embodiments, channel layer 108 may be formed using Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), metalorganic chemical vapor deposition (MOCVD), other suitable methods, or a combination thereof.
Thereafter, a barrier layer 110 is epitaxially formed on the channel layer 108. In some embodiments, barrier layer 110 includes undoped III-V semiconductor material. For example, the barrier layer 110 is formed of undoped gallium aluminum nitride (AlxGa1-xN, wherein 0< x <1), but the invention is not limited thereto. In some other embodiments, the barrier layer 110 may also include aluminum gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or combinations thereof. For example, the barrier layer 110 may be formed on the channel layer 108 by molecular beam epitaxy, metal organic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination thereof.
In some embodiments, the channel layer 108 and the barrier layer 110 comprise dissimilar materials to form a heterogeneous interface between the channel layer 108 and the barrier layer 110. A two-dimensional electron gas (2 DEG) (not shown) may be formed on the hetero-interface by a band gap of the hetero-material. Semiconductor structures formed according to some embodiments, such as High Electron Mobility Transistors (HEMTs), may utilize a two-dimensional electron gas as a conducting carrier.
Although the epitaxial layer 111 is a gallium nitride-containing composite layer as in the above embodiments, the invention is not limited thereto. In addition to the buffer layer 106, the channel layer 108, and the barrier layer 110, the epitaxial layer 111 may also include other layers; for example, in some other embodiments, a carbon-doped layer (carbon-doped layer) may be further formed between the buffer layer 106 and the channel layer 108 to increase the breakdown voltage of the semiconductor structure.
Next, referring to fig. 1B, in some embodiments, a trench 112h is formed through the epitaxial layer 111 and contacts the top surface of the substrate 100. As shown in fig. 1B, the trench 112h passes through the barrier layer 110, the channel layer 108, the buffer layer 106, and the seed layer 104, and contacts the insulating layer 102 on the substrate 101. In this example, the top surface 102a of the insulating layer 102 is taken as the top surface of the substrate 100. Furthermore, in some embodiments, the trench 112h is a portion of a connected closed trench (closed trench) that separates the first region 100A and the second region 100B of the substrate 100 as viewed from above the substrate 100.
The trench 112h may be formed by forming a mask layer (not shown) on the barrier layer 110. Then, the mask layer is patterned by performing a patterning process to form a patterned mask (not shown). The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, washing, and baking (e.g., hard baking). The etching process includes dry etching or wet etching. As a result, the patterned mask exposes a portion of barrier layer 110. Then, using the patterned mask as a mask, a dry etching process, a wet etching process, or a combination of both dry and wet processes is performed to form the trench 112 h.
Then, referring to fig. 1C, in some embodiments, one or more insulating materials are filled in the trench 112h to form an isolation structure 112, and a first gate 113 is formed on the epitaxial layer 111 (e.g., on the barrier layer 110) in the first region 100A.
In some embodiments, the trench 112h is filled with an insulating material, such as a nitride, an oxide, or a combination thereof, to form the isolation structure 112. The isolation structure 112 may be formed by Atomic Layer Deposition (ALD), chemical vapor deposition (cvd), spin-on glass (SOG), Flow Chemical Vapor Deposition (FCVD), high density plasma chemical vapor deposition (hdp cvd), or the like. In some other embodiments, the isolation structure 112 may include a liner (liner) on the sidewall of the trench 112 h. The liner material used may comprise a metal and/or a dielectric material depending on the process and device requirements.
Furthermore, in some embodiments, the isolation structure 112 is a portion of a connected closed structure (i.e., a closed structure) that separates the first region 100A and the second region 100B of the substrate 100 as viewed from above the substrate 100. For example, as shown in fig. 1C, the leftmost isolation structure 112 and the middle isolation structure 112 are part of the left and right sidewalls, respectively, of the enclosure surrounding the first region 100A, while the middle isolation structure 112 and the rightmost isolation structure 112 are part of the left and right sidewalls, respectively, of the enclosure surrounding the second region 100B. In some embodiments, the top view shape of the enclosure structure is square, rectangular, or other suitable shape. The top view shape of the closed structure and the area of the region surrounded by the closed structure (i.e., the size of the first region 100A and the second region 100B) are not particularly limited, and may be arbitrarily changed or adjusted according to the configuration requirements of the semiconductor structure in practical use.
Then, referring again to fig. 1C, in some embodiments, a first gate 113 is formed on the barrier layer 110 in the first region 100A, and a first dielectric layer 114 is formed on the barrier layer 110. The first dielectric layer 114 conformally (conformally) covers the isolation structure 112 and the first gate 113. As shown in fig. 1C, the first gate electrode 113 directly contacts the barrier layer 110.
In some embodiments, the first gate 113 may be made of P-type doped gallium nitride (P-GaN). In some other embodiments, the first gate 113 may comprise P-type doped aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or combinations thereof. In addition, the formation method of the first gate 113 may include the deposition or epitaxy process, ion implantation (ion implantation) or in-situ (in-situ) doping process.
In some embodiments, the first dielectric layer 114 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or other suitable dielectric material, wherein the first dielectric layer 114 has a thickness of about 1 angstrom
Figure BDA0002354555610000111
About 1000 angstroms
Figure BDA0002354555610000112
Furthermore, the first dielectric layer 114 may be formed by a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, or a combination thereof.
Thereafter, referring to fig. 1D, in some embodiments, a second gate electrode 115 is formed on the first dielectric layer 114 in the second region 100B, and a second dielectric layer 116 is formed on the first dielectric layer 114. Wherein the second gate electrode 115 directly contacts the first dielectric layer 114. The second dielectric layer 116 conformally covers the isolation structure 112 and the second gate electrode 115.
In some embodiments, the second gate electrode 115 may comprise a metal material, a metal silicide, a polysilicon, other suitable conductive material, or a combination thereof. Examples of the metal material include nickel (Ni), gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), combinations of the foregoing, and other suitable materials. In some embodiments, the second gate 115 can be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (e.g., sputtering), or the like. In addition, in some embodiments, the process and material of the second dielectric layer 116 may be similar or identical to the process and material of the first dielectric layer 114, and thus, the description is not repeated here.
In some embodiments, the first gate 113 is a p-GaN gate, and the first gate 113, the first source electrode 121 and the first drain electrode 123 (fig. 1F) formed on two sides of the first gate 113 may form an enhanced mode (E-mode) device. The second gate 115 is a metal gate, and the second gate 115, the second source electrode 125 and the second drain electrode 127 (fig. 1F) formed on two sides of the second gate 115 may form a depletion mode (D-mode) device.
Next, as shown in fig. 1E, in some embodiments, the material layers including the second dielectric layer 116, the first dielectric layer 114, and the barrier layer 110 are patterned to form openings 121h and 123h in the first region 100A and openings 125h and 127h in the second region 100B.
In this example, the openings 121h and 123h in the first region 100A are respectively located at two opposite sides of the first gate 113 for forming the first element DE subsequently1A source and a drain. In this example, the openings 125h and 127h in the second region 100B are respectively located at two opposite sides of the second gate 115 for forming the second element DE subsequently2A source and a drain. In some embodiments, openings 121h, 123h, 125h, and 127h extend into barrier layer 110 and expose channel layer 108.
In some embodiments, the openings 121h, 123h, 125h and 127h may be formed simultaneously by a mask layer (not shown) and an etching process. The etching process is, for example, a dry etching process such as Reactive Ion Etching (RIE), electron cyclotron resonance (ERC) etching, Inductively Coupled Plasma (ICP) etching, or the like.
In some embodiments, an etching apparatus including an etch chamber may be used to provide a gas supply system for an etchant used in an etch process, a bias power generator (bias power generator) that may apply bias power to the etch chamber, a wafer stage, a showerhead that may uniformly dispense the etchant, and an etch endpoint detector that may monitor an etch signal of a material layer desired to be removed in real time during the etch process. During the etching process, the etchant is accelerated by the bias electric field in the etching chamber and performs anisotropic (anistropic) etching on the second dielectric layer 116, the first dielectric layer 114 and the barrier layer 110 in the direction of the wafer stage.
After the openings 121h, 123h, 125h, and 127h are formed, an ashing process may be performed to remove the mask layer.
Next, as shown in fig. 1F, in some embodiments, a suitable conductive material is deposited in the openings 121h, 123h, 125h and 127h, and a patterning step is performed to form source electrodes and drain electrodes of the first element and the second element, respectively.
In some embodiments, the deposited conductive material is, for example, gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), tantalum nitride (TaN), titanium nitride (TiN), tungsten silicide (WSi)2) A combination of the above or similar materials to form a first source electrode 121 and a first drain electrode 123 at the openings 121h, 123h of the first region 100A, respectively, and a second source electrode 125 and a second drain electrode 125 at the openings 125h, 127h of the second region 100B, respectivelyAnd poles 127.
As shown in fig. 1F, in some embodiments, the first source electrode 121 and the first drain electrode 123 in the first region 100A are located on the channel layer 108 and electrically contact with the channel layer 108; the second source electrode 125 and the second drain electrode 127 in the second region 100B are located on the channel layer 108 and electrically contact with the channel layer 108.
In some embodiments, the deposition of the conductive material may be performed by Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), electron beam evaporation (electron beam evaporation), sputtering, or the like. In some embodiments, after depositing the material layer for forming the source/drain electrodes, a high temperature thermal process, such as a rapid thermal annealing (rapid thermal annealing) process, is performed to form the source/drain ohmic contacts.
As shown in fig. 1F, a first element DE formed in the first region 100A1For example, a second element DE including a first gate 113, a first source electrode 121 and a first drain electrode 123 formed in the second region 100B2For example, includes a second gate electrode 115, a second source electrode 125, and a second drain electrode 127. According to some embodiments, the first element DE1Is an enhancement mode (i.e. normal-off) high electron mobility transistor, the second element DE2Is a depletion mode (D-mode) high electron mobility transistor.
Notably, according to some embodiments of the present invention, the first element DE1First drain electrode 123 (in the first region 100A) and second element DE2Is electrically connected to the second source electrode 125 (in the second region 100B). In some embodiments, as shown in fig. 1F, after depositing the conductive material in the openings 121h, 123h, 125h and 127h, the first drain electrode 123 in the first region 100A and the second source electrode 125 in the second region 100B may be electrically connected through the connection portion 124 through a suitable patterning step. In some embodiments, the connection portion 124, the first drain electrode 123, and the second source electrode 125 have the same conductive material.
Thereafter, referring to fig. 1G, in some embodiments, the second dielectric layer 1A third dielectric layer 118 is formed over 16. As shown in FIG. 1G, a third dielectric layer 118 conformably covers the first element DE1And a second element DE2. The first dielectric layer 114, the second dielectric layer 116, and the third dielectric layer 118 may constitute an interlayer dielectric layer (ILD) above the epitaxial layer 111. In some embodiments, the process and material of the third dielectric layer 118 may be similar or identical to the process and material of the second dielectric layer 116 and the first dielectric layer 114, and thus, the description is not repeated here.
Next, as shown in FIG. 1G, in some embodiments, in the first element DE1Respectively, and vias 121V and 113V are formed on the first source electrode 121 and the first gate electrode 113, respectively, and the second element DE2And the second gate electrode 115 and the second drain electrode 127 are formed with via holes 115V and 127V, respectively, wherein the second element DE2 Second gate electrode 115 and first element DE1The first source electrode 121 is electrically connected via the connection portion 129. It is noted that although fig. 1G illustrates the connection portion 129, the connection portion 129 is not electrically contacted with the via 113V above the first gate 113. The process and material of the vias 121V, 113V, 115V, 127V and the connection portion 129 may be similar or identical to those of the source and drain electrodes (filled in the openings 121h, 123h, 125h and 127 h) and the connection portion 124, and thus, the description thereof will not be repeated.
According to some embodiments of the invention, the second element DE in the second region 100B2Is electrically connected to the first element DE in the first region 100A1And a first source electrode 121. As shown in fig. 1G, the second gate electrode 115 and the first source electrode 121 are electrically connected through the connection portion 129. In some embodiments, the vias 121V, 113V, 115V, 127V and the connection 129 are of the same conductive material.
According to some embodiments, the semiconductor structure proposed above connects multiple elements to each other by means of a cascade (cascade) to achieve the possibility of high voltage applications. In some embodiments, the element formed in the first region 100A is, for example, an enhancement transistor (e.g., the first element DE)1For an enhancement mode hemt), the devices formed in the second region 100B are, for example, depletion mode transistors (e.g., firstTwo elements DE2A depletion type high electron mobility transistor) and the first drain electrode 123 of the first region 100A is electrically connected to the second source electrode 125 of the second region 100B. Furthermore, in some embodiments, the second gate 115 of the device in the second region 100B is electrically connected to the first source electrode 121 of the device in the first region 100A. In operation of the semiconductor structure 10 shown in FIG. 1G, voltages are applied at the terminal S, G, D, for example, in some embodiments, a source voltage is applied at the terminal S to the first source electrode 121 via the via 121V, a gate voltage is applied at the terminal G to the first gate 113 via the via 113V, and a drain voltage is applied at the terminal D to the second drain electrode 127 via the via 127V. As shown in FIG. 1G, semiconductor structure 10, first element DE1As a switching element of the semiconductor structure 10, via the first element DE1Closable (Vgs less than 0) second element DE2。
According to some embodiments of the present invention, the epitaxial layer 111 only needs to have a capability of withstanding about 650V by the serial connection manner as shown in the semiconductor structure 10 of fig. 1G, and the first device DE withstanding about 650V can be fabricated on the same substrate1And a second element DE capable of withstanding about 650V2Thus, high voltage application of 1200V can be realized. In addition, when 0V and 1200V are applied to the first source electrode 121 and the second drain electrode 127, respectively, the first drain electrode 123 and the second source electrode 125, which are electrically connected, are 600V, respectively.
Therefore, according to the series connection of the semiconductor structure 10 proposed in some embodiments of the present invention, the semiconductor structure 10 can be applied to high voltage devices or ultra high voltage devices without forming a thick epitaxial layer 111. For example, a first element DE1In series with a second element DE2The thickness of the epitaxial layer 111, which originally needs about 5 to 10 micrometers (μm), can be reduced to about 1 to 5 micrometers (μm). The epitaxial layer 111 with a reduced thickness not only reduces the time of the epitaxial process, but also greatly reduces the weight of the epitaxial layer 111 borne by the substrate 100, and reduces the stress of the epitaxial layer 111 on the substrate, so as to prevent the epitaxial layer 111 from being peeled off from the substrate. Accordingly, some embodiments of the present invention provide semiconductor structuresThe process of (2) can reduce the manufacturing cost and improve the reliability of the product.
Furthermore, some embodiments of the present invention provide a process for fabricating a system on a chip (SoC) semiconductor structure that is easy to implement and low in manufacturing cost. As in the method of fabricating the semiconductor structure shown in FIGS. 1A-1G, the first element DE is fabricated on the same substrate 1001And a second element DE2The epitaxial layers corresponding to different devices are isolated from each other by the isolation structures 112 and the insulating layer 102 on the substrate, and the devices in different regions are connected in series by the connection portions (e.g., metal wires) 124 and 129 in the aforementioned connection manner. Moreover, compared to the conventional method in which elements are separately manufactured and then electrically connected by wire bonding (i.e., system on package (SiP)), the semiconductor structure provided in some embodiments of the present invention can avoid the noise caused by parasitic inductance and parasitic capacitance generated by the conventional method in which different elements (e.g., transistor elements) are connected by wire bonding, thereby reducing the peak current (spike of current) caused by high current change rate (di/dt). The smaller the up and down swing of the peak current, the less susceptible the device is to damage. Accordingly, embodiments of the present invention provide semiconductor structures with improved electronic characteristics and good reliability.
According to some embodiments of the present invention, a plurality of depletion-mode (D-mode) transistors may be connected in series in the second region 100B, so that the semiconductor structure formed after the series connection may realize high voltage or ultra high voltage operation.
Fig. 2 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the invention. The semiconductor structure 20 of FIG. 2 differs from the semiconductor structure 10 of FIG. 1G in that two depletion-type transistors are connected in series in the second region 100B of the semiconductor structure 20, which can reduce the voltage that each transistor needs to withstand or increase the voltage that the semiconductor structure 20 can apply. The same or similar reference numerals are used for the same components in fig. 2 as those in the aforementioned fig. 1A to 1G and the description thereof is omitted.
As shown in FIG. 2, in some embodiments, the semiconductor structure 20 includes an enhancement mode (E-mode) transistor such as the first element DE1Disposed in the first region 100A, and two depletion mode (D-mode) transistors, e.g., the secondTwo elements DE2And a third element DE3Is disposed in the second region 100B. The semiconductor structure 20 further includes another isolation structure 112 on the substrate 100, and the isolation structure 112 corresponds to the second element DE2And a third element DE3Are isolated from each other. In some embodiments, the first element DE1For an enhancement mode high electron mobility transistor (E-mode HEMT), the second element DE2And a third element DE3Is a depletion mode high electron mobility transistor (D-mode HEMT).
In some embodiments, the third element DE3Including a third gate 115-2, a third source electrode 125-2, and a third drain electrode 127-2. The third gate electrode 115-2 is disposed on the first dielectric layer 114, and the third source electrode 125-2 and the third drain electrode 127-2 are disposed on opposite sides of the third gate electrode 115-2 and extend into the barrier layer 110 and contact the channel layer 108. Third component DE3Included parts, materials used and related processes and the aforementioned second element DE2The components involved, the materials used, and the associated processes are the same or similar and will not be described in detail herein.
Furthermore, the connection between the three elements is similar to the connection manner of the above example. For example, in some embodiments, the first element DE1Is electrically connected to the second element DE2 Second source electrode 125, second element DE2Is electrically connected to the third element DE3And a third source electrode 125-2.
Furthermore, the gate of the device (e.g., depletion transistor) located in the second region 100B of the substrate 100 is electrically connected to the source electrode of the next transistor. For example, in some embodiments, the second element DE2Is electrically connected to the first element DE1 First source electrode 121, third element DE3Is electrically connected to the second element DE2And a second source electrode 125. In operation of the semiconductor structure 20 shown in FIG. 2, a source voltage is applied to the first source electrode 121 at the terminal S, a gate voltage is applied to the first gate 113 at the terminal G, and a drain voltage is applied to the first gate 113 at the terminal D, respectivelyAnd a third drain electrode 127-2. As shown in the semiconductor structure 20 of fig. 2, a first element DE1As a switching element of the semiconductor structure 20, via a first element DE1Closable second element DE2And a third element DE3。
According to the semiconductor structure 20 of fig. 2, by the serial connection manner as shown in fig. 2, if it is required to implement a high voltage application of 1200V, the epitaxial layer 111 only needs to have a capability of withstanding about 450V, and the first element DE withstanding about 450V can be fabricated on the same substrate1Second element DE capable of bearing about 450V2And a third element DE capable of withstanding about 450V3Thus, high voltage application of 1200V can be realized. In addition, when 0V and 1200V are applied to the first source electrode 121 and the third drain electrode 127-2, respectively, the electrically connected first drain electrode 123 and the second source electrode 125 are 800V, respectively, and the electrically connected second drain electrode 127 and the third source electrode 125-2 are 400V, respectively.
Furthermore, in some embodiments of the semiconductor structure, n depletion-mode (D-mode) transistors are connected in series in the second region 100B, where n is a positive integer greater than or equal to 3. Figure 3 is a cross-sectional schematic view of a semiconductor structure according to some embodiments of the present invention. The same or similar reference numerals are used for the components of fig. 1A to 1G and fig. 2 in fig. 3 that are the same as those of the foregoing embodiment, and the description thereof is omitted.
As shown in FIG. 3, in some embodiments, semiconductor structure 30 comprises an enhancement transistor such as first element DE1Disposed in the first region 100A, and n depletion transistors such as the second element DE2Third element DE3… … and (n +1) th element DE(n+1)And is disposed in the second region 100B, where n is a positive integer greater than or equal to 3. And the semiconductor structure 30 includes a plurality of isolation structures 112 to isolate the epitaxial layers 111 corresponding to the devices from each other. In some embodiments, the first element DE1Such as an enhancement mode high electron mobility transistor (E-mode HEMT), the second element DE2Third element DE3… … and (n +1) th element DE(n+1)Such as depletion mode high electron mobility transistors (D-mode HEMTs).
Furthermore, in some embodiments, the components disposed in the second region 100B have similar components and configurations. For example, the (n +1) th element DE(n+1)Including an (n +1) th gate 115-n, an (n +1) th source electrode 125-n, and an (n +1) th drain electrode 127-n. The (n +1) th gate 115-n is disposed on the first dielectric layer 114, and the (n +1) th source electrode 125-n and the (n +1) th drain electrode 127-n are disposed on opposite sides of the (n +1) th gate 115-n and extend into the barrier layer 110 and contact the channel layer 108. The structure, materials used, and related processes provided in the second region 100B and the second element DE of the previous embodiments2The components, materials used, and associated processes are the same or similar and will not be described in detail herein.
Furthermore, the connection between the three elements is similar to the connection manner of the above example. For example, in some embodiments, the first element DE1Is electrically connected to the second element DE2 Second source electrode 125, second element DE2Is electrically connected to the third element DE3Third source electrode 125-2, n-th element DEnThe n-th drain electrode 127- (n-1) of (n +1) -th element DE(n+1)The (n +1) th source electrode 125-n, and so on.
Furthermore, the gate of the device (e.g., depletion transistor) located in the second region 100B of the substrate 100 is electrically connected to the source electrode of the next transistor. For example, in some embodiments, the second element DE2Is electrically connected to the first element DE1 First source electrode 121, third element DE3Is electrically connected to the second element DE2 Second source electrode 125, and (n +1) th element DE(n+1)Is electrically connected to the n-th element DEnThe nth source electrode 125- (n-1), and so on.
In operation of the semiconductor structure 30 shown in FIG. 3, a source voltage is applied to the first source electrode 121 at the terminal S, a gate voltage is applied to the first gate 113 at the terminal G, and a drain voltage is applied to the (n +1) th drain electrode 127-n at the terminal D, respectively. As shown in the semiconductor structure 30 of FIG. 3, a first element DE1As a switching element of the semiconductor structure 20, via a first element DE1Can close the second element DE on the second area 100B2Third element DE3… … and (n +1) th element DE(n+1)。
According to the semiconductor structure 30 of fig. 3, by the serial connection manner as shown in fig. 3, if it is required to implement a high voltage application of 1200V, the epitaxial layer 111 only needs to have the capability of bearing slightly more than (1200/(n +1)) V. For example, when n is 4, and there are 1 enhancement and 4 depletion transistors on the substrate, the epitaxial layer 111 only needs to have the capability of withstanding, for example, about 280V to 300V (1200/5 is 240V), so as to stably operate the semiconductor structure 30. And the first element DE capable of bearing about 280V-300V can be manufactured on the same substrate1Fifth element DE5After being connected in series, the high-voltage application of 1200V can be realized.
Fig. 4 is an equivalent circuit diagram of a semiconductor structure 40 according to some embodiments of the present invention, wherein the semiconductor structure 40 is formed by connecting 1 enhancement transistor (the first region 100A) and 5 depletion transistors (the second region 100B) in series. Structure of each component of semiconductor structure 40 please refer to the first element DE shown in FIGS. 1G, 2, and 31Second element DE2And a third element DE3。
Further, although the thickness of the epitaxial layer 111 can be reduced as more elements are connected in series on the substrate 100, the voltage to be applied to each element is also reduced. But also increases the area of the substrate 100. Therefore, in practical applications, the number of elements to be connected in series on the substrate can be determined by considering various factors such as the reduced thickness of the epitaxial layer corresponding to the increased number of elements, the increased area of the substrate, and the applied product size.
In addition, the present invention is not limited to the semiconductor structure proposed in the above embodiments. In some other embodiments, the semiconductor structure may include other components to further improve the electrical performance of the semiconductor structure.
For example, the seed layer 104 below the epitaxial layer 111 may be generated by a plasma etching process and accumulate parasitic charges in the seed layer 104. The parasitic charges accumulated in the seed layer 104 may cause a dynamic on-resistance (dynamic R-on) increase, resulting in a current (I-on) decrease, which may cause the circuit to fail and affect the electrical properties of the semiconductor structure. The following presents semiconductor structures of some other embodiments to address the problem of parasitic charge accumulation in the seed layer 104.
Fig. 5 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the invention. In fig. 5, the same or similar components as those in fig. 1G are denoted by the same or similar reference numerals, and the related structures, materials, processes and the serial connection manner between the elements refer to the description of the above embodiments, and are not repeated herein.
The semiconductor structure 50 of fig. 5 differs from the semiconductor structure 10 of fig. 1G described above in that the source electrode of each element of the semiconductor structure 50 comprises two conductive portions electrically connected to each other, and one of the conductive portions is electrically connected to the seed layer 104 through an additionally formed via hole to release parasitic charges generated by, for example, a plasma etching process and accumulated in the seed layer 104.
As shown in FIG. 5, in some embodiments, the first element DE1The first source electrode 121 includes a first conductive portion 1211 and a second conductive portion 1212 electrically connected to each other, and the first conductive portion 1211 and/or the second conductive portion 1212 pass through the epitaxial layer 111 and contact the seed layer 104.
Likewise, in some embodiments, the second element DE2Comprises two third and fourth conductive portions 1251, 1252 electrically connected to each other, and third and/or fourth conductive portions 1251, 1252 pass through epitaxial layer 111 and contact seed layer 104. In this example, the third conductive portion 1251 passes through the epitaxial layer 111 and contacts the seed layer 104 to release parasitic charge accumulated in the seed layer 104.
During high voltage operation (e.g., operation voltage above 600V), such as the semiconductor structure 50 of fig. 5, since the conductive material filled in the through holes 151, 152 of the epitaxial layer 111 provides a path for releasing the parasitic charges accumulated in the seed layer 104, the problem that the parasitic charges randomly move under high voltage to affect the electrical performance of the semiconductor structure can be further solved.
In some other embodiments, 2 or more than 2 depletion transistors may be connected in series in the second region 100B. Fig. 6 is a schematic cross-sectional view of a semiconductor structure according to some other embodiments of the invention. The same or similar reference numerals are used for the components of fig. 3 and 5 in fig. 6 that are the same as those of the foregoing embodiment, and the description thereof is omitted.
As shown in fig. 6, n depletion transistors, for example, a positive integer greater than or equal to 3, may be connected in series in the second region 100B of the semiconductor structure 60. Furthermore, in some embodiments, the source electrodes of the various elements of semiconductor structure 60 include two conductive portions electrically connected to each other (e.g., first conductive portion 1211 and second conductive portion 1212, third conductive portion 1251 and fourth conductive portion 1252, conductive portions 125-21 and 125-22, … …, conductive portions 125-n1 and 125-n 2). And one of the conductive portions of each source electrode may be electrically connected to the seed layer 104 by a via (e.g., 151, 152-2, … …, 152-n) through the epitaxial layer 111.
Therefore, when the semiconductor structure 60 shown in fig. 6 is operated at a high voltage (for example, the operating voltage is over 600V), the semiconductor structure not only has the advantages of reducing the thickness of the epitaxial layer, reducing the voltage to which each device needs to bear, and being capable of performing device fabrication on the same substrate, thereby realizing high voltage or ultra-high voltage application, but also provides a path for releasing the parasitic charges accumulated in the seed layer 104 with the conductive material filled in the through holes of each device, so that when the semiconductor structure 60 shown in fig. 6 is operated at a high voltage, the parasitic charges can be prevented from moving randomly at a high voltage, and the electrical performance of the semiconductor structure can be further improved.
In summary, some embodiments of the present invention provide a semiconductor structure having a plurality of serially connected transistor devices. According to the device serial connection method provided by some embodiments, the semiconductor structure can be applied to high-voltage devices or ultra-high-voltage devices without forming a thick epitaxial layer. The epitaxial layer with the reduced thickness not only reduces the time of the epitaxial process, but also greatly lightens the weight of the epitaxial layer born by the substrate and reduces the stress of the epitaxial layer on the substrate. Furthermore, the elements of the semiconductor structure proposed by some embodiments may be elements that withstand lower voltages, and high voltage applications are realized by the series connection of the above embodiments. In addition, some embodiments provide a semiconductor structure process that is a system on a chip (SoC) process that is easy to implement and low in manufacturing cost. Multiple devices, such as an enhancement transistor and one or more depletion transistors, are formed on the same substrate in series, and the epitaxial layers corresponding to the different devices are isolated from each other by the isolation structure and the insulating layer on the substrate. By the series connection of the devices in the above embodiments, the noise caused by the parasitic inductance and parasitic capacitance generated by the conventional wire bonding of different devices (such as transistor devices) can be avoided, and the peak current (spike of current) caused by the high current change rate (di/dt) can be reduced. The smaller the up and down swing of the peak current, the less susceptible the device is to damage. In addition, according to some other embodiments, the semiconductor structure may further include other components, such as a conductive portion connecting the source electrode of each element in the via hole, to provide a release path for parasitic charges accumulated in the seed layer, so as to further improve the electrical performance of the semiconductor structure. Accordingly, embodiments of the present invention provide semiconductor structures and methods for fabricating the same with improved electrical characteristics and good reliability.
Although embodiments of the present invention and their advantages have been described above, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the process, machine, manufacture, composition of matter, means, methods and steps described in connection with the embodiments disclosed herein will be understood to one skilled in the art to which the present application relates from the disclosure of the embodiments of the present application, and to any variations of the embodiments of the invention provided that the present application may be practiced with substantially the same function or achieve substantially the same result as the presently described embodiments. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes combinations of the respective claims and embodiments.

Claims (28)

1. A semiconductor structure, comprising:
a substrate including a first region and a second region;
an epitaxial layer located above the substrate;
a first element disposed on the first region of the substrate, the first element comprising:
a first grid electrode, which is positioned on the epitaxial layer, and a dielectric layer is formed on the epitaxial layer and covers the first grid electrode;
a first source electrode and a first drain electrode respectively located at two opposite sides of the first gate;
a second element disposed on the second region of the substrate, the second element comprising:
a second gate on the dielectric layer;
a second source electrode and a second drain electrode respectively located at two opposite sides of the second gate, wherein the second source electrode is electrically connected with the first drain electrode; and
an isolation structure disposed on the substrate, wherein the epitaxial layers in the first and second regions are isolated from each other by the isolation structure.
2. The semiconductor structure of claim 1, wherein the second gate of the second element is electrically connected to the first source electrode of the first element.
3. The semiconductor structure of claim 1, wherein the isolation structure extends through the epitaxial layer and contacts the top surface of the substrate.
4. The semiconductor structure of claim 1, further comprising a seed layer on the substrate, wherein the epitaxial layer is on the seed layer.
5. The semiconductor structure of claim 4, wherein the isolation structure extends through the epitaxial layer and the seed layer and contacts the top surface of the substrate.
6. The semiconductor structure of claim 4, wherein the first source electrode comprises two first conductive portions electrically connected to each other, the first element further comprises a first via electrically connected to one of the two first conductive portions, and the first via penetrates the epitaxial layer and contacts the seed layer.
7. The semiconductor structure of claim 6, wherein the second source electrode comprises two second conductive portions electrically connected to each other, the second element further comprises a second via electrically connected to one of the two second conductive portions, and the second via passes through the epitaxial layer and contacts the seed layer.
8. The semiconductor structure of claim 1, wherein the first gate comprises p-type doped gallium nitride and the second gate comprises metal or polysilicon.
9. The semiconductor structure of claim 1, wherein the first device is an enhancement mode high voltage transistor and the second device is a depletion mode high voltage transistor.
10. The semiconductor structure of claim 1, further comprising an interlayer dielectric layer on the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer comprises the dielectric layer covering the first gate and another dielectric layer covering the second gate.
11. The semiconductor structure of claim 1, further comprising:
a third element disposed on the second region of the substrate, the third element comprising:
a third gate on the dielectric layer;
a third source electrode and a third drain electrode respectively located at two opposite sides of the third gate;
wherein the third source electrode of the third element is electrically connected to the second drain electrode of the second element.
12. The semiconductor structure of claim 11, wherein the third gate of the third element is electrically connected to the second source electrode of the second element.
13. The semiconductor structure of claim 11, further comprising:
and another isolation structure disposed on the substrate for isolating the epitaxial layers corresponding to the second and third elements from each other.
14. The semiconductor structure of claim 11, wherein the first element is an enhancement mode high voltage transistor, and the second and third elements are depletion mode high voltage transistors.
15. The semiconductor structure of claim 1, wherein the substrate comprises a substrate and an insulating layer disposed on the substrate, and the epitaxial layer is disposed over the insulating layer.
16. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area;
forming an epitaxial layer above the substrate;
forming an isolation structure on the substrate, wherein the isolation structure isolates the epitaxial layers in the first region and the second region from each other;
forming a first element on the first region of the substrate, the first element comprising:
a first grid electrode, which is positioned on the epitaxial layer, and a dielectric layer is formed on the epitaxial layer and covers the first grid electrode;
a first source electrode and a first drain electrode respectively located at two opposite sides of the first gate; and
forming a second element on the second region of the substrate, the second element comprising:
a second gate on the dielectric layer;
a second source electrode and a second drain electrode are respectively positioned at two opposite sides of the second grid electrode, wherein the second source electrode is electrically connected with the first drain electrode.
17. The method of claim 16, wherein the second gate of the second device is electrically connected to the first source electrode of the first device.
18. The method of claim 16, wherein the isolation structure extends through the epitaxial layer and contacts the top surface of the substrate.
19. The method of claim 16, further comprising forming a seed layer on the substrate, wherein the epitaxial layer is formed on the seed layer.
20. The method of claim 19, wherein the isolation structure extends through the epitaxial layer and the seed layer and contacts the top surface of the substrate.
21. The method of claim 19, wherein the first source electrode comprises two first conductive portions electrically connected to each other, the first element further comprising forming a first via electrically connected to one of the two first conductive portions, the first via penetrating the epitaxial layer and contacting the seed layer.
22. The method of claim 19, wherein the second source electrode comprises two second conductive portions electrically connected to each other, the second element further comprising forming a second via electrically connected to one of the two second conductive portions, the second via penetrating the epitaxial layer and contacting the seed layer.
23. The method of claim 16, wherein the first device is an enhancement-mode high voltage transistor and the second device is a depletion-mode high voltage transistor.
24. The method of claim 16, further comprising an interlayer dielectric layer overlying the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer comprises the dielectric layer covering the first gate and another dielectric layer covering the second gate.
25. The method of fabricating a semiconductor structure of claim 16, further comprising:
forming a third device on the second region of the substrate, the third device comprising:
a third gate on the dielectric layer;
a third source electrode and a third drain electrode respectively located at two opposite sides of the third gate;
wherein the third source electrode is electrically connected to the second drain electrode.
26. The method of claim 25, wherein the third gate of the third element is electrically connected to the second source electrode of the second element.
27. The method of claim 25, further comprising forming another isolation structure on the substrate to isolate the epitaxial layers corresponding to the second and third elements from each other.
28. The method of claim 25, wherein the first element is an enhancement mode high voltage transistor, and the second and third elements are depletion mode high voltage transistors.
CN202010004028.8A 2020-01-03 2020-01-03 Semiconductor structure and manufacturing method thereof Pending CN113078098A (en)

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