CN111223824B

CN111223824B - Semiconductor device and method of forming the same

Info

Publication number: CN111223824B
Application number: CN201811423550.9A
Authority: CN
Inventors: 周政伟; 林信志; 周钰杰
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2018-11-27
Filing date: 2018-11-27
Publication date: 2021-11-09
Anticipated expiration: 2038-11-27
Also published as: CN111223824A

Abstract

The invention provides a semiconductor device and a forming method thereof, wherein the semiconductor device comprises: the semiconductor device includes a first compound group III-V semiconductor layer disposed on a compound substrate, and a second group III-V semiconductor layer disposed on the first compound group III-V semiconductor layer. The semiconductor device also includes a gate structure disposed on the second group III-V semiconductor layer, and a source electrode and a drain electrode disposed on the second group III-V semiconductor layer and on opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure passing through the second III-V semiconductor layer and the first compound III-V semiconductor layer, wherein the field plate is electrically connected to the compound substrate by the conductive structure.

Description

Semiconductor device and method of forming the same

Technical Field

The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices having conductive structures electrically connecting a field plate to a substrate and methods of forming the same.

Background

Semiconductor devices are used in a variety of electronic applications such as high power devices, personal computers, cell phones, digital cameras, and other electronic devices. These semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layer materials, and semiconductor layer materials on a semiconductor substrate, followed by patterning the various material layers using a photolithographic process. Thus, circuit devices and components are formed on the semiconductor substrate.

Among these devices, high-electron mobility transistors (HEMTs) are widely used in high-power applications because they have advantages such as high output power and high breakdown voltage.

Although existing semiconductor devices and methods for forming them are adequate for their intended purposes, they have not been fully satisfactory in every aspect, and thus semiconductor integrated circuits and techniques are still problematic.

Disclosure of Invention

Embodiments of a semiconductor device and methods of forming the same, particularly a High Electron Mobility Transistor (HEMT), are provided. In some embodiments of the present invention, a composite substrate with a high thermal conductivity (thermal conductivity) is used, and a field plate disposed between a gate structure and a drain electrode is electrically connected to the composite substrate through a conductive structure, so as to simultaneously achieve the purpose of reducing an electric field and dissipating heat, thereby improving the operating performance of a high current density semiconductor device.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a first compound group III-V semiconductor layer disposed on a compound substrate, and a second group III-V semiconductor layer disposed on the first compound group III-V semiconductor layer. The semiconductor device also includes a gate structure disposed on the second group III-V semiconductor layer, and a source electrode and a drain electrode disposed on the second group III-V semiconductor layer and on opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure passing through the second III-V semiconductor layer and the first compound III-V semiconductor layer, wherein the field plate is electrically connected to the compound substrate by the conductive structure.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a first compound group III-V semiconductor layer disposed on a compound substrate, and a second group III-V semiconductor layer disposed on the first compound group III-V semiconductor layer. The semiconductor device also includes a source electrode, a gate structure, and a drain electrode disposed on the second III-V semiconductor layer, with the gate structure between the source electrode and the drain electrode. The semiconductor device further includes a first field plate region disposed between the gate structure and the drain electrode, and a first conductive structure electrically connecting the first field plate region and the composite substrate, wherein the first conductive structure is electrically isolated from the source electrode.

According to some embodiments, a method of forming a semiconductor device is provided. A method of forming a semiconductor device includes forming a first compound III-V semiconductor layer on a compound substrate and forming a second III-V semiconductor layer on the first compound III-V semiconductor layer. The method of forming a semiconductor device also includes forming a source electrode, a gate structure, and a drain electrode on the second III-V semiconductor layer, with the gate structure being located between the source electrode and the drain electrode. The method further includes forming a field plate between the gate structure and the drain electrode, and forming a conductive structure through the second III-V semiconductor layer and the first compound III-V semiconductor layer, the field plate being electrically connected to the compound substrate by the conductive structure.

In order to make the features and advantages of the present invention more comprehensible, embodiments of the present invention applied to an enhanced-mode (normal-off) High Electron Mobility Transistor (HEMT) are described in detail below with reference to the attached drawings.

Drawings

The aspects of the embodiments of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that some components (features) may not be drawn to scale according to industry standard practice. In fact, the dimensions of the various elements may be increased or decreased for clarity of discussion.

FIGS. 1A-1G are schematic cross-sectional views illustrating various intermediate stages in forming the semiconductor device of FIG. 1G, according to some embodiments;

FIG. 2 is a top view of a semiconductor device, according to some embodiments, wherein FIG. 1G is a schematic cross-sectional view of the semiconductor device along line I-I' of FIG. 2;

fig. 3 is a top view showing a semiconductor device, according to some embodiments;

fig. 4A is a top view showing a semiconductor device, according to some embodiments;

FIG. 4B is an enlarged schematic view of area A of FIG. 4A, according to some embodiments;

fig. 5 is a top view showing a semiconductor device, according to some embodiments;

fig. 6A is a perspective view showing a semiconductor device, according to some embodiments;

FIG. 6B is a schematic cross-sectional view illustrating a semiconductor device, according to some embodiments, wherein FIG. 6B is a schematic cross-sectional view of the semiconductor device along the line X1-X2 in FIG. 6A;

fig. 7A is a perspective view showing a semiconductor device, according to some embodiments;

FIG. 7B is a schematic cross-sectional view illustrating a semiconductor device, according to some embodiments, wherein FIG. 7B is a schematic cross-sectional view of the semiconductor device along the line X1-X2 in FIG. 7A;

fig. 8A is a perspective view showing a semiconductor device, according to some embodiments; and

fig. 8B is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments, wherein fig. 8B is a schematic cross-sectional view of the semiconductor device along the line X1-X2 in fig. 8A.

Description of the symbols of the drawings:

100a, 100b, 100c, 100d, 100e, 100f, 100g to semiconductor devices;

101-a substrate;

103-a buffer layer;

105-a seed crystal layer;

106-composite substrate;

107 to a first compound group III-V semiconductor layer;

107' -a pedestal;

107's to the top surface;

107' -fin structure;

109 to a second III-V semiconductor layer;

111-a gate structure;

112-first groove;

113-a first conductive portion;

115 to a first dielectric layer;

117-source electrode;

119-a drain electrode;

121-a second conductive portion;

123 to a second dielectric layer;

125-gate metal layer;

127 to a third dielectric layer;

129-field plate;

129a to a first field plate region;

129b to a second field plate region;

129c to a third field plate region;

131 to a fourth dielectric layer;

132-a second trench;

133a to a third conductive portion;

133b, 133d to a conductive layer;

133c, 133e to guide holes;

133c1 to a first guide hole;

133c2 to a second guide hole;

133c3 to a third guide hole;

134-opening;

150a, 150b, 150c, 150d1, 150d2, 150d 3-conductive structure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different components of the provided semiconductor devices. Specific examples of components and arrangements thereof are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to be limiting. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional operations may be provided before, during, or after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

Fig. 1A-1G are schematic cross-sectional views illustrating various intermediate stages in forming the semiconductor device 100a of fig. 1G, according to some embodiments.

According to some embodiments, as shown in fig. 1A, a composite substrate 106 is provided. The composite substrate 106 includes a substrate 101, a buffer layer 103 disposed on the substrate 101, and a seed layer 105 disposed on the buffer layer 103. It is noted that the substrate 101 may be made of a material having a high heat transfer coefficient, such as aluminum nitride (AlN). In some embodiments, the substrate 101 comprises a ceramic material. The ceramic material comprises a metallic inorganic material. In some other embodiments, the substrate 101 may be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), silicon dioxide (SiO)₂) Sapphire (Sapphire), or a combination of the foregoing. The sapphire substrate is composed of alumina and gallium nitride formed on the alumina.

In some embodiments, the buffer layer 103 is disposed as a spacer layer between the seed layer 105 and the substrate 101, so as to prevent the seed layer 105 from directly contacting the substrate 101. The buffer layer 103 may be formed of silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other materials. In some embodiments, the buffer layer 103 may be formed by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), other suitable methods, or a combination thereof. Further, in some embodiments, the buffer layer 103 may be a multilayer structure.

In some embodiments, the seed layer 105 may be formed of silicon (Si) or other suitable material. In some embodiments, the seed layer 105 may be formed by a Selective Epitaxial Growth (SEG) process, a Chemical Vapor Deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a Low Pressure Chemical Vapor Deposition (LPCVD) process, an ultra-high vacuum chemical vapor deposition (UHV-CVD) process, a molecular beam epitaxy process, a solid-phase epitaxial recrystallization (r) step after depositing a doped amorphous semiconductor (e.g., Si), a direct-seeded transfer process, or other suitable processes. Fig. 1A illustrates the composite substrate 106 composed of the substrate 101, the buffer layer 103 and the seed layer 105, but the composite substrate 106 may also include other layers, which is not limited by the disclosure.

Next, according to some embodiments, as shown in fig. 1B, a first compound III-V semiconductor layer 107 is formed on the compound substrate 106, and a second III-V semiconductor layer 109 is formed on the first compound III-V semiconductor layer 107. In some embodiments, the first compound III-V semiconductor layer 107 is made of undoped (GaN) or a combination of multiple layers of doped and undoped gallium nitride interleaved, and the second III-V semiconductor layer 109 is made of doped aluminum gallium nitride (AlGaN).

In some other embodiments, the material of the first and second III-V semiconductor layers 107 and 109 may comprise aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or combinations of the foregoing. It is noted that the first and second III-V semiconductor layers 107 and 109 comprise different materials to form a heterojunction (heterojunction), such that the interface between the first and second III-V semiconductor layers 107 and 109 generates a two-dimensional electron gas (2 DEG) current by a band gap difference of the heterogeneous materials.

In addition, the method of forming the first and second III-V semiconductor layers 107, 109 may include Metal Organic Chemical Vapor Deposition (MOCVD) or other suitable methods. In some other embodiments, the first and second compound III-V semiconductor layers 107 and 109 may each comprise a multi-layered structure.

Next, as shown in fig. 1B, a gate structure 111 is formed on the second III-V semiconductor layer 109, and a first trench 112 is formed through the second III-V semiconductor layer 109, the first compound III-V semiconductor layer 107, the seed layer 105, and the buffer layer 103.

In some embodiments, the gate structure 111 may be made of P-type doped gallium nitride. In some other embodiments, the gate structure 111 may comprise P-type doped aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or combinations thereof. In addition, the gate structure 111 may be formed by the deposition or epitaxy process, and ion implantation or in-situ doping process.

In addition, the gate structure 111 may be selectively formed. For example, the gate structure 111 may be omitted in a depletion mode (normal-on) High Electron Mobility Transistor (HEMT). In this embodiment, the subsequently formed gate metal layer 125 will directly contact the second III-V semiconductor layer 109, and the subsequently formed gate metal layer 125 will serve as the gate structure of the semiconductor device.

Notably, a portion of the second III-V semiconductor layer 109, the first compound III-V semiconductor layer 107, the seed layer 105, and the buffer layer 103 are removed to form the first trench 112. The formation method of the first trench 112 may include forming a mask layer (not shown) on the second III-V semiconductor layer 109. Then, the mask layer is patterned by performing a patterning process to form a patterned mask (not shown). The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, washing, and baking (e.g., hard baking). The etching process includes dry etching or wet etching. As a result, the patterned mask exposes a portion of the second III-V semiconductor layer 109. Then, a dry etching or wet etching process is performed using the patterned mask as a mask to form the first trench 112.

According to some embodiments, as shown in fig. 1C, a first conductive portion 113 is formed within the first trench 112, and a first dielectric layer 115 is formed on the second III-V semiconductor layer 109. The first dielectric layer 115 conformally (conformamally) covers the first conductive portion 113 and the gate structure 111.

In some embodiments, the first conductive portion 113 may be made of polysilicon, metal, or other conductive material. The first conductive portion 113 may be formed by a deposition process, such as a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, or a combination thereof.

In addition, the first dielectric layer 115 may be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Furthermore, the first dielectric layer 115 may be formed by a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, or a combination thereof.

According to some embodiments, as shown in fig. 1D, a second conductive portion 121 is formed on the first conductive portion 113, and a source electrode 117 and a drain electrode 119 are formed on the second III-V semiconductor layer 109. Specifically, the second conductive portion 121, the source electrode 117, and the drain electrode 119 pass through the first dielectric layer 115 and the second III-V semiconductor layer 109. In some other embodiments, the bottom portions of the source electrode 117 and the drain electrode 119 are embedded within the first compound III-V semiconductor layer 107. In the present embodiment, the gate structure 111 is located between the source electrode 117 and the drain electrode 119.

In some embodiments, the second conductive portion 121, the source electrode 117, and the drain electrode 119 are made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), or other suitable materials. In addition, the second conductive portion 121, the source electrode 117, and the drain electrode 119 may be a single-layered metal structure or a multi-layered metal stack structure. Ohmic contacts (Ohmic contacts) are formed between the source electrode 117, the drain electrode 119, and the first compound III-V semiconductor layer 107.

It is noted that in some embodiments, the second conductive portion 121 is formed of the same material as the source electrode 117 and the drain electrode 119 in the same process. In addition, the formation method of the second conductive portion 121, the source electrode 117, and the drain electrode 119 may be similar or identical to the formation method of the first conductive portion 113, and thus, a description thereof will not be repeated.

Continuing with the foregoing, according to some embodiments, as shown in fig. 1E, a second dielectric layer 123 is formed on the first dielectric layer 115, and a gate metal layer 125 is formed on the gate structure 111. Specifically, the gate metal layer 125 passes through the second dielectric layer 123 and the first dielectric layer 115, and directly contacts the gate structure 111.

In some embodiments, the process and material of the second dielectric layer 123 may be similar or identical to the process and material of the first dielectric layer 115, and thus, the description is not repeated here. Furthermore, in some embodiments, the gate metal layer 125 may be made of a conductive material, such as nickel (Ni), gold (Au), a combination of the foregoing, or other suitable materials. A Schottky contact (Schottky contact) is formed between the gate metal layer 125 and the gate structure 111. The formation method of the gate metal layer 125 may be similar to or the same as the formation method of the first conductive portion 113, and thus, the description thereof will not be repeated.

According to some embodiments, as shown in fig. 1F, a third dielectric layer 127 is formed on the second dielectric layer 123, and a field plate 129 is formed on the third dielectric layer 127. Specifically, the field plate 129 is located on the gate metal layer 125 and extends between the gate metal layer 125 and the drain electrode 119, and the field plate 129 is electrically isolated from the gate metal layer 125 by the third dielectric layer 127.

In some embodiments, the process and material of the third dielectric layer 127 may be similar or identical to the process and material of the first dielectric layer 115, and thus, the description is not repeated here. Furthermore, in some embodiments, the field plate 129 may be made of polysilicon, metal, or other suitable conductive material, and may be formed using a deposition process and a patterning process.

Subsequently, a fourth dielectric layer 131 is formed on the third dielectric layer 127. The process and material of the fourth dielectric layer 131 may be similar or identical to those of the first dielectric layer 115, and thus, the description thereof will not be repeated. Next, a second trench 132 is formed on the second conductive portion 121, and an opening 134 is formed on the field plate 129. Specifically, a portion of the second dielectric layer 123, the third dielectric layer 127, and the fourth dielectric layer 131 is removed to form a second trench 132 exposing the second conductive portion 121, and another portion of the fourth dielectric layer 131 is removed to form an opening 134 exposing the field plate 129. In some embodiments, the second trench 132 and the opening 134 may be formed in the same etching process.

According to some embodiments, as shown in fig. 1G, a third conductive portion 133a is formed within the second trench 132, a conductive layer 133b is formed on the third conductive portion 133a, a via 133c is formed within the opening 134, and a conductive layer 133d is formed on the via 133 c. In some embodiments, the third conductive portion 133a, the conductive layer 133b, the via 133c, and the conductive layer 133d may be made of metal, polysilicon, or other suitable conductive materials, and may be formed using a deposition process and a patterning process.

After the

conductive layers

133b and 133d are formed, the semiconductor device 100a having the conductive structure 150a is completed. It is noted that the conductive structure 150a includes the first conductive portion 113, the second conductive portion 121, and the third conductive portion 133a, and the conductive structure 150a and the gate metal layer 125 are located at two opposite sides of the source electrode 117.

Fig. 2 is a top view of a semiconductor device 100a, according to some embodiments, wherein fig. 1G is a cross-sectional view of the semiconductor device 100a along the line I-I' in fig. 2. Referring to fig. 1G and 2, conductive layer 133b and conductive layer 133d are connected ring structures, and field plate 129 is electrically connected to substrate 101 within composite substrate 106 by way of via 133c, the ring structure comprising

conductive layers

133b and 133d, and conductive structure 150 a.

In addition, in some embodiments, as shown in fig. 2, an additional via hole 133e can be provided to electrically connect the field plate 129 with the ring structure comprising

conductive layers

133b and 133 d. In some embodiments, any of the guide holes 133c and 133e may be omitted.

In some embodiments, the field plate 129 extends between the gate metal layer 125 and the drain electrode 119 to reduce the electric field in the semiconductor device 100a near the drain electrode 119, so that the electric field between the gate metal layer 125 and the drain electrode 119 is less dense, thereby reducing or delaying the occurrence of breakdown (breakdown). In the present embodiment, the conductive structure 150a penetrating through the second III-V semiconductor layer 109 and the first compound III-V semiconductor layer 107 is disposed to electrically connect the field plate 129 with the compound substrate 106 having a high thermal conductivity (e.g., the compound substrate 106 including the substrate 101 made of aluminum nitride), so as to simultaneously achieve the objectives of reducing the electric field and dissipating heat, thereby improving the operation performance of the high current density semiconductor device 100 a.

In addition, since the conductive structure 150a is disposed at a position far from the active region between the source electrode 117 and the drain electrode 119, damage to the semiconductor device 100a can be avoided. Furthermore, the conductive structure 150a of the present embodiment does not penetrate through the substrate 101 of the composite substrate 106 and does not extend to a position directly under the source electrode 117, in other words, the conductive structure 150a does not extend to the back side of the composite substrate 106 and does not extend to a position directly under the active region, so that the high breakdown voltage of the semiconductor device 100a can be maintained, and the applicable voltage range of the semiconductor device 100a is not limited.

Fig. 3 is a top view showing a semiconductor device 100b, according to some embodiments. The semiconductor device 100b differs from the semiconductor device 100a in the arrangement position of the conductive structure.

According to some embodiments, as shown in fig. 3, in the semiconductor device 100b, a conductive structure 150b electrically connecting the field plate 129 to the composite substrate 106 is provided under the field plate 129, and the conductive structure 150b is located in a range directly under the field plate 129. Specifically, the projection of the conductive structure 150b onto the top surface of the composite substrate 106 falls within the projection of the field plate 129 onto the top surface of the composite substrate 106. The process and material of the conductive structure 150b may be similar or identical to those of the conductive structure 150a, and thus, the description thereof will not be repeated.

In addition, since the conductive structure 150b of the semiconductor device 100b is disposed directly below the field plate 129, the via hole 133c and the ring structure including the

conductive layers

133b and 133d in the semiconductor device 100a can be omitted, thereby reducing the device size and creating a larger wiring space. The processes and materials of other components in the semiconductor device 100b may be similar or identical to those of the semiconductor device 100a, and thus, the description thereof will not be repeated.

Fig. 4A is a top view of a semiconductor device 100c according to some embodiments, and fig. 4B is an enlarged schematic view of a region a of the semiconductor device 100c of fig. 4A according to some embodiments. The semiconductor device 100c of fig. 4A and 4B differs from the semiconductor device 100a of fig. 2 in the shape of the field plate.

According to some embodiments, as shown in fig. 4A and 4B, in the semiconductor device 100c, the field plate 129 includes a first field plate region 129a, a second field plate region 129B, and a third field plate region 129 c. In some embodiments, the first, second and third

field plate regions

129a, 129b and 129c are disposed between the gate metal layer 125 and the drain electrode 119, and the first, second and third

field plate regions

129a, 129b and 129c are physically separated from each other.

In the semiconductor device 100c, since the three field plate regions (i.e., the first field plate region 129a, the second field plate region 129b, and the third field plate region 129c) are disposed between the gate metal layer 125 and the drain electrode 119 and are separated from each other, the electric field near the drain electrode 119 can be reduced compared to the semiconductor device 100a, so that the electric field between the gate metal layer 125 and the drain electrode 119 is more dispersed, and the occurrence of breakdown is reduced or delayed.

In addition, the first field plate region 129a is electrically connected to the ring structure including the

conductive layers

133b and 133d through the first via 133c1 on the first field plate region 129a, the second field plate region 129b is electrically connected to the ring structure including the

conductive layers

133b and 133d through the second via 133c2 on the second field plate region 129b, and the third field plate region 129c is electrically connected to the ring structure including the

conductive layers

133b and 133d through the third via 133c3 on the third field plate region 129c, so that the first, second and third

field plate regions

129a, 129b and 129c are electrically connected to the composite substrate 106 through the aforementioned ring structure and the conductive structure 150 c.

The processes and materials of the first via 133c1, the second via 133c2, and the third via 133c3 may be similar or identical to the

vias

133c and 133e of fig. 1G and 2, and the processes and materials of the conductive structure 150c may be similar or identical to the conductive structure 150a, which will not be repeated herein.

Two first guide holes 133c1, two second guide holes 133c2, and two third guide holes 133c3 are shown in fig. 4A and 4B, however, the number of first guide holes 133c1, second guide holes 133c2, and third guide holes 133c3 may not be limited thereto. For example, any of the first vias 133c1, any of the second vias 133c2, and any of the third vias 133c3 may be omitted in the semiconductor device 100 c. The processes and materials of other components in the semiconductor device 100c may be similar or identical to those of the semiconductor device 100a, and thus, the description thereof will not be repeated.

Fig. 5 is a top view showing a semiconductor device 100d, according to some embodiments. The semiconductor device 100d of fig. 5 differs from the semiconductor device 100b of fig. 3 in the shape of the field plate.

According to some embodiments, as shown in fig. 5, similar to the semiconductor device 100c of fig. 4A, the field plate 129 of the semiconductor device 100d includes a first field plate region 129a, a second field plate region 129b, and a third field plate region 129 c. In some embodiments, the first, second, and third

field plate regions

129a, 129b, and 129c are disposed between the gate metal layer 125 and the drain electrode 119 and are physically separated from each other. Therefore, the electric field near the drain electrode 119 can be reduced compared to the semiconductor device 100b of fig. 3, thereby reducing or delaying the occurrence of breakdown.

Further, in the present embodiment, the conductive structure 150d1 electrically connecting the first field plate region 129a to the composite substrate 106 is disposed under the first field plate region 129a, the conductive structure 150d2 electrically connecting the second field plate region 129b to the composite substrate 106 is disposed under the second field plate region 129b, the conductive structure 150d3 electrically connecting the third field plate region 129c to the composite substrate 106 is disposed under the third field plate region 129c, and the conductive structures 150d1, 150d2, and 150d3 are located in ranges directly below the first, second, and third

field plate regions

129a, 129b, and 129c, respectively.

Specifically, the projection of the conductive structure 150d1 on the top surface of the composite substrate 106 falls within the projection of the first field plate region 129a on the top surface of the composite substrate 106, the projection of the conductive structure 150d2 on the top surface of the composite substrate 106 falls within the projection of the second field plate region 129b on the top surface of the composite substrate 106, and the projection of the conductive structure 150d3 on the top surface of the composite substrate 106 falls within the projection of the third field plate region 129c on the top surface of the composite substrate 106. The processes and materials of the conductive structures 150d1, 150d2 and 150d3 may be similar or identical to those of the conductive structure 150a, and thus, the description thereof will not be repeated.

Two conductive structures 150d1, two conductive structures 150d2, and two conductive structures 150d3 are shown in fig. 5, however, the number of conductive structures 150d1, 150d2, and 150d3 may not be limited thereto. For example, any of the conductive structures 150d1, any of the conductive structures 150d2, and any of the conductive structures 150d3 may be omitted in the semiconductor device 100 d. The processes and materials of other components in the semiconductor device 100d may be similar or identical to those of the semiconductor device 100a, and thus, the description thereof will not be repeated.

Fig. 6A is a perspective view showing a semiconductor device 100e according to some embodiments, and fig. 6B is a schematic cross-sectional view showing the semiconductor device 100e according to some embodiments, wherein fig. 6B is a schematic cross-sectional view of the semiconductor device 100e along the line X1-X2 in fig. 6A.

In the semiconductor device 100e, according to some embodiments, the first compound III-V semiconductor layer 107 includes a base 107 ' and a plurality of fin structures 107 ″ protruding from the base 107 ', and the second III-V semiconductor layer 109 conformally overlies the base 107 ' and the fin structures 107 ″. The source electrode 117 and the drain electrode 119 of the semiconductor device 100e are located on the first compound III-V semiconductor layer 107 and on opposite sides of the gate structure 111. It is noted that the field plate 129 includes a first field plate region 129a and a second field plate region 129b that respectively cover two adjacent fin structures 107 ″.

In some embodiments, the first and second

field plate regions

129a and 129b do not extend to the top surface 107's of the pedestal 107'. In addition, the first field plate region 129a and the second field plate region 129b may be electrically connected to the composite substrate 106 outside the active region (i.e., the region between the source electrode 117 and the drain electrode 119), for example, by the provision of the aforementioned conductive structure, ring structure and/or via. The processes and materials of the components in the semiconductor device 100e may be similar or identical to those of the components in the semiconductor device 100a, and thus, the description thereof will not be repeated.

Fig. 7A is a perspective view showing a semiconductor device 100f according to some embodiments, and fig. 7B is a schematic cross-sectional view showing the semiconductor device 100f according to some embodiments, wherein fig. 7B is a schematic cross-sectional view of the semiconductor device 100f along the line X1-X2 in fig. 7A. The semiconductor device 100f differs from the semiconductor device 100e in the arrangement position of the field plate.

In the semiconductor device 100f, the field plate 129 includes a first field plate region 129a, a second field plate region 129b, and a third field plate region 129c located between the fin structures 107 ". Specifically, the first, second, and third

field plate regions

129a, 129b, and 129c cover the top surface 107's of the pedestal 107' and do not cover the fin structure 107 ″.

In addition, similar to the semiconductor device 100e, the first field plate region 129a, the second field plate region 129b and the third field plate region 129c may be electrically connected to the composite substrate 106 outside the active region, for example, by the provision of the aforementioned conductive structures, ring structures and/or vias. The processes and materials of other components in the semiconductor device 100f may be similar or identical to those of the semiconductor device 100a, and thus, the description thereof will not be repeated.

Fig. 8A is a perspective view showing a semiconductor device 100g according to some embodiments, and fig. 8B is a schematic cross-sectional view showing the semiconductor device 100g according to some embodiments, wherein fig. 8B is a schematic cross-sectional view of the semiconductor device 100g along the line X1-X2 in fig. 8A. The semiconductor device 100g differs from the semiconductor device 100e in the arrangement position of the field plate.

The semiconductor device 100g includes a field plate 129 disposed on the second III-V semiconductor layer 109. Specifically, the field plate 129 covers the top surface 107's of the pedestal 107' and the plurality of fin structures 107 ". In addition, similar to the semiconductor device 100e, the field plate 129 can be electrically connected to the composite substrate 106 outside the active region, for example, by the provision of conductive structures, ring structures, and/or vias as described above. The processes and materials of other components in the semiconductor device 100g may be similar or identical to those of the semiconductor device 100a, and thus, the description thereof will not be repeated.

Embodiments of semiconductor devices, such as High Electron Mobility Transistors (HEMTs), and embodiments of methods of forming the same are provided. In some embodiments, the field plate is electrically connected to the composite substrate having a high thermal conductivity by providing a conductive structure through the second III-V semiconductor layer and the first composite III-V semiconductor layer, thereby achieving the objectives of reducing an electric field and dissipating heat simultaneously, and further improving the operating performance of the high current density semiconductor device.

In addition, the conductive structure is arranged at a position far away from the active region between the source electrode and the drain electrode, so that the semiconductor device can be prevented from being damaged. Furthermore, the conductive structure does not extend to the back side of the composite substrate and does not extend to the right under the active region, so that the high breakdown voltage of the semiconductor device can be maintained, and the applicable voltage range of the semiconductor device is not limited.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising:

a first compound III-V semiconductor layer disposed on a compound substrate;

a second III-V semiconductor layer disposed on the first compound III-V semiconductor layer;

a gate structure disposed on the second III-V semiconductor layer;

a source electrode and a drain electrode disposed on the second III-V semiconductor layer and on opposite sides of the gate structure;

a field plate disposed between the gate structure and the drain electrode; and

a conductive structure passing through the second III-V semiconductor layer and the first compound III-V semiconductor layer, wherein the field plate is electrically connected to the compound substrate by the conductive structure and the conductive structure is electrically isolated from the source electrode by a dielectric layer.

2. The semiconductor device of claim 1, wherein a bottom surface of the conductive structure is higher than a bottom surface of the composite substrate.

3. The semiconductor device of claim 1, wherein the first compound III-V semiconductor layer comprises gallium nitride, the second III-V semiconductor layer comprises aluminum gallium nitride, and the gate structure comprises P-type doped gallium nitride.

4. The semiconductor device of claim 1, wherein said conductive structure and said gate structure are located on opposite sides of said source electrode.

5. The semiconductor device of claim 1, wherein said conductive structure is located in a region directly below said field plate.

6. The semiconductor device of claim 1, wherein the composite substrate comprises:

a substrate;

a buffer layer disposed on the substrate; and

a seed layer disposed on the buffer layer, wherein the conductive structure passes through the buffer layer and the seed layer, and the conductive structure contacts the substrate.

7. The semiconductor device of claim 6, wherein said substrate is made of aluminum nitride.

8. A semiconductor device, comprising:

a first compound III-V semiconductor layer disposed on a compound substrate;

a source electrode, a gate structure and a drain electrode disposed on the second III-V semiconductor layer, wherein the gate structure is located between the source electrode and the drain electrode;

a first field plate region disposed between the gate structure and the drain electrode; and

and a first conductive structure electrically connected to the first field plate region and the composite substrate, wherein the first conductive structure is electrically isolated from the source electrode.

9. The semiconductor device of claim 8, further comprising:

a via hole disposed on the first field plate region, wherein the top surface of the first conductive structure is higher than the top surface of the first field plate region, and the first field plate region is electrically connected to the first conductive structure via the via hole.

10. The semiconductor device of claim 8, wherein the composite substrate comprises:

an aluminum nitride substrate;

an oxide layer disposed on the aluminum nitride substrate; and

and a silicon layer disposed on the oxide layer, wherein the first conductive structure penetrates through the oxide layer and the silicon layer, and the bottom surface of the first conductive structure is higher than the bottom surface of the aluminum nitride substrate.

11. The semiconductor device of claim 8, further comprising:

a second field plate region and a third field plate region disposed between the gate structure and the drain electrode, wherein the first field plate region, the second field plate region and the third field plate region are separated from each other;

a first via hole disposed on the first field plate region;

a second via hole disposed on the second field plate region; and

a third via hole disposed on the third field plate region, wherein the first, second and third field plate regions are electrically connected to the first conductive structure through the first, second and third via holes, respectively, and the first and gate structures are located on opposite sides of the source electrode.

12. The semiconductor device of claim 8, further comprising:

a second field plate region and a third field plate region disposed between the gate structure and the drain electrode, wherein the first field plate region, the second field plate region and the third field plate region are separated from each other; and

and the first conductive structure, the second conductive structure and the third conductive structure are respectively positioned in the ranges right below the first field plate area, the second field plate area and the third field plate area.

13. The semiconductor device of claim 8, wherein the first compound III-V semiconductor layer comprises a pedestal and a fin structure protruding from the pedestal, and the first field plate region covers the fin structure.

14. The semiconductor device of claim 8, wherein the first compound III-V semiconductor layer comprises a base and a plurality of fin structures protruding from the base, the first field plate region being between the fin structures and covering the base.

15. A method of forming a semiconductor device, comprising:

forming a first compound III-V semiconductor layer on a compound substrate;

forming a second group III-V semiconductor layer on the first compound group III-V semiconductor layer;

forming a source electrode, a gate structure and a drain electrode on the second III-V semiconductor layer, wherein the gate structure is located between the source electrode and the drain electrode;

forming a field plate between the gate structure and the drain electrode; and

forming a conductive structure through the second III-V semiconductor layer and the first compound III-V semiconductor layer, wherein the field plate is electrically connected to the compound substrate by the conductive structure and the conductive structure is electrically isolated from the source electrode.

16. The method of claim 15, wherein forming the conductive structure comprises:

removing a portion of the second III-V semiconductor layer and a portion of the first compound III-V semiconductor layer to form a first trench prior to forming the source electrode and the drain electrode;

filling polysilicon material in the first trench to form a first conductive portion of the conductive structure; and

a first dielectric layer is formed overlying the first conductive portion.

17. The method of claim 16, wherein forming the conductive structure comprises:

forming a second conductive portion of the conductive structure on the first conductive portion, wherein the second conductive portion and the source electrode are made of the same material in the same process.

18. The method of claim 17, wherein forming the conductive structure comprises:

forming a second dielectric layer on the field plate;

removing a portion of the second dielectric layer to form an opening on the field plate and a second trench exposing the second conductive portion; and

filling a metal material in the second trench and the opening to form a third conductive portion of the conductive structure on the second conductive portion and a via hole on the field plate, wherein the field plate is electrically connected to the conductive structure through the via hole.

19. The method of claim 15, wherein the composite substrate comprises an aluminum nitride substrate, and the conductive structure extends into the composite substrate and contacts the aluminum nitride substrate.

20. The method of claim 15, wherein said conductive structure does not extend directly under said source electrode.