TWI732239B - Semiconductor structure and method for forming the same - Google Patents

Abstract

A semiconductor structure includes a substrate structure having a plurality of first trenches extending in a first direction, a nucleation layer disposed on the substrate structure, a compound semiconductor layer disposed on the nucleation layer, a gate disposed on the compound semiconductor layer, and a source and a drain disposed on the compound semiconductor layer and at the opposite sides of the gate.

Description

Semiconductor structure and its forming method

The present invention relates to a semiconductor technology, in particular to a semiconductor structure having a compound semiconductor layer and a method of forming the same.

GaN-based semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterogeneous interface structures. ).

However, in the operation of a thinned high electron mobility transistor (HEMT) device, if a high voltage is applied, the depletion region is easily expanded and the silicon substrate under the epitaxial layer is turned on, which will cause substrate breakdown (substrate breakdown). ). In the prior art, it is difficult to achieve a good balance between the thinning of the high electron mobility transistor element and the break down voltage.

With the development of gallium nitride-based semiconductor materials, these semiconductor devices using gallium nitride-based semiconductor materials are used in more severe working environments, such as higher frequency, higher temperature, or higher voltage. Therefore, semiconductor devices with gallium nitride-based semiconductor materials still need to be further improved to overcome the challenges they face.

Some embodiments of the present invention provide a semiconductor structure including: a substrate structure having a plurality of first trenches extending along a first direction, a nucleation layer on the substrate structure, and a compound on the nucleation layer The semiconductor layer, the gate located on the compound semiconductor layer, and the source and drain located on the compound semiconductor layer and on both sides of the gate.

Some embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate structure; performing an etching step to form a plurality of first trenches extending along a first direction in the substrate structure; On the substrate structure; forming a compound semiconductor layer on the nucleation layer; and forming a gate, a source and a drain on the compound semiconductor layer, wherein the source and the drain are located on both sides of the gate.

Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. If it is mentioned in the description that the first part is formed on the second part, it may include an embodiment in which the first and second parts are in direct contact, or may include additional parts formed between the first and second parts, so that the first An embodiment in which the second component is not in direct contact. In addition, the embodiments of the present invention may use repeated component symbols in many examples. These repetitions are only for the purpose of simplification and clarity, and do not represent a specific relationship between the various embodiments and/or configurations discussed.

Furthermore, related terms in space, such as "above", "below", "above...", "below..." and similar terms, in addition to the orientation shown in the diagram, also Contains the different orientations of the device in use or operation. When the device is turned to other orientations (rotated by 90 degrees or other orientations), the relative description of the space used here can also be interpreted according to the rotated orientation.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, without specifying "about", "approximately", "approximately", "about", "approximately" and "approximately" can still be implied. The meaning of "probably".

Although the components in some of the described embodiments are described in a specific order, these descriptions can also be performed in other logical orders. Other components can be added to the semiconductor structure in the embodiment of the present invention. In different embodiments, some components may be replaced or omitted.

The semiconductor structure provided by the embodiment of the present invention includes a plurality of trenches extending along a specific direction in the substrate structure formed under the compound semiconductor layer. With the above-mentioned trench configuration, a hiatus can be formed when the space charge in the active region of the semiconductor structure extends vertically to the conductive layer (such as the silicon layer) in the substrate structure, so that The substrate does not conduct in the lateral direction to avoid substrate breakdown, thereby increasing the breakdown voltage, so as to allow the thinner semiconductor structure to be applied to high-voltage operation.

FIGS. 1-7 are schematic cross-sectional views illustrating various stages of forming the semiconductor structure 100 shown in FIG. 7 according to some embodiments of the present invention. Referring to Figure 1, a substrate structure 110 is provided. In some embodiments, the substrate structure 110 is a silicon on insulator (SOI) substrate, which includes a substrate 111, an insulating layer 112 formed on the substrate 111, and a silicon layer 113 formed on the insulating layer 112. In other embodiments, the substrate structure 110 may also be a bulk silicon substrate (not shown). In some embodiments, the substrate structure 110 may also be a QST ^TM substrate; here, the QST ^TM substrate refers to a substrate produced by Qromis Technology, Inc. in the United States.

In some embodiments, the substrate 111 can be a doped (for example, doped with p-type or n-type dopants) or an undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or the like The semiconductor substrate. In other embodiments, the substrate 111 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide substrate (Al ₂ O ₃ ) (or called a sapphire (Sapphire) substrate) or others. Similar base. In some embodiments, the thickness of the substrate 111 may range from about 300 microns to about 1200 microns, for example, about 750 microns.

The insulating layer 112 disposed on the substrate 111 is a high-quality film with good thermal stability at high temperatures. In some embodiments, the insulating layer 112 is a high-quality silicon oxide insulating layer made of, for example, tetraethoxysilane (TEOS). In other embodiments, the insulating layer 112 is a dielectric layer formed by plasma-enhanced chemical vapor deposition (PECVD), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide , Other similar materials or a combination of the foregoing. According to some embodiments of the present invention, the insulating layer 112 can provide a higher-quality surface to facilitate subsequent formation of other layers of the semiconductor structure on the surface. In some embodiments, the thickness of the insulating layer 112 may range from about 0.5 microns to about 3 microns, for example, about 2 microns.

According to some embodiments of the present invention, the top surface of the silicon layer 113 disposed on the insulating layer 112 includes a (111) silicon crystal plane or a (110) silicon crystal plane. Specifically, those skilled in the art to which the present invention pertains can understand that a crystalline semiconductor material (such as silicon) includes a plurality of atoms arranged in a three-dimensional structure, and such a three-dimensional structure includes a plurality of faces, and each face has Each crystal orientation expressed by Miller index. On the other hand, in the embodiment where the substrate structure 110 is a bulk silicon substrate, the top surface of the substrate structure 110 includes a (111) silicon crystal plane or a (110) silicon crystal plane.

Next, referring to FIG. 2, a patterning process is performed to form a plurality of trenches 114 in the substrate structure 110 (such as the silicon layer 113). The patterning process may include a photolithography process and an etching process. In some embodiments, the depth of the trench 114 can be controlled by adjusting the conditions of the etching process (for example, etching time, etching rate, concentration of etching chemicals, etc.). The photolithography process can include, for example, photoresist coating (such as spin-coating), soft baking, exposure pattern, post-exposure baking, photoresist development, and cleaning. And drying (such as hard baking), other suitable manufacturing processes, or a combination of the above. The above-mentioned etching process may be a wet etching process, a dry etching process, other suitable etching processes (such as reactive ion etching (RIE)), or a combination of the foregoing. In some embodiments, a patterned photoresist layer (not shown) is formed on the substrate structure 110 by a photolithography process, and the substrate structure 110 is etched through a plurality of openings (not shown) of the patterned photoresist layer The step is to form a plurality of trenches 114 in the substrate structure 110.

Continue to refer to FIG. 2 in conjunction with the top view of the exemplary semiconductor structure depicted in FIG. 9A. In some embodiments. The semiconductor structure 100 shown in FIG. 2 may correspond to the cross-section A-A' shown in FIG. 9A. It should be noted that, in order to briefly describe the embodiment of the present invention and highlight its features, not all the structures of the semiconductor structure 100 are shown in FIG. 9A. In some embodiments, as shown in FIG. 9A, the plurality of trenches 114 formed in the substrate structure 110 through the patterning process described above extend along the first direction. In other words, in the top view, the long axes of the plurality of grooves 114 are parallel to the above-mentioned first direction. According to some embodiments of the present invention, the above-mentioned first direction may be the process used to identify the crystal orientation of a wafer formed by the Czochralski process or the floating zone process. The direction of the notch. According to other embodiments of the present invention, the above-mentioned first direction may be the >1-10> crystal orientation of the silicon layer 113, and the direction of the notch 901 may be parallel to the >1-10> crystal orientation of the silicon layer 113, but the present invention The extending direction of the trench 114 provided by the embodiment is not limited thereto.

Through the above-mentioned multiple trenches extending in a specific direction (such as the direction of the score and/or the >1-10> crystal orientation of the silicon layer 113) in the substrate structure under the compound semiconductor layer, the active area of the semiconductor structure can be When the space charge vertically expands and extends to the conductive layer (such as the silicon layer) in the substrate structure, a cross-section is formed, so that the substrate structure is laterally non-conductive to avoid substrate breakdown.

Continue to refer to FIG. 2 in conjunction with the top view of the exemplary semiconductor structure depicted in FIG. 9B. It should be noted that, in order to briefly describe the embodiment of the present invention and highlight its features, not all the structures of the semiconductor structure 100 are shown in FIG. 9B. In some embodiments, the patterning process described above can simultaneously form a plurality of trenches 114 extending along a first direction and a plurality of trenches 914 extending along a second direction different from the first direction. As shown in FIG. 9B, the extending direction of the trench 114 (ie, the first direction) is perpendicular to the extending direction of the trench 914 (ie, the second direction). However, the embodiment of the present invention is not limited to this. The angle between the first direction and the second direction can be adjusted according to the product design, for example, it can be 30 degrees, 45 degrees, 80 degrees (not shown), or other angles.

By simultaneously forming a plurality of first trenches 114 extending along the first direction and a plurality of second trenches 914 extending along the second direction, the vertical expansion of space charges in the active region of the semiconductor structure can be more effectively blocked And it extends to the conductive layer in the substrate structure to conduct conduction, so as to avoid the breakdown of the substrate and improve the effect of stress relief.

Next, referring to FIG. 3, a nucleation layer 120 is conformably formed on the substrate structure 110 (for example, the silicon layer 113). In some embodiments, the material of the nucleation layer 120 may be aluminum nitride (AlN). In other embodiments, the nucleation layer 120 can be made of other semiconductor materials such as doped silicon carbide (for example, doping silicon carbide with nitrogen or phosphorus can form an n-type semiconductor, and doping with aluminum, boron, gallium or beryllium) P-type semiconductor), III-V (III-V) compound semiconductor materials, or other similar materials. In some embodiments, the nucleation layer 120 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), Molecular beam epitaxy (MBE), a combination of the foregoing, or similar methods are compliantly formed on the substrate structure 110.

It is worth noting that although FIG. 3 only shows the nucleation layer 120 formed on the top surface of the substrate structure 110, in some embodiments, the nucleation layer 120 formed on the substrate structure 110 can also be formed at the same time. On the sidewall surface of the trench 114 (not shown), the thickness of the nucleation layer 120 formed on the sidewall surface of the trench 114 is not sufficient to fill the trench 114 and can substantially maintain the void volume in the trench 114.

4 to 6 are schematic cross-sectional views of various stages of forming the compound semiconductor layer 130 on the nucleation layer 120. In some embodiments, the compound semiconductor layer 130 may include a buffer layer 131 formed on the nucleation layer 120, a channel layer 132 formed on the buffer layer 131, a barrier layer 133 formed on the channel layer 132, and a barrier layer 133 formed on the channel layer 132. The cap layer 134 on the barrier layer 133.

The buffer layer 131 can slow down the strain of the channel layer 132 subsequently formed above the buffer layer 131 to prevent defects from being formed in the channel layer 132 above. The strain is caused by the mismatch between the channel layer 132 and the substrate structure 110. In some embodiments, the material of the buffer layer 131 may be AlN, GaN, Al _x Ga _1-x N (where 0>x>1), a combination of the foregoing, or other similar materials. The buffer layer 131 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or the like. According to some embodiments of the present invention, in the schematic cross-sectional view, the buffer layer 131 formed by the epitaxial growth process includes a discontinuous film layer (such as the first buffer layer 131A) and a continuous film sequentially stacked on the nucleation layer 120 Layer (for example, the second buffer layer 131B).

Referring to FIGS. 4 and 5, which illustrate cross-sectional schematic diagrams of epitaxial growth of the first buffer layer 131A and the second buffer layer 131B on the nucleation layer 120. In Figures 4 and 5, the first buffer layer 131A has a plurality of openings OP located above the plurality of trenches 114 to form a discontinuous film layer, wherein the width of the opening OP is smaller than the width of the trench 114 to facilitate continuous formation. The second buffer layer 131B is bonded on the first buffer layer 131A to form a smooth and continuous film layer.

It is worth noting that in the embodiment where the extending direction of the trench 114 (ie, the first direction) is parallel to the >1-10> crystal orientation of the silicon layer 113, the lattice structure of the buffer layer 131 and the substrate structure 110 is different. Due to the characteristics, the buffer layer 131 cannot be epitaxially grown on the sidewall of the trench 114, so that the void volume in the trench 114 can be substantially maintained at the original size. However, the buffer layer 131 grows laterally and upwardly on the top surface of the nucleation layer 120, thereby forming a discontinuous first buffer layer 131A that gradually adheres but still leaves a plurality of openings OP, and is completely bonded. A flat and continuous second buffer layer 131B is formed. In other embodiments, the buffer layer 131 will rapidly grow laterally, so that the discontinuous first buffer layer 131A does not exist, that is, there is no opening OP (as shown in the subsequent figures 8A, 8B, 8C, and 8D) Buffer layer 131).

In other embodiments, the step of epitaxially growing the buffer layer 131 can be performed by depositing a dielectric material in the trench 114 and/or the trench 914 and then performing a planarization step to prevent the buffer layer 131 from being deposited. The material is epitaxially grown in trench 114 and/or trench 914. In some embodiments, the dielectric material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (borophosphosilicate glass, BPSG), low-k dielectric materials, and/or other suitable dielectric materials. For example, spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma Chemical vapor deposition (high density plasma CVD, HDPCVD), other suitable methods, or a combination of the foregoing, deposit the above-mentioned dielectric material in the trench 114 and/or the trench 914.

According to the above embodiment, the extending direction of the trench is designed to be parallel to the >1-10> crystal orientation of the silicon layer 113, or when the extending direction of the trench is not parallel to the >1-10> crystal orientation of the silicon layer 113 Filling the trench with a dielectric material enables the subsequent formation of the compound semiconductor layer 130 while substantially maintaining the void volume in the trench, which can effectively block the vertical expansion of space charges in the active region of the semiconductor structure 100 and avoid The space charge extends to the substrate structure 110 or the conductive layer (such as the silicon layer 113) in the substrate structure 110 and conducts the substrate breakdown caused by the conduction.

Next, referring to FIG. 6, in some embodiments, the channel layer 132 may be a gallium nitride (GaN) layer, and the barrier layer 133 formed on the channel layer 132 may be an aluminum gallium nitride (AlGaN) layer. The gallium nitride layer and the gallium aluminum nitride layer may have dopants (for example, n-type dopants or p-type dopants) or no dopants. The cap layer 134 formed on the barrier layer 133 may be a III-V compound semiconductor material, which is used to passivate the surface of the material, so as to significantly suppress the current collapse effect and reduce the surface leakage current. The channel layer 132, the barrier layer 133, and the cap layer 134 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) ), the aforementioned combination or other similar methods. In some embodiments, the thickness of the formed channel layer 132 may range from about 10 nanometers to about 1 micrometer, for example, about 0.4 micrometers. The thickness of the barrier layer 133 may range from about 5 nanometers to about 30 nanometers, for example, about 25 nanometers. The thickness of the cap layer 134 may range from about 0.5 nanometers to about 10 nanometers, for example, about 2 nanometers.

According to some embodiments of the present invention, two-dimensional electron gas (2DEG) is formed on the hetero interface between the channel layer 132 and the barrier layer 133. The semiconductor structure 100 shown in the subsequent FIG. 7 is A high electron mobility transistor (HEMT) that uses a two-dimensional electron gas (2DEG) (or carrier channel 701) as a conductive carrier.

Next, referring to FIG. 7, the gate electrode 150 is formed on the compound semiconductor layer 130 (for example, the cap layer 134 ), and the source electrode 160 and the drain electrode 170 are on both sides of the gate electrode 150 to form the semiconductor structure 100. According to some embodiments of the present invention, the semiconductor structure 100 is a high electron mobility transistor (HEMT). In some embodiments, an optional doped compound semiconductor layer 140 may be included between the gate 150 and the cap layer 134, the details of which will be further described later.

In some embodiments, the materials of the gate 150, the source 160, and the drain 170 may be conductive materials, such as metals, metal nitrides, or semiconductor materials. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, the aforementioned combination or the aforementioned multilayer structure. The semiconductor material can be polycrystalline silicon or polycrystalline germanium. The aforementioned conductive material can be formed on the cap layer 134 by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods. Above, the gate electrode 150, the source electrode 160, and the drain electrode 170 are formed through a patterning process.

According to some embodiments of the present invention, before forming the gate 150, the doped compound semiconductor layer 140 may be formed on the cap layer 134 first, and then the gate 150 may be formed on the doped compound semiconductor layer 140. By disposing the doped compound semiconductor layer 140 between the gate 150 and the cap layer 134, the generation of two-dimensional electron gas (2DEG) under the gate 150 can be suppressed, so as to achieve the normally-off state of the semiconductor device 100. In some embodiments, the material of the doped compound semiconductor layer 140 may be p-type doped or n-type doped gallium nitride (GaN). The step of forming the doped compound semiconductor region 140 may include depositing a doped compound semiconductor layer (not shown) on the cap layer 134 by an epitaxial growth process and performing a patterning process on the doped compound semiconductor layer 140 to form a corresponding doped compound semiconductor layer 140 At the position where the gate 150 is scheduled to be formed.

It should be noted that the aspect of the gate structure of the semiconductor structure 100 provided by the embodiment of the present invention is not limited to this. For example, a metal-insulator-semiconductor gate (MIS-gate) ), recess gate, or fluorine-gate formed by doping fluorine ions in the barrier layer 133 under the gate 150, etc., can be designed according to different products It is applied to the semiconductor structure 100 provided by the embodiment of the present invention.

Continuing to refer to FIG. 7, according to some embodiments of the present invention, the vertical sidewalls of the trench 114 have a normal direction A, wherein the normal direction A is parallel to the carriers on the hetero interface between the channel layer 132 and the barrier layer 133 The direction of carrier flow in channel 701. On the other hand, in the embodiment where the extending direction (ie, the first direction) of the trench 114 is parallel to the >1-10> crystal orientation of the silicon layer 113, the normal direction of the vertical sidewalls of the trench 114 is parallel to the silicon layer 113 113 of >001> crystal orientation. In this embodiment, the carrier flow direction of the carrier channel 701 is also parallel to the >001> crystal orientation of the silicon layer 113.

In summary, through the above-mentioned arrangement of the relative positions of the trench 114 and the carrier channel 701, the trench 114 formed in the substrate structure 110 can effectively block the vertical expansion of the space charge SC in the active region of the semiconductor structure 100. It avoids the substrate breakdown caused by the space charge SC extending into the substrate structure 110 and is turned on, thereby increasing the breakdown voltage, and allowing the thinner semiconductor structure to be applied to high voltage operation.

8A, 8B, 8C, and 8D are schematic cross-sectional views of exemplary semiconductor structures 100A, 100B, 100C, and 100D, respectively, according to some embodiments of the present invention. As shown in FIGS. 8A, 8B, 8C, and 8D, the structure of the semiconductor structure 100A, 100B, 100C, and 100D is substantially similar to the semiconductor structure 100 shown in FIG. The trenches 114A, 114B, 114C, and 114D of different depths are formed by the conditions of the above-mentioned etching step (for example, etching time, etching rate, concentration of etching chemicals, etc.). It is worth noting that, in order to briefly describe the embodiment of the present invention and highlight its features, only the buffer layer 131 of a single film layer is shown in FIGS. 8A, 8B, 8C, and 8D. The semiconductor structures 100A, 100B, 100C, and 100D shown in FIGS. 8A, 8B, 8C, and 8D, respectively, may optionally include a dielectric material 801 filled in the trench.

Referring to FIG. 8A, the trench 114A in the substrate structure 110 of the semiconductor structure 100A partially penetrates the silicon layer 113 in the substrate structure 110. In some embodiments, the trench 114A has a depth D1, where the depth D1 is in the range of about 0.05 micrometers to about 0.2 micrometers, such as 0.1 micrometers. The trench 114A has a width W, where the width W is in the range of about 0.2 micrometers to about 6 micrometers, for example, 2 micrometers. The spacing S between the plurality of trenches 114A ranges from about 0.5 microns to about 10 microns, for example, 5 microns.

Referring to FIG. 8B, the trench 114B in the substrate structure 110 of the semiconductor structure 100B completely penetrates the silicon layer 113, so the bottom surface of the trench 114B and the bottom surface of the silicon layer 113 in the substrate structure 110 are substantially coplanar. In some embodiments, the trench 114B has a depth D2, where the depth D2 ranges from about 0.05 microns to about 0.4 microns, such as 0.2 microns. Referring to FIG. 8C, the trench 114C in the substrate structure 110 of the semiconductor structure 100C penetrates the silicon layer 113 and penetrates a part of the insulating layer 112 under the silicon layer 113. In other words, the bottom surface of the trench 114C is lower than the bottom surface of the silicon layer 113 in the substrate structure 110, and is located in the insulating layer 112 under the silicon layer 113. In some embodiments, the trench 114C has a depth D3, where the depth D3 is in the range of about 0.05 micrometers to about 2 micrometers, for example, 1 micrometer. Referring to FIG. 8D, the trench 114D in the substrate structure 110 of the semiconductor structure 100D penetrates the silicon layer 113 and the insulating layer 112, and passes through a part of the base 111 of the insulating layer 112. In other words, the bottom surface of the trench 114D is lower than the bottom surface of the insulating layer 112 in the substrate structure 110, and is located in the base 111 below the insulating layer 112. In some embodiments, the trench 114D has a depth D4, where the depth D4 is in the range of about 0.05 microns to about 8 microns, for example, 4 microns. It should be noted that the depth, width, and pitch of the trenches provided by the embodiments of the present invention are only exemplary, and the present invention is not limited thereto.

According to some embodiments of the present invention, trenches with different depths (for example, an aspect ratio ranging from about 0.01 to about 50, such as 10) formed by adjusting the conditions of the above-mentioned etching step, when the trenches in the substrate structure 110 The deeper the depth, the better the effect of stress relief, but it may also increase the cost of the etching process relatively. The depth, width, and pitch of the plurality of trenches extending in a specific direction in the substrate structure formed under the compound semiconductor layer included in the embodiment of the present invention can be adjusted according to the product design to achieve the effect of stress relief and process cost Balance between.

In summary, the semiconductor structure provided by the embodiments of the present invention is formed by forming a plurality of trenches extending along a specific direction (for example, >1-10> crystal orientation of the silicon layer) in the substrate structure under the compound semiconductor layer. The arrangement of the position opposite to the carrier channel can effectively block the vertical expansion of space charge in the active region of the semiconductor structure, and avoid the substrate breakdown caused by the conduction of the space charge extending to the conductive layer (such as the silicon layer) in the substrate structure. In turn, the breakdown voltage is increased to allow thinner semiconductor structures to be used in high-voltage operations.

Several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field of the present invention should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and replacements.

100, 100A, 100B, 100C, 100D: semiconductor structure 110: Substrate structure 111: Base 112: Insulation layer 113: Silicon layer 114, 114A, 114B, 114C, 114D, 914: groove 120: Nucleation layer 130: compound semiconductor layer 131: Buffer layer 131A: the first buffer layer 131B: second buffer layer 132 ~ Channel layer 133: Barrier Layer 134: cap layer 140 ~ Doped compound semiconductor layer 150: gate 160: Source 170: Dip pole 701: carrier channel 801: Dielectric material 901: nick A-A’: Section A: Direction D1, D2, D3, D4: depth OP: opening S: Spacing SC: Space charge W: width

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale and are only used for illustration and illustration. In fact, the size of the element may be arbitrarily enlarged or reduced to clearly show the characteristics of the embodiment of the present invention. FIGS. 1 to 7 are schematic cross-sectional views illustrating various stages of forming a semiconductor structure according to some embodiments of the present invention. FIG. 8A is a schematic cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present invention. FIG. 8B is a schematic cross-sectional view of an exemplary semiconductor structure according to another embodiment of the present invention. FIG. 8C is a schematic cross-sectional view of an exemplary semiconductor structure according to another embodiment of the present invention. FIG. 8D is a schematic cross-sectional view of an exemplary semiconductor structure according to another embodiment of the present invention. FIG. 9A is a top view of an exemplary semiconductor structure according to some embodiments of the present invention. FIG. 9B is a top view of an exemplary semiconductor structure according to other embodiments of the present invention.

100: semiconductor structure

110: Substrate structure

111: Base

112: Insulation layer

113: Silicon layer

114: groove

120: Nucleation layer

130: compound semiconductor layer

131: Buffer layer

131A: the first buffer layer

131B: second buffer layer

132: Channel layer

133: Barrier Layer

134: cap layer

140: doped compound semiconductor layer

150: gate

160: Source

170: Dip pole

701: carrier channel

A: Direction

A-A’: Section

OP: opening

SC: Space charge

Claims (23)

A semiconductor structure includes: a substrate structure, wherein the substrate structure includes a plurality of first trenches extending along a first direction, the substrate structure has an upper surface and a lower surface, and the first trenches are not Exposed on the lower surface; a nucleation layer located on the upper surface of the substrate structure; a compound semiconductor layer located on the nucleation layer; a gate electrode located on the compound semiconductor layer; and a source and a The drain is located on the compound semiconductor layer and on both sides of the gate. The semiconductor structure described in claim 1, wherein the substrate structure further includes: a base; an insulating layer on the base; and a silicon layer on the insulating layer, wherein the first trenches Located in the silicon layer. The semiconductor structure described in item 2 of the scope of patent application, wherein the substrate is a silicon substrate. The semiconductor structure described in item 2 of the scope of patent application, wherein the substrate is an aluminum nitride substrate, a silicon carbide substrate, or an aluminum oxide substrate. In the semiconductor structure described in item 2 of the scope of patent application, a top surface of the silicon layer includes a (111) silicon crystal plane or a (110) silicon crystal plane. The semiconductor structure described in claim 1 further includes a dielectric material filled in the first trenches. The semiconductor structure described in item 2 of the scope of patent application, wherein the semiconductor structure is a high electron mobility transistor, and the compound semiconductor layer includes: a first buffer layer located on the nucleation layer, wherein the cross-sectional view Wherein, the first buffer layer is a discontinuous film layer; a second buffer layer is located on the first buffer layer, wherein in the cross-sectional view, the second buffer layer is a continuous film layer; a channel layer is located On the second buffer layer; and a barrier layer on the channel layer, wherein a plurality of carrier channels are included between the channel layer and the barrier layer. The semiconductor structure described in item 7 of the scope of the patent application further includes a doped compound semiconductor layer, and the doped compound semiconductor layer is located between the gate and the barrier layer. According to the semiconductor structure described in claim 1, wherein the substrate structure further includes a plurality of second trenches extending along a second direction different from the first direction. The semiconductor structure described in item 2 of the scope of patent application, wherein the first direction is a <1-10> crystal orientation of the silicon layer. In the semiconductor structure described in claim 7, wherein a normal direction of the sidewalls of the first trenches is parallel to a <001> crystal orientation of the silicon layer. The semiconductor structure described in claim 11, wherein the carrier channels are parallel to the normal direction of the sidewalls of the first trenches. A method for forming a semiconductor structure includes: providing a substrate structure; performing an etching step to form a plurality of first trenches extending along a first direction In the substrate structure; conformally forming a nucleation layer on the substrate structure; forming a compound semiconductor layer on the nucleation layer; and forming a gate, a source and a drain on the compound semiconductor layer, The source and the drain are located on both sides of the gate. The method for forming a semiconductor structure as described in claim 13, wherein the substrate structure includes: a base; an insulating layer formed on the base; and a silicon layer formed on the insulating layer, wherein the etching The first trenches formed by the step are located in the silicon layer. According to the method for forming a semiconductor structure described in claim 14, wherein the first trenches formed by the etching step penetrate the silicon layer. According to the method for forming a semiconductor structure described in claim 14, wherein a top surface of the silicon layer includes a (111) silicon crystal plane or a (110) silicon crystal plane. According to the method for forming a semiconductor structure described in claim 13, wherein the etching step further includes forming a plurality of second trenches in the substrate structure extending along a second direction different from the first direction. According to the method for forming the semiconductor structure described in the scope of the patent application, the method further includes: depositing a dielectric material in at least one of the first trenches and the second trenches. The method of forming a semiconductor structure as described in item 18 of the scope of patent application further includes: After the step of depositing the dielectric material in at least one of the first trenches and the second trenches, a planarization step is performed. The method for forming a semiconductor structure as described in claim 14, wherein the semiconductor structure is a high electron mobility transistor, and the step of forming the compound semiconductor layer on the nucleation layer includes: forming a first buffer Layer on the nucleation layer, wherein in the cross-sectional view, the first buffer layer is a discontinuous film layer; forming a second buffer layer on the first buffer layer, wherein in the cross-sectional view, the second buffer layer The layers are joined as a continuous film layer; a channel layer is formed on the second buffer layer; and a barrier layer is formed on the channel layer, wherein a plurality of carrier channels are included between the channel layer and the barrier layer. According to the method for forming the semiconductor structure described in item 20 of the scope of the patent application, it further includes forming a doped compound semiconductor layer between the gate and the barrier layer. According to the method for forming a semiconductor structure described in claim 20, wherein the first direction is a <1-10> crystal orientation of the silicon layer. According to the method for forming a semiconductor structure as described in claim 22, wherein a normal direction of the sidewalls of the first trenches is parallel to a <001> crystal orientation of the silicon layer, and the carrier channels are parallel In the direction of the normal.

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