TW202040819A - Semiconductor structure - Google Patents

Abstract

A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed at the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and at the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias.

Description

Semiconductor structure

The present invention relates to a semiconductor structure, in particular to a semiconductor structure having a pair of via holes in contact with a seed layer.

GaN-based semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterogeneous interface structures. ).

However, in the operation of high electron mobility transistor (HEMT) devices, the lower epitaxial layer in the device structure contains many negatively charged impurities due to its material characteristics. At this time, if a high voltage is applied , These negative charges will be attracted toward the upper-layer components, and affect the operation of the upper-layer components. In order to solve this problem in the prior art, the silicon substrate under the epitaxial layer is usually grounded to discharge the negative charge of impurities. However, this method cannot be applied to various substrates.

With the development of gallium nitride-based semiconductor materials, these semiconductor devices using gallium nitride-based semiconductor materials are used in more severe working environments, such as higher frequency, higher temperature, or higher voltage. Therefore, semiconductor devices with gallium nitride-based semiconductor materials still need to be further improved to overcome the challenges they face.

Some embodiments of the present invention provide a semiconductor structure including: a substrate with active regions and isolation regions, an insulating layer on the substrate, a seed layer on the insulating layer, a compound semiconductor layer on the seed layer, and a compound semiconductor layer on the seed layer. The gate structure on the semiconductor layer and in the active region, the isolation structure on the substrate and in the isolation region, a pair of via holes in the isolation region and on both sides of the gate structure, on the substrate and in the gate The source structure and drain structure on both sides of the structure. The pair of via holes penetrate the isolation structure and contact the seed layer. The source structure and the drain structure are electrically connected to the seed layer through the pair of via holes respectively.

Some embodiments of the present invention provide a semiconductor structure comprising: a ceramic substrate having an active region and an isolation region, an insulating layer on the substrate, a seed layer on the insulating layer, and a seed layer on the seed layer The compound semiconductor layer, the gate structure on the compound semiconductor layer and in the active region, the source structure and the drain structure on the substrate and on both sides of the gate structure. The source structure and the drain structure are respectively electrically connected to the seed layer.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, and is not used to express the relationship between the different embodiments discussed.

In addition, words that are relative to space may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These space-relative terms are In order to facilitate the description of the relationship between one element or feature(s) and another element(s) or feature in the figure, these spatially relative terms include the different orientations of the device in use or operation, and the description in the figure The orientation. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, without specific description of "about", "approximately", "approximately", "about", "approximately" and "approximately" can still be implied. The meaning of "probably".

Although the components in some of the described embodiments are described in a specific order, these descriptions can also be performed in other logical orders. Other components can be added to the semiconductor structure in the embodiment of the present invention. In different embodiments, some components may be replaced or omitted.

The semiconductor structure provided by the embodiment of the present invention electrically connects the source structure and the drain structure in the semiconductor structure to the seed layer on the substrate through a pair of via holes located in the isolation region of the substrate. With the configuration of the above-mentioned via holes, a voltage difference (that is, the voltage difference between the source and the drain) can be generated inside the seed layer, so that the power lines extend to the film layer (such as the insulating layer) under the seed layer. The internal seed layer with voltage difference does not shield the power lines in the high electric field area of the semiconductor structure, thereby redistributing the electric field and increasing the breakdown voltage, so as to allow the semiconductor device to be applied to high voltage operation.

FIG. 1A is a schematic cross-sectional view of an exemplary semiconductor structure 100 according to some embodiments of the present invention. According to some embodiments of the present invention, the semiconductor structure 100 includes a substrate 200 having an active region 201 and an isolation region 202, an insulating layer 210 disposed on the substrate 200, a seed layer 220 disposed on the insulating layer 210, and a seed layer The compound semiconductor layer 230 on 220, the gate structure 300 disposed on the compound semiconductor layer 230 and located in the active region 210, the source structure 400 and the drain structure disposed on the substrate 200 and located on both sides of the gate structure 300 500, and a pair of via holes 601, 602 passing through the isolation structure 240 disposed in the isolation region 202.

In some embodiments, the substrate 200 may be a doped (for example, doped with p-type or n-type dopants) or an undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or the like The semiconductor substrate. In other embodiments, the substrate 200 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide substrate (Al ₂ O ₃ ) (or called a sapphire (Sapphire) substrate) or others. Similar base. The above ceramic substrate can be formed by high temperature sintering of ceramic powder by powder metallurgy.

The insulating layer 210 disposed on the substrate 200 is a high-quality film with good thermal stability at high temperatures. In some embodiments, the insulating layer 210 is a high-quality silicon oxide insulating layer made of, for example, tetraethoxysilane (TEOS). In other embodiments, the insulating layer 210 is a dielectric layer formed by plasma-enhanced chemical vapor deposition (PECVD), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide , Other similar materials or a combination of the foregoing. According to some embodiments of the present invention, the insulating layer 210 can provide a higher-quality surface to facilitate subsequent formation of other layers of the semiconductor structure on the surface. In some embodiments, the thickness of the insulating layer may range from about 0.5 microns to about 10 microns, such as about 2 microns.

In some embodiments, the material of the seed layer 220 formed on the insulating layer 210 may be silicon. In other embodiments, the seed layer 220 can be made of other semiconductor materials such as doped silicon carbide (for example, doping silicon carbide with nitrogen or phosphorus can form an n-type semiconductor, and doping with aluminum, boron, gallium or beryllium) P-type semiconductor), three-five group (III-V) compound semiconductor material, or other similar materials. In other embodiments, the seed layer 220 may include aluminum oxide (Al ₂ O ₃ ). In some embodiments, the seed layer 220 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), Molecular beam epitaxy (MBE), a combination of the foregoing, or similar methods are compliantly formed on the insulating layer 210.

In some embodiments, the compound semiconductor layer 230 formed on the seed layer 220 may include a buffer layer 231 disposed on the seed layer 220, a channel layer 232 disposed on the buffer layer 231, and a channel layer 232 disposed on the channel layer 232 The barrier layer 233.

The buffer layer 231 can slow down the strain of the channel layer 232 subsequently formed above the buffer layer 231 to prevent defects from being formed in the channel layer 232 above. The strain is caused by the mismatch between the channel layer 232 and the substrate 200. In some embodiments, the material of the buffer layer 231 may be AlN, GaN, Al _x Ga _1-x N (where 0<x<1), a combination of the foregoing, or other similar materials. The buffer layer 231 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or the like. In some embodiments, the thickness of the formed buffer layer 231 may range from about 0.5 microns to about 10 microns, for example, about 3 microns. It should be noted that although the buffer layer 231 has a single-layer structure in the embodiment shown in FIG. 1A, the buffer layer 231 may also have a multi-layer structure (not shown) in other embodiments.

According to some embodiments of the present invention, a two-dimensional electron gas (2DEG) (not shown) is formed on the hetero interface between the channel layer 232 and the barrier layer 233. The semiconductor structure 100 shown in FIG. 1A is a high electron mobility transistor (HEMT) that uses a two-dimensional electron gas (2DEG) as a conductive carrier. In some embodiments, the channel layer 232 may be a gallium nitride (GaN) layer, and the barrier layer 233 formed on the channel layer 232 may be an aluminum gallium nitride (AlGaN) layer, where the gallium nitride layer and the nitride The gallium aluminum layer may have dopants (for example, n-type dopants or p-type dopants) or no dopants. Both the channel layer 232 and the barrier layer 233 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing Or other similar methods. In some embodiments, the thickness of the formed channel layer 232 may range from about 300 nanometers to about 1 micrometer, for example, about 0.6 micrometers. In some embodiments, the thickness of the barrier layer 233 formed may range from about 5 nanometers to about 30 nanometers, for example, about 25 nanometers.

Next, according to some embodiments of the present invention, an isolation structure 240 may be formed in the compound semiconductor layer 230 of the substrate 200 to define the active region 201 and the isolation region 202. In some embodiments, as shown in FIG. 1A, the bottom surface of the isolation structure 240 may be located in the buffer layer 231 included in the compound semiconductor layer 230. In other embodiments, the bottom surface of the isolation structure 240 may be flush with the bottom surface of the buffer layer 231 and contact the seed layer 220 (not shown). In some embodiments, by forming the isolation structure 240, the two-dimensional electron gas (2DEG) formed on the hetero interface between the channel layer 232 and the barrier layer 233 can be isolated in the active region 201.

According to some embodiments of the present invention, the isolation structure 204 can be formed by destroying the crystal lattice structure of the compound semiconductor layer 230 at a predetermined position of the isolation structure 240, so that this part of the compound semiconductor layer 230 loses the piezoelectric effect ( piezoelectricity) and cannot conduct electricity. In these embodiments, nitrogen (N), oxygen (O), or other suitable elements can be implanted into the compound semiconductor layer 230 (for example, a gallium nitride layer) through an ion implantation process to The lattice structure is destroyed, so that the compound semiconductor layer 230 at a predetermined position of the isolation structure 240 is transformed into the isolation structure 240. In other embodiments, the material of the isolation structure 240 may be a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, similar materials, or a combination of the foregoing, and the trench isolation may be formed through an etching process and a deposition process Structure in the compound semiconductor layer 230.

Next, a gate structure 300 is formed on the compound semiconductor layer 230 (for example, the barrier layer 233) in the active region 201, a source structure 400 and a drain structure 500 are formed on both sides of the gate structure 300, and an inner layer is formed Electrical layers (such as the first dielectric layer 250, the second dielectric layer 260, and the third dielectric layer 270) are on the compound semiconductor layer 230 to form the semiconductor structure 100. According to some embodiments of the present invention, the semiconductor structure 100 is a high electron mobility transistor (HEMT). In some embodiments, the gate structure 300 includes a gate electrode 301 and a gate metal layer 302, wherein the gate electrode 301 is located on the barrier layer 233, and the gate metal layer 302 is located on the gate electrode 301 and is electrically connected to the gate electrode 301. connection. In other embodiments, an optional doped compound semiconductor layer 234 may be included between the gate electrode 301 and the barrier layer 233, the details of which will be further described later. The source structure 400 includes a source electrode 401, a source contact 402, and a source metal layer 403 that are electrically connected to each other, and the drain structure 500 includes a drain electrode 501, a drain contact 502, and a drain electrode 501 that are electrically connected to each other. And the drain metal layer 503. In some embodiments, the source electrode 401 and the drain electrode 501 located on both sides of the gate electrode 301 are both located in the active region 201 and pass through the barrier layer 233 to contact the channel layer 232.

In some embodiments, the material of the gate electrode 301 may be a conductive material, such as a metal, a metal nitride, or a semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, the combination of the foregoing, or the foregoing multilayers. The semiconductor material can be polycrystalline silicon or polycrystalline germanium. The aforementioned conductive material can be formed on the barrier layer by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods. On 233, the gate electrode 301 is formed through a patterning process.

According to some embodiments of the present invention, before forming the gate electrode 301, the doped compound semiconductor layer 234 may be formed on the barrier layer 233 first, and then the gate electrode 301 may be formed on the doped compound semiconductor layer 234. By disposing the doped compound semiconductor layer 234 between the gate electrode 301 and the barrier layer 233, the generation of two-dimensional electron gas (2DEG) under the gate electrode 301 can be suppressed to achieve the normally-off state of the semiconductor device 100. In some embodiments, the material of the doped compound semiconductor layer 234 may be p-type doped or n-type doped gallium nitride (GaN). The step of forming the doped compound semiconductor region 234 may include depositing a doped compound semiconductor layer (not shown) on the barrier layer 233 by an epitaxial growth process and performing a patterning process on it to form the doped compound semiconductor layer 234 Corresponds to the position where the gate electrode 301 is scheduled to be formed. In some embodiments, the thickness of the formed doped compound semiconductor layer 234 may range from about 50 nanometers to about 100 nanometers.

The source electrode 401 and the drain electrode 501 formed on both sides of the gate electrode 301 and located in the active region 201 comprise substantially the same material as the gate electrode 301, so they will not be repeated here. In some embodiments, as shown in FIG. 1A, the source electrode 401 and the drain electrode 501 pass through the barrier layer 233 and contact the channel layer 231.

In some embodiments, the gate metal layer 302, the source contact 402, the source metal layer 403, the drain contact 502, and the drain metal layer 503 can be formed by a deposition process and a patterning process. Contains conductive materials, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), Nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN) , Titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), metal oxide, metal alloy, other suitable conductive materials or a combination of the foregoing.

According to some embodiments of the present invention, as shown in FIG. 1A, the gate electrode 301 is buried in the first dielectric layer 250, and the gate metal layer 302 is buried in the first dielectric layer 250 and formed in the first dielectric layer. In the second dielectric layer 260 on the electrical layer 250. In addition, the source contact 402 and the drain contact 502 located on both sides of the gate structure 300 pass through the first dielectric layer 250 and the second dielectric layer 260 formed on the compound semiconductor layer 230 to respectively connect to the source The electrode 402 is in contact with the drain electrode 502, and the source metal layer 403 and the drain metal layer 503 are formed on the second dielectric layer 260 and electrically connected to the source contact 402 and the drain contact 502, respectively.

In some embodiments, the first dielectric layer 250 and the second dielectric layer 260 may respectively include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, and tetraethoxysilane. (tetraethoxysilane, TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials. Low-k dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, and amorphous carbon fluoride (fluorinated carbon), parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma Chemical vapor deposition (high density plasma CVD, HDPCVD), other suitable methods, or a combination of the foregoing, deposit the above-mentioned dielectric material on the compound semiconductor layer 230 (such as the barrier layer 233) and the isolation structure 240 to form a first dielectric The electrical layer 250 and the second dielectric layer 260.

According to some embodiments of the present invention, a pair of vias 601 and 602 included in the semiconductor structure 100 shown in FIG. 1A are disposed in the isolation region 202 and located on both sides of the gate structure 300. In some embodiments, the pair of vias may be through-GaN vias (TGV). The via holes 601 and 602 penetrate the second dielectric layer 206, the first dielectric layer 250, the isolation structure 240, and the buffer layer 231 located in the isolation region 202 to contact the seed layer 220. In the embodiment where the bottom surface of the isolation structure 240 directly contacts the seed layer 220, the vias 601, 602 passing through the isolation structure 240 may directly contact the seed layer 220 without passing through the buffer layer 231 (not shown). By arranging the vias 601, 602 in the isolation region 202, it is possible to prevent the vias 601, 602 from contacting the two-dimensional electron gas (2DEG) formed on the heterogeneous interface between the channel layer 232 and the barrier layer 233 to generate electricity Sexual abnormalities.

Referring to FIG. 1A, the source structure 400 and the drain structure 500 are electrically connected to the seed layer 220 through the via 601 and the via 602, respectively. Specifically, the source structure 400 is electrically connected to the seed layer 220 by contacting the source metal layer 403 and the via 601 across the active region 201 and the isolation region 202, and the drain structure 500 is electrically connected to the seed layer 220 by The drain metal layer 503 spanning the active region 201 and the isolation region 202 is in contact with the via 602 and is electrically connected to the seed layer 220. According to some embodiments of the present invention, the voltage difference generated inside the seed layer 220 electrically connected to the source structure 400 and the drain structure 500 may be substantially the same as the voltage between the source electrode 401 and the drain electrode 501 difference.

According to some embodiments of the present invention, the formation of the vias 601, 602 includes the compound semiconductor layer 230, the isolation structure 240, the first dielectric layer 250, and the second dielectric layer, which are first performed lithography and etching processes in the isolation region 202 260 to form a pair of holes (not shown) on both sides of the gate structure 300. Next, a conductive material is filled into the pair of holes to form via holes 601 and 602. In some embodiments, the conductive material can be selected from the aforementioned materials used to form the gate metal layer 302, the source contact 402, the source metal layer 403, the drain contact 502, and the drain metal layer 503. Therefore, I won't repeat it here. According to some embodiments of the present invention, the apertures of the via holes 601 and 602 may each be in the range of about 0.5 microns (micrometer, um) to about 5 microns. With the configuration of the via holes 601 and 602, a voltage difference (that is, the voltage difference between the source and the drain) can be generated inside the seed layer, so that the power line extends to the film layer (such as an insulating layer) below the seed layer , Thereby redistributing the electric field and increasing the breakdown voltage. In addition, applying the above-mentioned configuration of the vias 601 and 602 to a semiconductor device using a ceramic substrate can significantly improve its performance under high voltage operation.

Please refer to Figure 1B in conjunction. The semiconductor structure 100' shown in Figure 1B is substantially the same as the semiconductor structure 100 shown in Figure 1A. The difference lies in the vias 601, 602 further passes through the seed layer 220 and contacts the insulating layer 210. In some embodiments, the bottom surfaces of the vias 601 and 602 may be located in the insulating layer 210 (ie, as shown in FIG. 1B). In other embodiments, the bottom surfaces of the vias 601 and 602 can contact the top surface of the insulating layer 210 (not shown).

To sum up, with the configuration of the through holes 601 and 602 described above, a voltage difference (that is, the voltage difference between the source electrode 401 and the drain electrode 501) can be generated inside the seed layer 220, so that the power line extends to the crystal layer. The insulating layer 210 under the seed layer 220. The seed layer 220 with a voltage difference inside does not shield the lines of force in the high electric field regions of the semiconductor structures 100, 100' (for example, the compound semiconductor layer 230 located under the gate structure 300 in the active region 201), thereby redistributing the electric field. In this way, the insulating layer 210 in the semiconductor structure 100, 100' can withstand the applied voltage together with the compound semiconductor layer 230 formed on the insulating layer 210, thereby increasing the breakdown voltage to allow the semiconductor device 100 , 100' is used for high voltage operation.

It is worth noting that although only a pair of via holes 601 and 602 are shown here, the embodiment of the present invention may also include multiple pairs of via holes that are electrically connected to the source structure 400 and the seed layer 220 simultaneously and electrically connected. The drain structure 500 and the seed layer 220 (not shown). In other embodiments, the number of via holes electrically connecting the source structure 400 and the seed layer 220 may be different from the number of via holes electrically connecting the electrode structure 500 and the seed layer 220 (not shown).

According to some embodiments of the present invention, the semiconductor structure 100 shown in FIG. 1A may include a third dielectric layer 270 formed on the second dielectric layer 260, which covers the source metal layer 403 and the drain metal layer 503, and a metal layer 280 electrically connected to the source metal layer 403 and the drain metal layer 503 through the third dielectric layer 270. In some embodiments, the material of the third dielectric layer 270 can be selected from the aforementioned materials used to form the first dielectric layer 250 and the second dielectric layer 260, and the material and forming method of the metal layer 280 are substantially the same as the source. The electrode metal layer 403 and the drain metal layer 503 are not described here. It should be noted that although the embodiment of the present invention only illustrates a single-layer third dielectric layer 270 and a single-layer metal layer 280, the embodiment of the present invention is not limited thereto. The number of layers of the third dielectric layer 270 and the metal layer 280 can be adjusted according to product design.

According to some embodiments of the present invention, the semiconductor structure 100 shown in Figure 1A can have various configurations in the top view, for example, the semiconductor structures 100A, 100B shown in Figures 2A, 2B, and 2C , And 100C. For example, the semiconductor structure 100 shown in FIG. 1A may correspond to the cross-section A-A' shown in FIG. 2A, wherein the cross-section A-A' does not pass through the opening 700 of the seed layer 220 . In other embodiments, the seed layer 220 of the semiconductor structure 100 shown in FIG. 1A may not have openings (not shown).

FIG. 2A is a partial top view of an exemplary semiconductor structure 100A according to some embodiments of the present invention. It should be noted that in order to briefly describe the embodiment of the present invention and highlight its features, not all the structures of the semiconductor structure 100A are shown in FIG. 2A. 2A, the semiconductor structure 100A includes an active region 201, an isolation region 202 surrounding the active region 201, a gate structure 300 formed in the active region 210, a source structure 400, and a drain structure 500, which are formed in the isolation region 202 The via holes 601 and 602 in, and the seed layer 220 with a plurality of openings 700 in the active region 201. In some embodiments, the opening 700 of the seed layer 220 may expose the insulating layer 210 under the seed layer 220. According to some embodiments of the present invention, in the top view, the openings 700 located in the active area 201 may be arranged in a matrix, as shown in FIG. 2A. For example, the matrix may include five rows and five columns of aligned openings 700.

FIG. 2B is a partial top view of an exemplary semiconductor structure 100B according to another embodiment of the present invention. The semiconductor structure 100B shown in FIG. 2B is substantially similar to the semiconductor structure 100A shown in FIG. 2A, so it will not be repeated here. The difference between the semiconductor structure 100B and the semiconductor structure 100A is that the plurality of openings 700 of the seed layer 220 in the active region 201 in the semiconductor structure 100B are arranged alternately.

FIG. 2C is a partial top view of an exemplary semiconductor structure 100C according to another embodiment of the present invention. The semiconductor structure 100C shown in Fig. 2C is substantially similar to the semiconductor structures 100A and 100B shown in Figs. 2A and 2B, so it will not be repeated here. The difference between the semiconductor structure 100C and the semiconductor structures 100A and 100B is that the seed layer 220 located in the active region 201 in the semiconductor structure 100C has a plurality of elongated openings 800. As shown in Figure 2C, the long axis of the elongated openings 800 is parallel to the direction extending from the via 601 to the via 602, and the elongated openings 800 are located in the active area 201 along the direction of their short axis. arrangement.

According to some embodiments of the present invention, the plurality of openings of the seed layer 220 formed in the active region 201 can form a high impedance region to reduce the leakage current between the drain structure and the source structure. It is worth noting that the shape, number, size, and arrangement of the openings of the seed layer 220 shown in Figures 2A, 2B, and 2C are only exemplary. The configuration of the openings of the seed layer 220 can be The product design is adjusted, so the embodiment of the present invention is not limited to this.

In summary, the semiconductor structure provided by the embodiment of the present invention is configured to electrically connect the source structure and the drain structure to the seed layer with a pair of via holes, so that a voltage difference can be generated inside the seed layer. The power line can extend to the film layer (for example, the insulating layer) under the seed layer. According to the embodiment of the present invention, the seed layer with a voltage difference inside does not shield the lines of electric force in the high electric field region (for example, the compound semiconductor layer under the gate) in the semiconductor structure, thereby redistributing the electric field. In this way, the insulating layer in the semiconductor structure and the compound semiconductor layer formed on the insulating layer can withstand the applied voltage together, thereby increasing the breakdown voltage and improving the performance of the semiconductor structure.

The foregoing summarizes several embodiments so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can, without departing from the spirit and scope of the present invention, Make all kinds of changes, substitutions and replacements.

100, 100', 100A, 100B, 100C: semiconductor structure 200: substrate 201: active region 202: isolation region 210: insulating layer 220: seed layer 230: compound semiconductor layer 231: buffer layer 232: channel layer 233: barrier Layer 234: doped compound semiconductor layer 240: isolation structure 250: first dielectric layer 260: second dielectric layer 270: third dielectric layer 280: metal layer 300: gate structure 301: gate electrode 302: gate Metal layer 400: source structure 401: source electrode 402: source contact 403: source metal layer 500: drain structure 501: drain electrode 502: drain contact 503: drain metal layer 601, 602 : Via 700, 800: Opening A-A': Section

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale and are only used for illustration and illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention. 1A is a schematic cross-sectional view of an exemplary semiconductor structure according to some embodiments of the present invention. 1B is a schematic cross-sectional view of an exemplary semiconductor structure according to another embodiment of the present invention. FIG. 2A is a partial top view of an exemplary semiconductor structure according to some embodiments of the present invention. FIG. 2B is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention. FIG. 2C is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention.

100: semiconductor structure

200: base

201: Active Zone

202: Quarantine

210: insulating layer

220: seed layer

230: compound semiconductor layer

231: buffer layer

232: Channel layer

233: Barrier Layer

234: doped compound semiconductor layer

240: isolation structure

250: first dielectric layer

260: second dielectric layer

270: third dielectric layer

280: Metal layer

300: gate structure

301: gate electrode

302: gate metal layer

400: Source structure

401: source electrode

402: source contact

403: source metal layer

500: Drain structure

501: Drain electrode

502: Drain contact

503: Drain metal layer

601, 602: via hole

Claims (20)

A semiconductor structure includes: a substrate with an active region and an isolation region; an insulating layer on the substrate; a seed layer on the insulating layer; a compound semiconductor layer on the seed layer; A gate structure located on the compound semiconductor layer and located in the active region; an isolation structure located on the substrate and located in the isolation region; a pair of via holes located in the isolation region and located in the gate structure On both sides, the pair of vias pass through the isolation structure and contact the seed layer; and a source structure and a drain structure located on the substrate and on both sides of the gate structure, wherein the source structure The drain structure and the drain structure are respectively electrically connected to the seed layer through the pair of via holes. According to the semiconductor structure of claim 1, wherein the compound semiconductor layer includes: a buffer layer on the seed layer; a channel layer on the buffer layer and in the active region; and a barrier The layer is located on the channel layer and in the active area. In the semiconductor structure described in item 2 of the scope of patent application, the thickness of the insulating layer is in the range of 0.5 to 10 microns, the thickness of the buffer layer is in the range of 0.5 to 10 microns, and the thickness of the channel layer is in the range of 300 nanometers. The thickness of the barrier layer is in the range of 5 nanometers to 30 nanometers. The semiconductor structure described in item 1 of the scope of patent application further includes a dielectric layer on the compound semiconductor layer. According to the semiconductor structure described in claim 2, wherein the gate structure includes: a gate electrode layer located on the barrier layer; and a gate metal layer located on the gate electrode layer and connected to the The gate electrode layer is electrically connected. The semiconductor structure described in item 5 of the scope of the patent application further includes a doped compound semiconductor layer located between the gate electrode layer and the barrier layer. According to the semiconductor structure described in claim 1, wherein the pair of via holes further penetrate the seed layer and contact the insulating layer. The semiconductor structure described in claim 2, wherein the source structure includes: a source electrode located in the active region and passing through the barrier layer to contact the channel layer; a source contact located in The active region passes through the dielectric layer and contacts the source electrode; and a source metal layer is located on the dielectric layer and is electrically connected to one of the source contact and the pair of via holes. The semiconductor structure according to claim 8, wherein the drain structure includes: a drain electrode located in the active region and passing through the barrier layer to contact the channel layer; a drain contact located on In the active region and passing through the dielectric layer to contact the drain electrode; and a drain metal layer located on the dielectric layer and electrically connected to the drain contact and the other of the pair of vias . The semiconductor structure described in the first item of the patent application, wherein the seed layer includes silicon, silicon carbide, or aluminum oxide. According to the semiconductor structure described in the first item of the scope of the patent application, the apertures of the pair of via holes are each in the range of 0.5 micrometers to 5 micrometers. According to the semiconductor structure described in claim 1, wherein in the top view, the seed layer includes a plurality of openings located in the active region. According to the semiconductor structure described in claim 12, in the top view, the openings are arranged in a matrix. In the semiconductor structure described in claim 12, in the top view, the openings are arranged alternately. A semiconductor structure includes: a ceramic substrate with an active region and an isolation region; an insulating layer on the substrate; a seed layer on the insulating layer; a compound semiconductor layer on the seed layer A gate structure located on the compound semiconductor layer and located in the active region; and a source structure and a drain structure located on the substrate and on both sides of the gate structure, wherein the source structure and The drain structure is electrically connected to the seed layer. The semiconductor structure described in claim 15 further includes: an isolation structure located on the substrate and located in the isolation region; and a pair of via holes located in the isolation region and located in two of the gate structure Side, wherein the pair of via holes pass through the isolation structure and contact the seed layer, and the source structure and the drain structure are electrically connected to the seed layer through the pair of via holes, respectively. In the semiconductor structure described in claim 16, wherein the pair of via holes further penetrate the seed layer and contact the insulating layer. The semiconductor structure according to claim 15, wherein the compound semiconductor layer includes: a buffer layer on the seed layer; a channel layer on the buffer layer and in the active region; and a resistor The barrier layer is located on the channel layer and in the active area. According to the semiconductor structure described in claim 15, wherein the ceramic substrate is an aluminum nitride substrate, a silicon carbide substrate, or an alumina substrate. According to the semiconductor structure described in item 15 of the scope of patent application, in the top view, the seed layer includes a plurality of elongated openings located in the active region.

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