CN112038402A

CN112038402A - Semiconductor structure

Info

Publication number: CN112038402A
Application number: CN201910476359.9A
Authority: CN
Inventors: 林鑫成; 陈志谚; 黄嘉庆
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp; Vanguard International Semiconductor America
Priority date: 2019-06-03
Filing date: 2019-06-03
Publication date: 2020-12-04

Abstract

The present invention provides a semiconductor structure comprising: the semiconductor device comprises a substrate, a gate structure arranged on the substrate, a source electrode structure and a drain electrode structure which are positioned on two sides of the gate structure, and a first dielectric layer. The gate structure includes a gate electrode disposed on the substrate and a gate metal layer electrically connected to the gate electrode and acting as a gate field plate. The source structure comprises a source electrode arranged on the substrate and a first source metal layer which is electrically connected with the source electrode and extends along the direction from the gate electrode to the drain structure. The first dielectric layer is arranged on the grid metal layer. The first source metal layer has a potential different from that of the gate metal layer, and at least a portion of the first dielectric layer directly above the gate metal layer is exposed from the first source metal layer. The semiconductor structure provided by the embodiment of the invention has good balance between breakdown voltage and grid-drain capacitance, can effectively reduce switching loss, and further improves the efficiency of the semiconductor structure.

Description

Semiconductor structure

Technical Field

The present invention relates to semiconductor structures, and more particularly to semiconductor structures having field plates.

Background

Gallium nitride-based (GaN-based) semiconductor materials have many excellent material characteristics, such as high heat resistance, wide band-gap (band-gap), and high electron saturation rate. Therefore, the gallium nitride based semiconductor material is suitable for high speed and high temperature operation environment. In recent years, gallium nitride-based semiconductor materials have been widely used in Light Emitting Diode (LED) elements, high frequency elements such as High Electron Mobility Transistors (HEMTs) having a hetero interface structure, and the like.

In a High Electron Mobility Transistor (HEMT) device, a field plate structure is typically disposed in a high electric field region of a semiconductor device to reduce a peak electric field (peak electric field) of the high electric field region. One of the field plates is a field plate connected to the source electrode (i.e., a source field plate) which can reduce the gate-to-drain capacitance (Cgd), and the other is a field plate connected to the gate electrode (i.e., a gate field plate) which can reduce the electric field strength of the gate electrode on the drain side. However, the field plate structure is configured such that the gate-to-source capacitance (Cgs) is greatly increased, resulting in a severe switching loss.

With the development of gallium nitride-based semiconductor materials, these semiconductor devices using gallium nitride-based semiconductor materials are applied in more severe operating environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, there is still a need for further improvement of semiconductor devices having gallium nitride based semiconductor materials to overcome the challenges.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor structure, comprising: the semiconductor device comprises a substrate, a gate structure arranged on the substrate, a source electrode structure and a drain electrode structure which are arranged on the substrate and positioned on two sides of the gate structure, and a first dielectric layer arranged on a gate metal layer contained in the gate structure. The gate structure includes a gate electrode disposed on the substrate and a gate metal layer electrically connected to the gate electrode and acting as a gate field plate. The source structure comprises a source electrode arranged on the substrate and a first source metal layer which is electrically connected with the source electrode and extends along the direction from the gate electrode to the drain structure. The first source metal layer has a potential different from that of the gate metal layer, and at least a portion of the first dielectric layer directly above the gate metal layer is exposed from the first source metal layer.

Some embodiments of the present invention provide a semiconductor structure, comprising: the semiconductor device comprises a substrate, a gate structure arranged on the substrate, a source structure arranged on the substrate and a drain structure arranged on the substrate. The gate structure includes a gate electrode disposed on the substrate and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate. The source structure includes a source electrode disposed on the substrate and a first source metal layer electrically connected to the source electrode and acting as a source field plate. Wherein the first source metal layer has a different potential than the gate metal layer. In the top view, the first source metal layer has an opening directly above the gate metal layer.

The semiconductor structure provided by the embodiment of the invention has good balance between breakdown voltage and grid-drain capacitance, can effectively reduce switching loss, and further improves the efficiency of the semiconductor structure.

Drawings

The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.

Fig. 1 is a partial top view illustrating an exemplary semiconductor structure, in accordance with some embodiments of the present invention.

FIG. 2 is a cross-sectional view of a line A-A' corresponding to the semiconductor structure shown in FIG. 1, in accordance with some embodiments of the present invention.

FIG. 3 illustrates a partial top view of an exemplary semiconductor structure, in accordance with other embodiments of the present invention.

FIG. 4 is a cross-sectional view of a line B-B' of the semiconductor structure of FIG. 3 according to another embodiment of the present invention.

FIG. 5 illustrates a partial top view of an exemplary semiconductor structure, in accordance with other embodiments of the present invention.

FIG. 6 is a cross-sectional view of a line C-C' corresponding to the semiconductor structure shown in FIG. 5, according to another embodiment of the present invention.

FIGS. 7, 8, and 9 are partial top views illustrating exemplary semiconductor structures according to further embodiments of the present invention.

Reference numerals:

100. 300, 500, 700, 800, 900-semiconductor structure

101-substrate

110-compound semiconductor layer

111 buffer layer

112-channel layer

113 barrier layer

114-doped compound semiconductor layer

115. 116, 616 dielectric layer

116 ', 616' dielectric layer portions

120-grid structure

121-grid electrode

122-gate metal layer

130-source electrode structure

131-source electrode

132. 332, 532, 732, 832, 932-source metal layer

133 source contact

140-drain structure

141-drain electrode

142-Drain Metal layer

143 drain contact

A-A ', B-B', C-C ', D-D', E-E ', F-F' section plane (section line)

OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP 8-openings

W, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12-width

Detailed Description

Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structures. References in the specification to a first element being formed on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements are not in direct contact. In addition, embodiments of the present invention may use repeated reference numerals in many instances. These repetitions are merely for simplicity and clarity and do not represent a particular relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "above," "below," "… … above," "… … below," and the like, encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to other orientations (rotated 90 degrees or other orientations), then the spatially relative descriptors used herein should be interpreted as such with respect to the rotated orientation.

As used herein, the terms "about", "approximately", "substantial" and "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, i.e., the meanings of "about", "about" and "about" can be implied without specifying "about", "about" and "about".

The semiconductor structure provided by the embodiment of the invention reduces the risk of the high electric field of the grid structure by the grid field plate (grid field plate), optimizes the electric field distribution by the source field plate (source field plate), and effectively reduces the capacitance (C) from the grid to the drain electrode_gd) And reducing the gate-to-source capacitance (C) by adjusting the coverage of the source field plate to the gate field plate_gs) Further, the switching loss (switch loss) is reduced. Therefore, the semiconductor structure provided by the embodiment of the invention has a breakdown voltage (breakdown voltage) and a gate-to-drain capacitance (C)_gd) The switching loss can be effectively reduced by good balance between the two, and the efficiency of the semiconductor structure is further improved.

Fig. 1 illustrates a partial top view of an exemplary semiconductor structure 100, in accordance with some embodiments of the present invention. As shown in fig. 1, the semiconductor structure 100 includes a gate metal layer 122, a source metal layer 132, and a drain metal layer 142 disposed on a substrate 101. According to some embodiments of the invention, the source metal layer 132 has an opening OP1 located directly above the gate metal layer 122. In some embodiments, opening OP1 may be rectangular. It should be understood that not all elements of the semiconductor structure 100 are shown in fig. 1 for simplicity in describing embodiments of the present invention and in order to highlight the technical features thereof.

Please refer to fig. 2. Fig. 2 is a cross-sectional view of a line a-a' corresponding to the semiconductor structure 100 shown in fig. 1, according to some embodiments of the present invention. The semiconductor structure 100 includes a compound semiconductor layer 110 disposed over a substrate 101, a dielectric layer 115 disposed over the compound semiconductor layer 110, and a dielectric layer 116 disposed over the dielectric layer 115. The semiconductor structure 100 further includes a gate structure 120 disposed on the compound semiconductor layer 110, and a source structure 130 and a drain structure 140 disposed on two sides of the gate structure 120.

In some embodiments, the substrate 101 may be a doped (e.g., doped with a p-type or n-type dopant) or undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or similar semiconductor substrate. In some embodiments, the substrate 101 may be a semiconductor-on-insulator substrate, such as a Silicon On Insulator (SOI) substrate. In other embodiments, the substrate 101 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an alumina substrate (Al)₂O₃) (otherwise known as Sapphire (Sapphire) substrates) or other similar substrates.

As shown in fig. 2, the compound semiconductor layer 110 includes a buffer layer 111, a channel layer 112 disposed on the buffer layer 111, and a barrier layer 113 disposed on the channel layer 112. The buffer layer 111 may relieve strain (strain) of a channel layer 112 subsequently formed over the buffer layer 111 to prevent defects from forming in the channel layer 112 above. The strain is caused by the mismatch of the channel layer 112 and the substrate 101. In some casesIn an embodiment, the buffer layer 111 may be AlN, GaN, or Al_xGa_1-xN (wherein 0)<x<1) Combinations of the foregoing, or other similar materials. The buffer layer 111 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), combinations thereof, or the like. It is noted that although the buffer layer 111 is a single-layer structure in the embodiment shown in fig. 2, the buffer layer 111 may be a multi-layer structure (not shown) in other embodiments.

According to some embodiments of the present invention, a two-dimensional electron gas (2DEG) (not shown) is formed at the hetero-interface between the channel layer 112 and the barrier layer 113. The semiconductor structure 100 shown in fig. 2 is a High Electron Mobility Transistor (HEMT) using a two-dimensional electron gas (2DEG) as a conductive carrier. In some embodiments, the channel layer 112 may be a gallium nitride (GaN) layer, and the barrier layer 113 formed on the channel layer 112 may be an aluminum gallium nitride (AlGaN) layer, wherein the GaN layer and the aluminum gallium nitride layer may or may not have a dopant, such as an n-type dopant or a p-type dopant. Both channel layer 112 and barrier layer 113 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), combinations thereof, or the like.

With continued reference to fig. 2, next,

dielectric layers

115 and 116, a gate structure 120, and a source structure 130 and a drain structure 140 located at two sides of the gate structure 120 are formed on the compound semiconductor layer 110 by a deposition process and a patterning process. Specifically, in some embodiments, the gate structure 120 includes a gate electrode 121 and a gate metal layer 122 electrically connected to the gate electrode 121. In some embodiments, gate electrode 121 is disposed on barrier layer 113 and embedded in dielectric layer 115, and gate metal layer 122 is disposed on dielectric layer 115 and covered by dielectric layer 116. In other embodiments, an optional doped compound semiconductor layer 114 may be included between the gate electrode 12 and the barrier layer 113, the details of which will be described further below.

As shown in fig. 2, the source structure 130 includes a source electrode 131, a source contact 133, and a source metal layer 132. In some embodiments, source electrode 131 is embedded in dielectric layer 115 and source metal layer 132 is disposed on dielectric layer 116, wherein source electrode 131 and source metal layer 132 are electrically connected by source contact 133 embedded in dielectric layer 116. The potential of the source metal layer 132 electrically connected to the source electrode 131 is different from the potential of the gate metal layer 122 electrically connected to the gate electrode 121.

As shown in fig. 2, the drain structure 140 includes a drain electrode 141, a drain contact 143, and a drain metal layer 142. In some embodiments, the drain electrode 141 is embedded in the dielectric layer 115, and the drain metal layer 142 is disposed on the dielectric layer 116, wherein the drain electrode 141 and the drain metal layer 142 are electrically connected by a drain contact 143 embedded in the dielectric layer 116. In some embodiments, the source electrode 131 and the drain electrode 141 on both sides of the gate electrode 121 contact the channel layer 112 through the barrier layer 113.

According to some embodiments of the present invention, the gate metal layer 122 extending along the direction from the gate electrode 121 to the drain electrode 141 as a gate field plate can effectively reduce the risk of the gate structure being subjected to high electric fields. On the other hand, the source metal layer 132 extending along the direction from the gate electrode 121 to the drain electrode 141 as a source field plate can optimize the electric field distribution and effectively reduce the gate-to-drain capacitance (C)_gd)。

In some embodiments, the material of the gate electrode 121 may be a conductive material, such as a metal, a metal nitride, or a semiconductor material. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations thereof, or multi-layer structures thereof. The semiconductor material may be polysilicon or poly-germanium. The conductive material may be formed on the barrier layer 113 by, for example, Chemical Vapor Deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods, and then patterned to form the gate electrode 121.

According to some embodiments of the present invention, the doped compound semiconductor layer 114 may be formed on the barrier layer 113 before the gate electrode 121 is formed, and then the gate electrode 121 is formed on the doped compound semiconductor layer 114. By disposing the doped compound semiconductor layer 114 between the gate electrode 121 and the barrier layer 113, generation of a two-dimensional electron gas (2DEG) under the gate electrode 121 can be suppressed to achieve a normally-off state of the semiconductor device 100. In some embodiments, the material of the doped compound semiconductor layer 114 may be p-type doped or n-type doped gallium nitride (GaN). The step of forming the doped compound semiconductor layer 114 may include forming it at a position corresponding to a position where the gate electrode 121 is to be formed, by epitaxial growth and etch-back processes.

In some embodiments, the material of the source electrode 131 and the drain electrode 141 formed on both sides of the gate electrode 121 may be selected from the materials used to form the gate electrode 121. Moreover, the gate electrode 121 and the source electrode 131 and the drain electrode 141 on both sides thereof may be formed in the same process, and thus, the description thereof is omitted. In other embodiments, the gate electrode 121 and the source electrode 131 and the drain electrode 141 on both sides thereof may be formed in different processes.

In some embodiments, the gate metal layer 122, the source contact 133, the source metal layer 132, the drain contact 143, and the drain metal layer 142 may be formed by a deposition process and a patterning process, and the material of the material may include a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), silicon nitride (TaC), tantalum nitride (TaSiN), tantalum nitride (TaCN), titanium aluminide (TiAl), titanium nitride (TiAlN), a metal oxide, a metal alloy, other suitable conductive materials, or a combination thereof.

In some embodiments, the

dielectric layers

115, 116 may each comprise one or more single or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials. Low-k dielectric materials may include, but are not limited to, Fluorinated Silica Glass (FSG), Hydrogen Silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous carbon fluoride (fluorinated carbon), parylene, benzocyclobutene (BCB), or polyimide (polyimide). For example, the

dielectric layers

115, 116 may be formed by spin coating (spin coating), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma Chemical Vapor Deposition (HDPCVD), other suitable methods, or combinations thereof.

With continued reference to fig. 2. According to some embodiments of the present invention, dielectric layer 116 is located between gate metal layer 122 and source metal layer 132. The dielectric layer 116 covering the gate metal layer 122 has a dielectric layer portion 116' located directly above the gate metal layer 122 (i.e., in a normal direction of the substrate 101). Specifically, in the cross-sectional view of the semiconductor structure 100 shown in fig. 2, the dielectric layer portion 116' located directly above the gate metal layer 122 has two sides aligned with the gate metal layer 122. Referring to fig. 1, in the top view, the source metal layer 132 has an opening OP1 corresponding to the gate metal layer 122. Referring to fig. 2, in the cross-sectional view, the source metal layer 132 has an opening OP1 corresponding to the gate metal layer 122 and exposing the dielectric layer portion 116' directly above the gate metal layer 122. In this embodiment, the width W of the gate metal layer 122 (i.e., the width of the dielectric layer portion 116') is smaller than the width D1 of the opening OP 1. Opening OP1 does not completely expose dielectric layer portion 116', and source metal layer 132 and gate metal layer 122 partially overlap in projection on substrate 101.

According to some embodiments of the present invention, the method can be implementedThe gate-to-source capacitance (C) is reduced by increasing the size (e.g., width D1) of opening OP1 to reduce the coverage of the gate field plate (gate metal layer 122) by the source field plate (source metal layer 132)_gs) Further, the switching speed is increased to reduce the switching loss. It is noted that the coverage of the gate metal layer 122 by the source metal layer 132 provided in the embodiments of the present invention is merely exemplary, and can be adjusted according to the actual product design and the required switching speed.

Please refer to fig. 3 and fig. 4. Fig. 3 is a partial top view of an exemplary semiconductor structure 300 according to other embodiments of the present invention, and fig. 4 is a cross-sectional view of a line B-B' corresponding to the semiconductor structure 300 shown in fig. 3. It should be understood that not all of the elements of the semiconductor structure 300 shown in fig. 4 are shown in fig. 3 for the sake of simplicity in describing embodiments of the present invention and highlighting features thereof.

The semiconductor structure 300 illustrated in fig. 3 and 4 is substantially similar to the semiconductor structure 100 illustrated in fig. 1 and 2, respectively, except that the source metal layer 332 in the semiconductor structure 300 has a larger-sized opening OP 2.

As shown in the cross-sectional view of fig. 4, the width D2 of the opening OP2 of the source metal layer 332 is substantially equal to the width W of the gate metal layer 122 (i.e., the width of the dielectric layer portion 116'). In some embodiments, the opening OP2 completely exposes the dielectric layer portion 116', and the source metal layer 332 is aligned with the projection of the gate metal layer 122 on the substrate 101. In this embodiment, two sides of the opening OP2 are substantially aligned with two sides of the gate metal layer 122. In other embodiments, the width D2 of the opening OP2 of the source metal layer 332 is greater than the width W of the gate metal layer 122 (i.e., the width of the dielectric layer portion 116 ') (not shown), and the opening OP2 exposes the dielectric layer 116 beside the dielectric layer portion 116 ' except for completely exposing the dielectric layer portion 116 ', and the projection of the source metal layer 332 and the gate metal layer 122 on the substrate 101 does not overlap at all.

In the embodiment of fig. 4, the larger opening OP2 further reduces the coverage of the source field plate (source metal layer 332) with respect to the gate field plate (gate metal layer 122)Furthermore, the gate-to-source capacitance (C) can be further reduced_gs) Further, the switching speed is increased to reduce the switching loss. Therefore, the switching speed of the semiconductor structure 300 shown in fig. 3, 4 is greater than the switching speed of the semiconductor structure 100 shown in fig. 1, 2.

Please refer to fig. 5 and fig. 6. Fig. 5 is a partial top view of an exemplary semiconductor structure 500 according to other embodiments of the present invention, and fig. 6 is a cross-sectional view of a line C-C' corresponding to the semiconductor structure 500 shown in fig. 5. It should be understood that not all of the elements of the semiconductor structure 500 shown in fig. 6 are shown in fig. 5 for the sake of simplicity and clarity in describing embodiments of the present invention and highlighting features thereof.

The semiconductor structure 500 illustrated in fig. 5 and 6 is substantially similar to the semiconductor structure 300 illustrated in fig. 3 and 4, with the difference that the semiconductor structure 500 illustrated in fig. 5 and 6 further includes an additional source field plate. Specifically, the semiconductor structure 500 further includes a dielectric layer 616 disposed on the source metal layer 332 and the dielectric layer 116, and a source metal layer 532 disposed on the dielectric layer 616. In some embodiments, the source metal layer 532 may serve as an additional source field plate and be electrically connected to the source electrode 131 and the source metal layer 332 by the source contact 133. The source metal layers 332 and 532 electrically connected to the source electrode 131 have a different potential from the gate metal layer 122 electrically connected to the gate electrode 121.

As shown in fig. 6, the dielectric layer 616 is located between the source metal layer 332, the dielectric layer 116 and the source metal layer 532, wherein the dielectric layer 616 has a dielectric layer portion 616 'located directly above the gate metal layer 122 and the dielectric layer portion 116'. Specifically, in the cross-sectional view of the semiconductor structure 500 shown in fig. 6, the dielectric layer portion 616 'located directly above the gate metal layer 122 and the dielectric layer portion 116' has two sides aligned with the gate metal layer 122. In some embodiments, as shown in FIG. 6, the source metal layer 532 has an opening OP3 located directly above the dielectric layer portion 616 'and exposing the dielectric layer portion 616'. In this embodiment, the width W of the gate metal layer 122 (i.e., the width of the dielectric layer portions 116 ', 616') is greater than the width D3 of the opening OP 3. The opening OP3 does not completely expose the dielectric layer portion 616', and the source metal layer 532 and the projection of the gate metal layer 122 on the substrate 101 are partially overlapped.

In an embodiment of a semiconductor structure having a plurality of source field plates, in addition to adjusting the coverage of the source field plate (source metal layer 332) with respect to the gate field plate (gate metal layer 122), the coverage of the gate metal layer 122 with respect to each additional source metal layer directly above the gate metal layer 122 can be further adjusted to facilitate reducing the gate-to-source capacitance (C)_gs) Further, the switching speed is increased to reduce the switching loss. It should be noted that although only two source metal layers 332 and 532 with openings are illustrated in the embodiments of the present invention, the number of the source metal layers, the size of the openings included therein, and the coverage of the gate metal layer 122 can be adjusted according to the actual product design and the required switching speed, which is not limited in the present invention.

Fig. 7 is a partial top view illustrating an exemplary semiconductor structure 700, in accordance with further embodiments of the present invention. As shown in fig. 7, the semiconductor structure 700 includes a source metal layer 732 having an opening OP4 directly above the gate metal layer 122. In this embodiment, the opening OP4 is triangular in shape, and its width varies linearly along the length of the opening OP 4. In fig. 7, sectional lines D-D ', E-E', F-F 'in the length direction of the opening OP4 are drawn, respectively, wherein the directions of the sectional lines D-D', E-E ', F-F' are parallel to the flow direction of electrons. In this embodiment, the cross-sectional lines D-D ', E-E ', F-F ' may correspond to linearly varying widths D4, D5, D6, respectively, of the opening OP 4. In fig. 7, the widths D4, D5, D6 are all smaller than the width W of the gate metal layer 122, and the width D4 is greater than the width D5, and the width D5 is greater than the width D6. In the embodiment shown in fig. 7, the arrangement of the openings of the source metal layer can be adjusted according to the product design and the required switching speed, so that the coverage of the gate field plate by the source field plate is different in the cross-section of the semiconductor structure with different electron flow directions.

Furthermore, depending on product characteristics, the source field plate (source metal layer) may have two or more openings (e.g., as shown in fig. 8 and 9) with different sizes and/or shapes and located right above the gate field plate (gate metal layer), so that the coverage of the gate field plate by the source field plate is different in the cross-section of the semiconductor structure with different electron flow directions. Fig. 8 is a partial top view of an exemplary semiconductor structure 800, in accordance with further embodiments of the present invention. As shown in fig. 8, the semiconductor structure 800 includes a source metal layer 832 having openings OP5, OP6 directly above the gate metal layer 122. In this embodiment, the openings OP5, OP6 are trapezoids having different sizes. In some embodiments, the opening OP5 has a maximum width D7 and a minimum width D8, wherein the maximum width D7 and the minimum width D8 are both greater than the width W of the gate metal layer 122. In some embodiments, the opening OP6 has a maximum width D9 and a minimum width D10, wherein the maximum width D9 is greater than the width W of the gate metal layer 122, and the minimum width D10 is less than the width W of the gate metal layer 122.

Fig. 9 illustrates a partial top view of an exemplary semiconductor structure 900, in accordance with further embodiments of the present invention. As shown in fig. 9, the semiconductor structure 900 includes a source metal layer 932 having openings OP7, OP8 directly above the gate metal layer 122. In this embodiment, the openings OP7, OP8 are oval with different sizes. In some embodiments, the minor axis length D11 of the opening OP7 is greater than the width W of the gate metal layer 122. In some embodiments, the minor axis length D12 of the opening OP8 is less than the width W of the gate metal layer 122.

It is to be noted that, in the semiconductor structure provided in the embodiments of the present invention, the number, the size, and the shape of the openings included in the source metal layer and located directly above the gate metal layer are not limited to the above embodiments. For example, various polygonal (e.g., pentagonal, hexagonal, or octagonal), circular, or irregular arc-shaped openings can be applied to the semiconductor structure provided by the embodiments of the present invention. The number, size and shape of the openings described in the different embodiments above may be integrated into a single semiconductor structure to adjust the degree of coverage of the source metal layer as a source field plate with respect to the gate metal layer as a gate field plate, depending on the actual product design and the required switching speed.

In summary, the semiconductor structure provided by the embodiments of the invention can reduce the risk of the gate structure being subjected to high electric field by the gate field plate, and optimize the electric field distribution by the source field plate, reduce the gate-to-drain capacitance (C)_gd) The gate-to-source capacitance (C) can also be reduced by forming an opening in the source metal layer to adjust the coverage of the gate field plate by the source field plate_gs) Further, the purpose of reducing the switch loss is achieved. Therefore, the semiconductor structure provided by the embodiment of the invention has a breakdown voltage (breakdown voltage) and a gate-to-drain capacitance (C)_gd) The switching loss can be effectively reduced by good balance between the two, and the efficiency of the semiconductor structure is further improved.

The embodiments are summarized above so that those skilled in the art to which the present invention pertains can more clearly understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a substrate;

a gate structure disposed on the substrate, comprising:

a gate electrode disposed on the substrate; and

a gate metal layer electrically connected to the gate electrode and serving as a gate field plate; and

a source structure and a drain structure disposed on the substrate and located on two sides of the gate structure, wherein the source structure comprises:

a source electrode disposed on the substrate;

a first source metal layer electrically connected to the source electrode and extending along the direction from the gate electrode to the drain structure; and

a first dielectric layer disposed on the gate metal layer;

the first source metal layer has a potential different from that of the gate metal layer, and at least a portion of the first dielectric layer directly above the gate metal layer is exposed.

2. The semiconductor structure of claim 1, wherein the first source metal layer completely exposes the first dielectric layer directly above the gate metal layer.

3. The semiconductor structure of claim 1, further comprising:

a second dielectric layer disposed on the first source metal layer and the first dielectric layer.

4. The semiconductor structure of claim 3, wherein the source structure further comprises:

a second source metal layer electrically connected to the source electrode and disposed on the second dielectric layer, wherein at least a portion of the second dielectric layer is exposed above the gate metal layer.

5. The semiconductor structure of claim 4, wherein the source structure further comprises:

a plurality of source contacts, wherein the source electrode, the first source metal layer, and the second source metal layer are electrically connected to each other by the plurality of source contacts.

6. The semiconductor structure of claim 1, further comprising a compound semiconductor layer disposed on the substrate, wherein the compound semiconductor layer comprises:

a buffer layer disposed on the substrate;

a channel layer disposed on the buffer layer, wherein the source structure and the drain structure are in contact with the channel layer via the source electrode and a drain electrode, respectively; and

a barrier layer disposed on the channel layer.

7. The semiconductor structure of claim 6, further comprising a doped compound semiconductor layer between the gate electrode and the barrier layer.

8. A semiconductor structure, comprising:

a substrate;

a gate structure disposed on the substrate, comprising:

a gate electrode disposed on the substrate; and

a gate metal layer electrically connected to the gate electrode and serving as a gate field plate;

a source structure disposed on the substrate, comprising:

a source electrode disposed on the substrate; and

a first source metal layer electrically connected to the source electrode and serving as a source field plate, wherein a potential of the first source metal layer is different from a potential of the gate metal layer, and the first source metal layer has an opening located right above the gate metal layer in a top view; and

and the drain structure is arranged on the substrate.

9. The semiconductor structure of claim 8, wherein a width of the opening varies linearly along a length of the opening.

10. The semiconductor structure of claim 8, wherein the opening has a first width and a second width, wherein the first width is smaller than the width of the gate metal layer, and the first width is not equal to the second width.

11. The semiconductor structure of claim 10, wherein the second width is less than a width of the gate metal layer.

12. The semiconductor structure of claim 10, wherein the second width is greater than a width of the gate metal layer.

13. The semiconductor structure of claim 8, wherein the opening has a minimum width and a maximum width, wherein the minimum width and the maximum width are both greater than a width of the gate metal layer.

14. The semiconductor structure of claim 8, wherein the opening is rectangular.

15. The semiconductor structure of claim 8, wherein the opening has an arcuate profile.

16. The semiconductor structure of claim 8, wherein the source structure further comprises:

and a second source metal layer electrically connected to the source electrode and disposed on the first source metal layer, wherein the second source metal layer has an opening located right above the gate metal layer.

17. The semiconductor structure of claim 16, wherein the source structure further comprises:

18. The semiconductor structure of claim 16, further comprising:

and a plurality of dielectric layers respectively arranged among the grid metal layer, the first source metal layer and the second source metal layer.

19. The semiconductor structure of claim 8, further comprising a compound semiconductor layer disposed on the substrate, wherein the compound semiconductor layer comprises:

a buffer layer disposed on the substrate;

a barrier layer disposed on the channel layer.

20. The semiconductor structure of claim 19, further comprising a doped compound semiconductor layer between the gate electrode and the barrier layer.