CN114335172A

CN114335172A - Semiconductor structure

Info

Publication number: CN114335172A
Application number: CN202011051566.9A
Authority: CN
Inventors: 周钰杰; 林琮翔
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2020-09-29
Filing date: 2020-09-29
Publication date: 2022-04-12

Abstract

A semiconductor structure includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor device, an insulation doped region, and at least one insulation pillar. The substrate comprises a base material and a composite material layer, a semiconductor epitaxial layer is arranged on the substrate, and a semiconductor barrier layer is arranged on the semiconductor epitaxial layer. The first semiconductor element is arranged on the substrate, wherein the first semiconductor element comprises a first semiconductor cover layer positioned on the semiconductor barrier layer. The insulated doped region is located on one side of the first semiconductor element. At least a portion of the insulating column is located within the insulating doped region, the insulating column surrounding at least a portion of the first semiconductor element and penetrating the composite layer.

Description

Semiconductor structure

Technical Field

The present invention relates to a high voltage semiconductor structure, and more particularly, to a high voltage semiconductor structure having an insulating structure.

Background

With the development of the 5G communication and electric vehicle industries, there is an increasing demand for high frequency, high power semiconductor devices, such as high frequency transistors, high power field effect transistors, or High Electron Mobility Transistors (HEMTs). High-frequency and high-power semiconductor devices generally use semiconductor compounds, for example, group III-V semiconductor compounds such as gallium nitride and silicon carbide, which have characteristics such as high frequency, high voltage resistance, and low on-resistance.

Among these devices, high electron mobility transistors have advantages such as high output power and high breakdown voltage, and thus they are widely used in high power applications. Although existing semiconductor structures and methods for forming the same can cope with their intended use, there are still problems to be overcome in various technical aspects such as structure and environment of use.

Disclosure of Invention

Accordingly, the present invention is directed to a semiconductor structure for solving the problems of the prior art.

According to an embodiment of the present invention, a semiconductor structure is provided, which includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor device, an insulation doped region, and at least one insulation pillar. The substrate comprises a base material and a composite material layer, a semiconductor epitaxial layer is arranged on the substrate, and a semiconductor barrier layer is arranged on the semiconductor epitaxial layer. The first semiconductor element is arranged on the substrate, wherein the first semiconductor element comprises a first semiconductor cover layer positioned on the semiconductor barrier layer. The insulated doped region is located on one side of the first semiconductor element. At least a portion of the insulating column is located within the insulating doped region, the insulating column surrounding at least a portion of the first semiconductor element and penetrating the composite layer.

According to an embodiment of the present invention, a semiconductor structure is provided, which includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, an insulating doped region, and at least one insulating pillar. The substrate comprises a base material and a composite material layer. The semiconductor channel layer is arranged on the substrate, the semiconductor barrier layer is arranged on the semiconductor channel layer, and the semiconductor cover layer is arranged on the semiconductor barrier layer. The insulation doped region is located in the semiconductor channel layer and the semiconductor barrier layer and located on at least one side of the semiconductor cover layer. The insulating pillar directly contacts the insulating doped region, and the insulating pillar penetrates through the semiconductor barrier layer, the semiconductor channel layer, and the composite material layer.

According to another embodiment of the present invention, a chip structure is provided, which includes a substrate, a high voltage semiconductor structure, a low voltage semiconductor structure, and at least one insulating pillar. The substrate comprises a base material and a composite material layer. The high-voltage semiconductor structure is arranged on the substrate, and the low-voltage semiconductor structure is arranged on the substrate and is separated from the high-voltage semiconductor structure. The insulating column completely surrounds the high-voltage semiconductor structure and penetrates through the composite material layer.

According to another embodiment of the present invention, a method of operating a high voltage semiconductor structure is provided, the method comprising providing a high voltage semiconductor structure and applying an electronic signal to the high voltage semiconductor structure at an ambient temperature above 150 ℃. The high-voltage semiconductor structure comprises a substrate, a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cover layer, an insulated doped region and at least two insulating columns. The substrate comprises a base material and a composite material layer. The semiconductor channel layer is arranged on the substrate, the semiconductor barrier layer is arranged on the semiconductor channel layer, and the semiconductor cover layer is arranged on the semiconductor barrier layer. The insulation doped region is located in the semiconductor channel layer and the semiconductor barrier layer and located on at least one side of the semiconductor cover layer. The insulating pillar directly contacts the insulating doped region, and the insulating pillar penetrates through the semiconductor barrier layer, the semiconductor channel layer, and the composite material layer.

Drawings

For the following to be more readily understood, reference is made to the drawings and to the detailed description thereof, when read in conjunction with the appended drawings. The embodiments of the present invention are illustrated in detail by the embodiments herein and with reference to the corresponding drawings, and the functional principle of the embodiments of the present invention is explained. Furthermore, for purposes of clarity, the various features in the drawings may not be to scale and the dimensions of some of the features in some drawings may be exaggerated or minimized.

Fig. 1 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the invention.

Fig. 2 is a cross-sectional view of the high voltage semiconductor structure along line a-a' of fig. 1 according to an embodiment of the invention.

Fig. 3 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the invention.

FIG. 4 is a cross-sectional view of the high voltage semiconductor structure along line A-A' of FIG. 3 according to one embodiment of the present invention.

Fig. 5 and 6 are electrical characteristics of the high voltage semiconductor structure of the embodiment of the invention at normal temperature.

Fig. 7 and 8 are electrical characteristics of the high voltage semiconductor structure at high temperature according to an embodiment of the present invention.

Fig. 9 is a schematic top view of a chip structure according to an embodiment of the invention.

Fig. 10 is a schematic top view of a chip structure according to an embodiment of the invention.

FIG. 11 is a cross-sectional view of the high voltage semiconductor structure along line B-B' of FIG. 10 according to one embodiment of the present invention.

The reference numerals are explained below:

1: chip structure

10: high voltage semiconductor structure

10-1: first high voltage semiconductor element

10-2: second high voltage semiconductor element

20: high voltage semiconductor element

22: insulating region

30: logic operation element

40: memory device

100: substrate

100C: base material

100M: composite material layer

101: silicon-containing semiconductor layer

102: semiconductor epitaxial layer

103: semiconductor buffer layer

104: semiconductor barrier layer

105: semiconductor channel layer

110: insulating doped region

112: interlayer dielectric layer

120: insulating column

120_ 1: first insulating column

120_ 2: second insulating column

120_ 3: third insulating column

200: active region

202: source electrode

204: grid electrode

206: drain electrode

210: semiconductor cap layer

300: active region

302: source electrode

304: grid electrode

306: drain electrode

310: semiconductor cap layer

A: chip region

B: cutting street area

L₁: width of

L₂: width of

L₃: width of

S₁: distance between each other

S₂: distance between each other

S₃: distance between each other

S₄: distance between each other

Detailed Description

The present invention provides many different embodiments, which can be used to implement different features of the present invention. Examples of specific components and arrangements are described herein for simplicity of illustration. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way.

In the present invention, the description "the first member is formed on or above the second member" may mean "the first member is in direct contact with the second member", or "another member is present between the first member and the second member", so that the first member is not in direct contact with the second member. Moreover, various embodiments of the present invention may use repeated reference numerals and/or text labels. These repeated use of reference characters and letters are intended to provide a concise and definite description, and are not intended to indicate any relationship between the various embodiments and/or configurations.

In addition, for spatially related descriptive words mentioned in the present invention, for example: the use of "below," "above," "lower," "upper," "lower," "below," "above," "below," "over," "bottom," "top," and the like in describing, for purposes of convenience, the relative relationship of one component or feature to another component(s) or feature in the drawings is for convenience. In addition to the orientations shown in the figures, these spatially relative terms are also used to describe possible orientations of the semiconductor structure during fabrication, during use, and during operation. For example, when the semiconductor structure is rotated 180 degrees, one element that was originally disposed "above" another element becomes disposed "below" the other element. Therefore, as the swing direction of the semiconductor structure changes (rotates by 90 degrees or other angles), the spatially related descriptions for describing the swing direction should be interpreted in a corresponding manner.

Although the present invention has been described using terms such as first, second, third, etc. to describe various elements, components, regions, layers and/or sections, it should be understood that these elements, components, regions, layers and/or sections should not be limited by these terms. Such terms are only used to distinguish one element, component, region, layer and/or block from another element, component, region, layer and/or block, and do not denote any order or importance, nor do they denote any order or importance, but rather the term "sequence" or "sequence" is used to distinguish one element, component, region, layer and/or block from another. Thus, a first element, component, region, layer or block discussed below could be termed a second element, component, region, layer or block without departing from the scope of embodiments of the present invention.

The terms "coupled," "coupled," and "electrically connected," as used herein, are intended to encompass any direct or indirect electrical connection. For example, if a first component is coupled to a second component, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

In the present invention, a "group III-V semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. Among them, the group III element may be boron (B), aluminum (Al), gallium (Ga), or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, the "III-V semiconductor" may include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), the like, or combinations thereof, but is not limited thereto. In addition, if desired, the group III-V semiconductor may also include dopants, such as an N-type or P-type group III-V semiconductor, having a particular conductivity type.

The particular hierarchy of steps or blocks in the steps/processes described below are exemplary. The particular steps or block hierarchies in the steps/flows described below may be rearranged as a matter of design preference. Further, some blocks may be integrated or deleted.

Although the following description describes the present invention in terms of specific embodiments, the principles of the present invention are applicable to other embodiments as well. Moreover, certain details may be omitted so as not to obscure the spirit of the invention, the omitted details being within the scope of one of ordinary skill in the art.

Fig. 1 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the invention. As shown in fig. 1, at least one high voltage semiconductor structure 10 may be disposed on a substrate 100, and the high voltage semiconductor structure 10 may include at least one semiconductor device, such as a first high voltage semiconductor device 10-1 and a second high voltage semiconductor device 10-2. According to an embodiment of the present invention, the first and second high voltage semiconductor elements 10-1 and 10-2 may be semiconductor elements operating at a source voltage or a drain voltage greater than 600V, such as, but not limited to, a high electron mobility transistor. According to an embodiment of the present invention, the first high voltage semiconductor device 10-1 may include an active region 200, a source electrode 202, a gate electrode 204, and a drain electrode 206. The source electrode 202, the gate electrode 204, and the drain electrode 206 may be electrically connected to corresponding regions of the active region 200, respectively. An electronic signal can be inputted into and outputted from the active region 200 through the source electrode 202 and the drain electrode 206, and the current conduction degree of the first high voltage semiconductor device 10-1 can be controlled by applying an appropriate voltage to the gate electrode 204. Similarly, according to an embodiment of the present invention, the second high voltage semiconductor device 10-2 may include an active region 300, a source electrode 302, a gate electrode 304, and a drain electrode 306. The source electrode 302, the gate electrode 304, and the drain electrode 306 may be electrically connected to corresponding regions of the active region 300, respectively. Since the first high voltage semiconductor device 10-1 and the second high voltage semiconductor device 10-2 are operated at a high voltage, the first high voltage semiconductor device 10-1 and the second high voltage semiconductor device 10-2 may be surrounded by the insulation doping region 110 to achieve an electrical insulation effect between the first high voltage semiconductor device 10-1 and the second high voltage semiconductor device 10-2.

Fig. 2 is a cross-sectional view of the high voltage semiconductor structure along line a-a' of fig. 1 according to an embodiment of the invention. As shown in fig. 2, according to an embodiment of the invention, the high voltage semiconductor structure 10 may include, but is not limited to, a substrate 100, a semiconductor epitaxial layer 102, a semiconductor barrier layer 104, an insulated doped region 110, at least two semiconductor cap layers 210, 310, an interlayer dielectric layer 112, and at least two

gate electrodes

204, 304.

According to an embodiment of the invention, the substrate 100 may include a base material 100C and a composite material layer 100M covering the base material 100C. The composition of the substrate 100C may be silicon carbide (SiC) or aluminum oxide (Al)₂O₃) Ceramic materials of sapphire (sapphire), aluminum nitride (aln), or combinations thereof. The composite material layer 100M may be disposed along the surface of the substrate 100C, such as, but not limited to, the top surface of the substrate 100C and the bottom surface of the substrate 100C, respectively, or even the side surface of the substrate 100C. Each composite material layer 100M may include a stacked insulating layer and a seed layer. According to an embodiment of the present invention, for the composite material layers 100M respectively located on the top surface and the bottom surface of the substrate 100C, the composite material layers 100M may respectively include a first insulating layer, a seed layer, and a second insulating layer in sequence along the direction away from the substrate 100C. WhereinThe first and second insulating layers may each be a single or multiple layers of insulating material, such as an oxide, nitride, oxynitride, or other suitable insulating material, and the seed layer may be a semiconductor material, such as silicon, but is not limited thereto. According to an embodiment of the invention, each composite material layer 100M may include an oxide layer, a semiconductor layer, a nitride layer, and an oxide layer stacked in sequence along a direction away from the substrate 100C, but not limited thereto. In the case where the base material 100C is a ceramic base, the substrate 100 is less likely to be broken or bent since the mechanical strength is higher than that of a single-crystal silicon base. In addition, since the ceramic base has higher electrical insulation than the single crystal silicon base, the substrate 100 can withstand higher voltage.

According to an embodiment of the invention, in the case that the first high voltage semiconductor device 10-1 and the second high voltage semiconductor device 10-2 are both high electron mobility transistors, a nitride layer, a super lattice layer (super lattice layer), and a high resistance layer may be selectively disposed between the semiconductor epitaxial layer 102 and the substrate 100, but not limited thereto. A nitride layer may be disposed on the substrate 100, which has fewer lattice defects, so as to improve the epitaxial quality of a semiconductor layer (e.g., the semiconductor epitaxial layer 102) disposed on the nitride layer. The superlattice layer may be used to reduce a lattice mismatch between the substrate 100 and a semiconductor layer (e.g., the semiconductor epitaxial layer 102) disposed thereon, and to reduce stress caused by the lattice mismatch. The high resistance layer has a higher resistivity than other semiconductor layers, thereby preventing leakage current between the semiconductor layer (e.g., the semiconductor epitaxial layer 102) disposed on the high resistance layer and the substrate 100.

The semiconductor epitaxial layer 102 may comprise one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. According to an embodiment of the invention, the semiconductor epitaxial layer 102 may include a semiconductor buffer layer and a semiconductor channel layer from bottom to top. The semiconductor channel layer is an undoped group III-V semiconductor, such as undoped GaN (u-GaN). According to an embodiment of the present invention, the semiconductor channel layer may also be one or more doped group III-V semiconductor layers, such as a P-type group III-V semiconductor layer. For the P-type III-V semiconductor layer, the dopant can be Cd, Fe, Mg or Zn, but is not limited thereto.

The semiconductor barrier layer 104 may comprise one or more group III-V semiconductor layers and may be different in composition from the group III-V semiconductor of the semiconductor channel layer. For example, the semiconductor barrier layer 104 may comprise AlN, Al_yGa_(1-y)N (0 < y < 1), or a combination thereof. According to an embodiment, the semiconductor barrier layer 104 may be an N-type III-V semiconductor, such as, but not limited to, an AlGaN layer that is N-type in nature.

In addition, according to an embodiment of the present invention, the semiconductor channel layer on the upper portion of the semiconductor epitaxial layer 102 may directly contact the semiconductor barrier layer 104, so that a region of the semiconductor epitaxial layer 102 adjacent to the semiconductor barrier layer 104 may form a carrier flow region, such as a two-dimensional electron gas (2-DEG) region. The semiconductor cap layers 210, 310 may be separated from each other and each may be one or more P-type III-V semiconductor layers, such as P-type GaN layers, and the dopant may be a metal dopant selected from Mg, Cd, Zn, or the like.

The isolation doped region 110 may be located in the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104 on both sides of the semiconductor cap layers 210 and 310, and the isolation doped region 110 is preferably located between two semiconductor cap layers 210 and 310 separated from each other without overlapping the semiconductor cap layers 210 and 310. According to an embodiment of the present invention, the isolation doped region 110 may be formed by, for example, applying external energy to destroy the crystal lattices of the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104, or by performing an ion implantation process to implant a specific non-conductor dopant into the semiconductor epitaxial layer 102 and the semiconductor barrier layer 104. The dopant for forming the insulation doping region 110 may include helium, argon, nitrogen, phosphorus, arsenic, oxygen, or a combination thereof, but is not limited thereto.

An interlayer dielectric layer 112 may be disposed on the insulated doped region 110 and cover the semiconductor cap layers 210, 310. Optionally, an interconnect structure may be further disposed in the interlayer dielectric layer 112 to electrically connect to the

semiconductor cap layer

210, 310 or the semiconductor barrier layer 104, but is not limited thereto.

The

gate electrodes

204, 304 may be disposed on the top surface of the interlayer dielectric layer 112 and electrically connected to the corresponding semiconductor cap layers 210, 310. According to an embodiment of the present invention, the

gate electrodes

204, 304 and other electrodes disposed in the first high voltage semiconductor device 10-1 and the first high voltage semiconductor device 10-2, such as the source electrode and the drain electrode, are made of conductive materials, such as Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi₂Combinations of the foregoing, or the like.

Fig. 3 is a schematic top view of a high voltage semiconductor structure according to an embodiment of the invention. As shown in fig. 3, similar to the high voltage semiconductor structure 10 shown in the embodiment of fig. 2, the high voltage semiconductor structure 10 shown in fig. 3 includes an insulating pillar 120 surrounding

active regions

200, 300 of the high voltage semiconductor elements 10-1, 10-2 in addition to the insulating doped region 110. According to an embodiment of the present invention, the insulating pillar 120 may surround the periphery of the

active regions

200, 300. According to an embodiment of the present invention, the insulating pillars 120 may include a plurality of insulating pillars (or sub-insulating pillars), such that the insulating pillars may be separately disposed and surround the peripheries of the

active regions

200 and 300, respectively. In an embodiment of the present invention, the insulating pillar 120 may be formed earlier than the

gate electrode

204, 304, the

source electrode

202, 302, or the

drain electrode

206, 306 to ensure an aspect ratio (aspect ratio) of the insulating pillar 120. By setting the dimensions of the insulating pillar 120 and the insulating doped region 110 within a specific range, the best electrical performance can be achieved, as further described in table 1 below.

FIG. 4 is a cross-sectional view of the high voltage semiconductor structure along line A-A' of FIG. 3 according to one embodiment of the present invention. As shown in fig. 4, according to an embodiment of the present invention, the insulating pillar 120 may include a plurality of insulating pillars, such as a first insulating pillar 120_1, a second insulating pillar 120_2, and a third insulating pillar 120_ 3. The insulating column 120 may be located between the high voltage semiconductor elements 10-1, 10-2, for example, between the semiconductor cap layers 210, 310. Furthermore, the insulating pillars 120 are not limited to being located only on the semiconductor cap layer 210Or one side of the semiconductor cap layer 310, the insulating pillar 120 may also be located on both sides of the semiconductor cap layer 210 or the semiconductor cap layer 310, or further around the periphery of the semiconductor cap layer 210 or the semiconductor cap layer 310. According to an embodiment of the present invention, at least one of the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may penetrate through the insulating doped region 110 and the composite material layer 100M and directly contact the insulating doped region 110 and the substrate 100C. According to an embodiment of the present invention, when the isolation doped region 110 is disposed in the semiconductor barrier layer 104 and the semiconductor epitaxial layer 102, the first isolation pillar 120_1, the second isolation pillar 120_2, and the third isolation pillar 120_3 can be considered to penetrate through the semiconductor barrier layer 104 and the semiconductor epitaxial layer 102 simultaneously. The insulating pillar 120 may be a single-layer structure or a composite structure, such as a single-layer structure including only an insulating material, or a composite structure including both an insulating material and a conductive material embedded in the insulating material, but not limited thereto. According to an embodiment of the present invention, the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may each have a width L₁、L₂、L₃And the first and third insulating pillars 120_1 and 120_3 and the

semiconductor cap layer

210 and 310 may have a space S therebetween₁A distance S₄The first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may have a space S therebetween₂A distance S₃. According to an embodiment of the present invention, the first insulating pillar 120_1, the second insulating pillar 120_2, and the third insulating pillar 120_3 may be equally distributed, i.e. the distance S₂Equal to the spacing S₃. According to an embodiment of the present invention, the width L of the insulating column 120₁、L₂、L₃May be smaller than the interval S between the insulating pillars 120₂、S₃。

According to an embodiment of the present invention, the insulating pillar 120 may be formed after the formation of the insulating doped region 110 but before the formation of the interlayer dielectric layer 112, but is not limited thereto. For example, after the ion implantation process is performed to form the isolation doped region 110, photolithography and etching processes may be used to form at least one trench in the isolation doped region 110, wherein the bottom of the trench may reach as deep as the top surface of the substrate 100C, so that the substrate 100C is exposed out of the trench. Thereafter, an appropriate deposition process, such as a chemical vapor deposition process or a spin-on process, may be performed to fill the trench with an insulating material, thereby forming the insulating pillar 120 as shown in FIG. 4. An interlayer dielectric layer 112 may be further formed on the insulating pillar 120, and at least one electrode, such as the

gate electrodes

204, 304, may be formed on the surface of the interlayer dielectric layer 112.

According to an embodiment of the present invention, in order to further reduce the thickness of the substrate 100, after forming the electrodes on the surface of the interlayer dielectric layer 112, a thinning process (grinding) may be performed on the back surface of the substrate 100 to completely remove the composite material layer 100M on the bottom surface of the base material 100C or further remove a portion of the base material 100C until the substrate 100 is thinned to a predetermined thickness.

According to an embodiment of the present invention, a method of operating a high voltage semiconductor structure is provided. First, a high voltage semiconductor structure, such as the high voltage semiconductor structure 10 shown in fig. 1, 2, or fig. 3, 4, is provided. Thereafter, an electronic signal may be applied to the high voltage semiconductor structure 10 with the ambient temperature in a particular interval. According to an example, a voltage higher than 200 volts (V) may be applied to the drain electrode 202 of the first high voltage semiconductor element 10-1 under a condition that an ambient temperature falls within an interval of 15 ℃ to 300 ℃, and a magnitude of a current transmitted from the drain electrode 302 of the second high voltage semiconductor element 10-2 may be measured. According to another example, it is possible to apply a voltage increasing from-800V to the drain electrode 202 of the first high voltage semiconductor element 10-1 under the condition that the ambient temperature falls within the interval of 15 ℃ to 300 ℃, and measure I of the second high voltage semiconductor element 10-2_DAnd V_GThe relationship (2) of (c).

The electrical performance of the high voltage semiconductor structure of the present invention is described accordingly below. The structure of the high voltage semiconductor structure may be, for example, the high voltage semiconductor structure 10 shown in fig. 1, fig. 2, or fig. 3 and fig. 4, and both the high voltage semiconductor elements 10-1 and 10-2 are high electron mobility transistors.

According to an embodiment of the present invention, it is possible to apply a voltage higher than 200V to 800V to the drain electrode 202 of the first high voltage semiconductor device 10-1 shown in fig. 2 and 4, respectively, at an ambient temperature of 25 ℃, and measure the magnitude of the current delivered from the drain electrode 302 of the second high voltage semiconductor device 10-2. Furthermore, for the high voltage semiconductor structure shown in fig. 2, the lateral dimensions of the isolation doped regions 110 between adjacent high voltage semiconductor elements 10-1, 10-2 may be adjusted such that the isolation doped regions 110 have unequal lateral dimensions, and the above measurements are performed for the respective high voltage semiconductor structures 10. Similarly, for the high voltage semiconductor structure shown in fig. 4, the number of insulating pillars 120 may be adjusted and the above measurements may be performed for the corresponding high voltage semiconductor structure 10. The results of the above measurements are reported in table 1 below.

TABLE 1

Note 1: the number of the insulating columns refers to the number of the insulating columns between two adjacent high-voltage semiconductor elements, namely 2: the whole insulation region width refers to the whole insulation region width between two adjacent active regions in the high-voltage semiconductor structure

Note 3: when the drain of one high-voltage semiconductor element outputs a specified current value, the voltage value to be applied to the drain of the adjacent high-voltage semiconductor element

From the results shown in table 1, it can be seen that when the high voltage semiconductor structure 10 includes the insulation doped region 110 or both the insulation doped region 110 and the insulation pillar 120, a voltage of at least 950V is applied to the drain electrode 202 of the high voltage semiconductor device 10-1, and the drain electrode 302 of the adjacent high voltage semiconductor device 10-2 generates a current of 1 nA. In addition, the high voltage semiconductor structure 10 including both the isolation doped region 110 and the isolation pillar 120 has a higher voltage endurance than the high voltage semiconductor structure 10 including only the isolation doped region 110. Further, when the number of the insulating pillars 120 reaches 2, the withstand voltage is saturated, and thus, in order to prevent the insulating pillars 120 from occupying an excessive crystal grain area, the sizes of the insulating pillars 120 and the insulating doped region 110 may be set to a specific range, so that the optimum electrical performance may be achieved.

According to an embodiment of the present invention, it is possible to apply a voltage of-200V to the drain electrode 202 of the first high voltage semiconductor element 10-1 shown in FIGS. 2 and 4, respectively, at an ambient temperature of 25 deg.C, and measure I of the second high voltage semiconductor element 10-2_DAnd V_GThe relationship (2) of (c). The results of the measurements are set forth in fig. 5 and 6, respectively. Fig. 5 and 6 are electrical characteristics of the high voltage semiconductor structure of the embodiment of the invention at normal temperature. Wherein fig. 5 corresponds to the electrical characteristics of the high voltage semiconductor structure 10 shown in fig. 2, and fig. 6 corresponds to the electrical characteristics of the high voltage semiconductor structure 10 shown in fig. 4. As shown in FIGS. 5 and 6, I of the second high voltage semiconductor device 10-2 is determined regardless of the magnitude of the voltage applied to the drain electrode 202 of the first high voltage semiconductor device 10-1_DAnd V_GThe relationship of (a) may remain substantially fixed. In other words, the threshold voltage of the second high voltage semiconductor device 10-2 does not fluctuate due to the voltage applied to the first high voltage semiconductor device 10-1.

Similarly, according to an embodiment of the present invention, it is possible to apply a voltage of-500V to the drain electrode 202 of the first high voltage semiconductor element 10-1 shown in FIGS. 2 and 4, respectively, at an ambient temperature of 150 deg.C, and measure I of the second high voltage semiconductor element 10-2_DAnd V_GThe relationship (2) of (c). The results of the measurements are set forth in fig. 7 and 8, respectively. Fig. 7 and 8 are electrical characteristics of the high voltage semiconductor structure at high temperature according to an embodiment of the present invention. Fig. 7 corresponds to the electrical characteristics of the high-voltage semiconductor structure 10 shown in fig. 2, and fig. 8 corresponds to the electrical characteristics of the high-voltage semiconductor structure 10 shown in fig. 4. As shown in FIG. 7, when a negative voltage or a positive voltage is applied to the drain electrode 202 of the first high voltage semiconductor element 10-1, I of the second high voltage semiconductor element 10-2_DAnd V_GIn other words, the threshold voltage of the second high voltage semiconductor device 10-2 varies due to the voltage applied to the first high voltage semiconductor device 10-1. Further, as the voltage applied to the first high voltage semiconductor element 10-1 is gradually increased, the degree of shift of the threshold voltage of the second high voltage semiconductor element 10-2 may be more significant. In contrast, as shown in FIG. 8, regardless of whetherWhat value of the voltage applied to the drain electrode 202 of the first high voltage semiconductor device 10-1 is I of the second high voltage semiconductor device 10-2_DAnd V_GThe relationship of (a) may remain substantially fixed. In other words, the threshold voltage of the second high voltage semiconductor device 10-2 does not fluctuate due to the voltage applied to the first high voltage semiconductor device 10-1.

Fig. 9 is a schematic top view of a chip structure according to an embodiment of the invention. As shown in fig. 9, the chip structure 1 may be disposed in a chip area a of the wafer, and the periphery of the chip area a may be surrounded by a scribe line area B. The chip structure 1 may include at least one high voltage semiconductor device 20 and a low voltage semiconductor device (e.g., a logic operation device 30 or a memory device 40), and the high voltage semiconductor device 20 may be surrounded by an insulating region 22. The high voltage semiconductor device 20 may be a high electron mobility transistor as described in the above embodiments, and the insulating doped region and/or the insulating pillar may be disposed in the insulating region 22.

Fig. 10 is a schematic top view of a chip structure according to an embodiment of the invention. The chip structure 1 in fig. 10 differs from the chip structure 1 in fig. 9 mainly in that the chip structure 1 in fig. 10 may include at least two high voltage semiconductor elements 20, and the high voltage semiconductor elements 20 may each be surrounded by an insulating region 22.

FIG. 11 is a cross-sectional view of the high voltage semiconductor structure along line B-B' of FIG. 10 according to one embodiment of the present invention. As shown in fig. 11, according to an embodiment of the invention, each high voltage semiconductor device 20 may include, from bottom to top, a substrate 100, a silicon-containing semiconductor layer 101, a semiconductor epitaxial layer 102, a semiconductor barrier layer 104, and a

semiconductor cap layer

210, 310, and a two-dimensional electron gas may exist at an interface between the semiconductor channel layer 105 and the semiconductor barrier layer 104 (as indicated by the dashed line). In addition, the adjacent high voltage semiconductor devices 20 may be connected in series with the source electrode 302 of one high voltage semiconductor device 20 to the drain electrode 206 of another high voltage semiconductor device 20 through the wire 320, but is not limited thereto. According to an embodiment of the present invention, the insulating doped region 110 and the insulating pillar 120 may be disposed between and around the adjacent high voltage semiconductor elements 20. The insulated doped region 110 may be obtained by doping or destroying the semiconductor barrier layer 104, the semiconductor channel layer 105, and/or a portion of the semiconductor buffer layer 103. An upper portion of the insulating pillar 120 may be disposed in the insulating doped region 110, and a lower portion of the insulating pillar 120 may penetrate through the semiconductor buffer layer 103 and the silicon-containing semiconductor layer 101, or further penetrate through the composite material layer 100M.

According to the above embodiments, the insulating doped region is disposed in the high-voltage semiconductor structure, or the insulating doped region and the insulating pillar are disposed at the same time, so that the high-voltage semiconductor device in the high-voltage semiconductor structure can be prevented from affecting the electrical performance of other high-voltage semiconductor devices and low-voltage semiconductor devices. In addition, for the high-voltage semiconductor structure comprising the insulated doped region and the insulated column, the high-voltage semiconductor structure is less prone to the problem of threshold voltage shift at high temperature.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a substrate including a base material and a composite material layer;

a semiconductor epitaxial layer disposed on the substrate;

a semiconductor barrier layer disposed on the semiconductor epitaxial layer;

a first semiconductor element disposed on the substrate, wherein the first semiconductor element includes a first semiconductor cap layer on the semiconductor barrier layer;

an insulation doped region located at one side of the first semiconductor element; and

at least one insulating column at least partially located in the insulating doped region, the at least one insulating column surrounding at least a portion of the first semiconductor element and penetrating through the composite material layer.

2. The semiconductor structure of claim 1, wherein the substrate comprises aluminum nitride, silicon carbide, aluminum oxide, or a combination of the foregoing.

3. The semiconductor structure of claim 1, wherein said at least one insulating pillar directly contacts said substrate.

4. The semiconductor structure of claim 1, wherein said first semiconductor element comprises a gate electrode, a source electrode, and a drain electrode, and said at least one insulating pillar does not extend beyond a top surface of said gate electrode.

5. The semiconductor structure of claim 1, further comprising an interlayer dielectric layer disposed on the at least one insulating pillar.

6. The semiconductor structure of claim 1, further comprising a second semiconductor element disposed adjacent to the first semiconductor structure, and wherein the at least one insulating pillar comprises a plurality of insulating pillars surrounding the first semiconductor element and the second semiconductor element, respectively.

7. The semiconductor structure of claim 6, wherein the plurality of insulating pillars is 3 in number.

8. The semiconductor structure of claim 1 wherein said isolation doped region is formed by applying external energy to destroy the crystal lattice of said semiconductor epitaxial layer and said semiconductor barrier layer or to implant a non-conductive element into said semiconductor epitaxial layer and said semiconductor barrier layer.

9. The semiconductor structure of claim 1, further comprising a second semiconductor device disposed on the substrate, wherein the second semiconductor device comprises a second semiconductor cap layer disposed on the semiconductor barrier layer, and wherein the insulated doped region is disposed between the first semiconductor device and the second semiconductor device.

10. The semiconductor structure of claim 9, wherein the first semiconductor device is a high voltage device and the second semiconductor device is a low voltage device.