CN104465746B - A kind of HEMT device and its manufacturing method - Google Patents
A kind of HEMT device and its manufacturing method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention discloses a kind of HEMT device and its manufacturing methods.The device includes substrate；Active area is formed on substrate；Barrier region is formed on active area；Resistance is formed on barrier region, and grid is formed on Resistance；Low-resistance region is respectively formed at grid both sides, and it is masking that wherein low-resistance region, which is with grid, is formed by self-registered technology, and low-resistance region has doping particle；Source electrode and drain electrode is respectively formed on the low-resistance region of grid both sides.Through the invention, be effectively shortened grid source away from grid leak away from reducing grid source series resistance and grid leak series resistance, improve the high frequency characteristics of device.And accurate alignment need not be carried out when low-resistance region formation, the requirement to photoetching process alignment precision is reduced, improves the yield rate of device, reduce production cost.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of HEMT devices and its manufacturing method.
Background technology
Compared with other semi-conducting materials, III-nitride material is with energy gap is big, critical breakdown electric field is high, full
With the advantages that velocity of electrons is high, thermal conductivity is high, chemical property is stablized.In addition III-nitride material has stronger spontaneous pole
Change and piezoelectric polarization effect, for example, GaN can be with the materials shape such as aluminum gallium nitride (AlGaN), indium aluminium nitrogen (InAlN) and aluminium nitrogen (AlN)
At two-dimensional electron gas (2DEG) conducting channel with high areal density and high mobility.Therefore GaN base high electron mobility field effect
Transistor (HEMT) is answered to have the characteristics that current density is big, power density is big, high frequency characteristics is good and high temperature resistant, dual-use
Microwave power field have a wide range of applications.
In microwave applications field, it is to improve GaN based hemts to reduce the size of device to shorten grid length and reduce source and drain resistance
Device current gain cut-off frequency (fT) important measures.Currently, the grid length of GaN base HEMT device has shortened to 30nm, device
The current gain cutoff frequencies of part have been also up to 370GHz (referring to Yuanzheng Yue, et al, InAlN/AlN/GaN
HEMTs With Regrown Ohmic Contacts and fT of 370GHz,IEEE Electron Device
Letters,vol.33,no.7,pp.988-990.)。
In GaN base HEMT device manufacturing process, for determining device size, ohmic contact resistance and grid source, grid leak
Series resistance be influence device high frequency characteristics two important parameters, therefore shorten grid source away from grid leak away from improve Ohmic contact
Growth technique is two important measures for improving device high frequency characteristics.
On the one hand, the method for forming source-drain electrode area and grid in the prior art, is limited to the limitation of photoetching alignment precision, device
The source and drain of part is away from usually larger so that the grid source series resistance and grid leak series resistance of HEMT device are larger, to reduce
The high frequency characteristics of HEMT device.
On the other hand, low ohmic contact resistance needs good Ohmic contact growth technique.The current generally use of industry
High annealing forms alloy Ohmic contact, however high annealing can cause grid knot to degenerate or even fail, and grid leakage current is made to increase,
Grid schottky junction is even set to form Ohmic contact.Larger grid leakage current can reduce the high frequency performance and breakdown performance of device,
The reliability and yield rate of device are reduced simultaneously.
Invention content
In view of this, the present invention proposes a kind of HEMT device and its manufacturing method, it is involved in background technology to solve
One or more of the problem of.
On the one hand, an embodiment of the present invention provides a kind of HEMT devices, including：
Substrate；
Active area is formed on the substrate；
Barrier region is formed on the active area；
Resistance is formed on the barrier region；
Grid is formed on the Resistance；
Low-resistance region is respectively formed at the grid both sides, wherein and it is masking that the low-resistance region, which is with the grid,
It is formed by self-registered technology, and the low-resistance region has doping particle, the concentration of the doping particle is in vertical side
To peak value be located at and the corresponding part of the active area or part corresponding with the barrier region；And
Source electrode and drain electrode is respectively formed on the low-resistance region of the grid both sides.
The substrate can be the suitable growth III-V races such as sapphire, silicon, silicon carbide, gallium nitride or rare earth oxide
Close the material of object.
The material of the grid is refractory material, and the refractory material is selected from one or more in the following group：Tungsten (W),
Molybdenum (Mo), tantalum (Ta), titanium, chromium and tantalum nitride；Or it is
The nitride of material in described group；Or it is
The alloy of material in described group；Or it is
The lamination of material in described group；Or it is
The lamination of the alloy of material in the nitride of material in described group or the material in described group or described group；Or
Person is
The alloy or insulation material of material in the nitride of material in described group or the material in described group or described group
The lamination of material.
The barrier region is the semiconductor material layer that hetero-junctions is formed with the material of the active area；Or it is
The lamination of semi-conducting material and insulating materials formed thereon.
One or more etching speeds that are eclipsed in the grid etch are less than the grid material in the Resistance material
The rate that one or more materials in material are etched.
Preferably, the Resistance includes：
Anti-etching area is formed on the barrier region, when for reducing the grid etch caused by the barrier layer
Etching injury；
First medium area is formed in the anti-etching area, the leakage current for reducing the grid.
The one or more materials for being eclipsed etching speed and being preferably less than in the grid material of anti-etching area's material
The rate being etched.
First medium area material is insulating materials.
The surface towards gate electrode side of the low-resistance region is less than the surface towards gate electrode side of the Resistance.
Preferably, the HEMT device further includes grid curb wall, is formed in the grid both sides or is formed in the grid
On both sides and the grid.The grid curb wall can be in the grid and source electrode and the grid and the width of drain directions
It is adjusted using photoetching technique, and the width of grid leak side grid curb wall is not less than the width of grid source side grid curb wall.Institute
The material for stating grid curb wall is insulating materials.
Preferably, the HEMT device further includes gate medium, is formed between the Resistance and the grid.
Preferably, the HEMT device further includes buffer layer, is formed between the substrate and the active area, for dropping
Lattice mismatch between low substrate and active area.
On the other hand, an embodiment of the present invention provides a kind of methods of manufacture HEMT device, including step：
S1, active layer is formed on substrate；
S2, barrier layer is formed on the active layer；
S3, barrier layer is formed on the barrier layer；
S4, grid is formed on the barrier layer；
S5, with the grid it is masking, is formed and low-resistance region and formed in the grid both sides by self-registered technology
Resistance, active area and barrier region, wherein the low-resistance region has doping particle；And
S6, the low-resistance region in the grid both sides are respectively formed source electrode and drain electrode.
Step S5 includes in a kind of method of manufacture HEMT device：
The region of grid both sides is doped, wherein in doping depth to active area or barrier region, is doped region shape
At low-resistance region, undoped barrier layer, barrier layer and active layer are respectively formed the Resistance, barrier region and active area,
And wherein it is described doping particle concentration the peak value of vertical direction be located at part corresponding with the active area or with it is described
The corresponding part in barrier region.
Optionally, step S5 further includes in a kind of method of manufacture HEMT device：
It is masking, the resistance of removal grid both sides whole thickness with grid before the region to grid both sides is doped
The barrier layer of barrier and part thickness, or the barrier layer of removal grid both sides whole thickness and the barrier layer of whole thickness are to reveal
Go out the active layer, or the barrier layer and part thickness of the barrier layer of removal grid both sides whole thickness and whole thickness
Active layer.
Optionally, step S5 includes in a kind of method of manufacture HEMT device：
It is masking with grid, the barrier layer of removal grid both sides whole thickness and the barrier layer of whole thickness are described to expose
Active layer, or the barrier layer and part thickness of the barrier layer of removal grid both sides whole thickness and whole thickness are active
Layer；Barrier layer, barrier layer and the active layer not being removed are respectively formed the Resistance, barrier region and active area；
Region growing in grid both sides carries the semi-conducting material of doping particle, forms low-resistance region.
Preferential, a kind of method of manufacture HEMT device further includes between step S4 and S5：In the grid two
Grid curb wall is formed on side or the grid both sides and grid, the side wall can utilize light in the width in grid source and grid leak direction
Lithography is adjusted, and the width of grid leak side grid curb wall is not less than the width of grid source side grid curb wall.
Further, when being doped to the region of grid both sides using ion injection method, ion implanting direction and gesture
The angle of barrier layer and active layer interface vertical direction along clockwise direction is more than or equal to 0 degree, and is less than or equal to 40 degree.The present invention is logical
Cross source and drain self-registered technology be effectively shortened grid source away from grid leak away from, reduce grid source series resistance and grid leak series resistance,
Improve the high frequency characteristics of device；And accurate alignment need not be carried out when the trivial formation of low resistance, is reduced to photoetching process
The requirement of alignment precision, improving the yield rate of device reduces production cost, is hindered by increasing between barrier layer and grid
Barrier can reduce the etch damage of barrier layer.Further, in a preferred embodiment of the invention, grid uses infusibility material
Material avoids grid knot caused by Ohmic contact high annealing and degenerates, and improves the yield rate and reliability of device；Source and drain is highly doped
Or source and drain regrowth process effectively improves the ohmic contact characteristic of source-drain electrode, reduces ohmic contact resistance, to
Improve the high frequency performance of device.
In reading specific implementation mode and after checking attached drawing, those skilled in the art will recognize that other spy
It seeks peace advantage.
Description of the drawings
Example is explained now with reference to attached drawing.Attached drawing is for illustrating basic principle so that illustrates only and understands basic principle institute
Required aspect.Attached drawing is not scale.Identical reference numeral indicates similar feature in the accompanying drawings.
Fig. 1 shows the structural schematic diagram for the HEMT device that the embodiment of the present invention one provides；
Fig. 2 shows the manufacturing method flow charts for the HEMT device that the embodiment of the present invention one provides；
Fig. 3 a-3f, 5a-5c show each step pair of manufacturing method for the HEMT device that according to embodiments of the present invention one provides
The structural section figure answered；
Fig. 4 show the embodiment of the present invention one provide HEMT device manufacturing method in low-resistance region doping particle concentration
Distribution schematic diagram；
Fig. 6 is the sectional view of the structure of HEMT device provided by Embodiment 2 of the present invention；
Fig. 7 shows the flow chart of the manufacturing method of HEMT device provided by Embodiment 2 of the present invention；
Fig. 8 is the cross-sectional view of the structure for the HEMT device that the embodiment of the present invention three provides；
Fig. 9 shows the flow chart of the manufacturing method for the HEMT device that the embodiment of the present invention three provides；
Figure 10 a- Figure 10 g, Figure 11 show each step pair of manufacturing method for the HEMT device that the embodiment of the present invention three provides
The structural section figure answered；
Figure 12 is intermediate ion of embodiment of the present invention injection schematic diagram.
Specific implementation mode
Technical solution to further illustrate the present invention below with reference to the accompanying drawings and specific embodiments.Such as " under
Face ", " lower section ", " ... under ", " low ", " top ", " ... on ", the spatial relationship term of "high" etc. for keeping description convenient,
To explain positioning of the element relative to second element, indicate in addition to from shown in figure those be orientated different orientations with
Outside, these terms are intended to cover the different orientation of device.In addition, for example " element is in another element up/down " can be with table
Show that two elements are in direct contact, can also indicate that also there are other elements between two elements.In addition, such as " first ", " the
Two " etc. term is also used for describing each element, area, part etc., and should not be regarded as limiting.Similar term is logical in description
Similar element is indicated in.
Embodiment one
Fig. 1 shows the structural schematic diagram for the HEMT device that the embodiment of the present invention one provides.As shown in Figure 1, shown HEMT
The structure of device includes：Substrate 100；Active area 106 is formed on substrate 100；Barrier region 107 is formed on active area 106；
Resistance 112 is formed on barrier region 107, and grid 103 is formed on Resistance 112；Low-resistance region 104, is formed in grid
It is masking that 103 both sides, wherein low-resistance region 104, which are with grid 103, is formed by self-registered technology, and the low resistance
There is doping particle, the concentration for adulterating particle to be located in the peak value of vertical direction corresponding with the active area 106 in area 104
Part or part corresponding with the barrier region 107；And source electrode 108 and drain electrode 109, be respectively formed at 103 both sides of grid
On low-resistance region 104.
Wherein, the material of substrate 100 can be the suitable growths such as sapphire, silicon, silicon carbide, gallium nitride or rare earth oxide
The material of III-V compound.Preferably, the material of substrate 100 is silicon carbide.
Wherein, active area 106 can be by one layer of aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1；X+y+z=1)) or
Multilayer InxAlyGazN (0≤x, y, z≤1；X+y+z=1, x, y, z is not exactly the same in each layer) lamination composition.Preferably,
The material of active area 106 is GaN.
Wherein, barrier region 107 can be formed the semiconductor material of hetero-junctions by one or more layers with the active area 106
Material composition, such as InxAlyGazN (0≤x, y, z≤1；X+y+z=1).
The rate that the material of Resistance 112 is etched is preferably shorter than the rate or barrier layer that 103 material of grid is etched
The rate that 111 material is etched is preferably less than 103 material of grid and semi-conducting material or the lamination of insulating materials, wherein
The semi-conducting material can be (0≤x, y, z≤1 InxAlyGazN；X+y+z=1) etc., the insulating materials can be nitrogen
SiClx, aluminium oxide or silica or hafnium oxide etc., handling in this way is advantageous in that in 103 material of etching grid and protects institute
Barrier layer 102 is stated, the etching injury of barrier layer 102 is reduced.
Wherein, grid 103 can be conductivity gate, can also be the grid that other form non-ohmic contact with barrier region
Pole.Grid 103 may include that gate medium 1031 and refractory material 1032, the gate medium 1031 can reduce the electric leakage of grid 103
Stream, the gate medium 1031 are formed between Resistance 112 and refractory material 1032, and the fusing point of the refractory material 1032 is high
In the impurity annealing activationary temperature when forming low-resistance region 104 using doping and in low-resistance region 104 and source electrode 108 and drain electrode
109 form annealing temperature when Ohmic contact.1032 optional material of refractory material is selected from one or more in the following group：Tungsten
(W), molybdenum (Mo), tantalum (Ta), titanium, chromium and tantalum nitride；Or the nitride for the material in described group；Or in described group
The alloy of material, or be the lamination of material in described group；Or in described group material or described group in material nitrogen
The lamination of the alloy of material in compound or described group；Or in described group material or described group in material nitride
Or the alloy of the material in described group or the lamination of insulating materials.
Since grid 103 uses refractory material, in the mistake for subsequently forming low-resistance region 104 and source electrode 108 and drain electrode 109
Cheng Zhong avoids grid knot caused by high annealing and degenerates, to improve the yield rate and reliability of device.
In order to reduce the short-circuit possibility of low-resistance region 104 and grid 103, and reduce between low-resistance region 104 and grid 103
Leakage current, the peak value of the concentration of doping particle in the vertical direction is located at active area 106 or barrier region in low-resistance region 104
107.Width for low resistance region in vertical direction can be adjusted according to specific requirements, this is those skilled in the art
It can realize.
Preferably, in order to further decrease the short-circuit possibility of low-resistance region 104 and grid 103, and reduce low-resistance region 104
With the leakage current between grid 103, the low-resistance region 104 is less than the court of the Resistance 112 towards the surface of 103 side of grid
To the surface of gate electrode side.
Wherein, source electrode 108 and drain electrode 109 are respectively formed on the low-resistance region 104 of 103 both sides of grid, and contact type is
Ohmic contact, the annealing temperature for forming Ohmic contact are less than the fusing point of grid refractory material.Wherein, the source electrode and drain electrode distance
The lateral distance of grid can be respectively greater than the lateral distance of source area and drain region apart from grid.
In the following, the manufacturing method of above-mentioned HEMT device, which elaborates, to be realized to the present invention, it is as shown in Figure 1 to manufacture
HEMT device.
It is shown as shown in Fig. 2 Fig. 2 shows the manufacturing method flow chart for the HEMT device that the embodiment of the present invention one provides
The manufacturing method of HEMT device includes step：
Step S11, active layer is formed on substrate；
Step S12, barrier layer is formed on the active layer；
Step S13, barrier layer is formed on the barrier layer；
Step S14, grid is formed on the barrier layer；
Step S15, with the grid be masking, by self-registered technology the grid both sides formed low-resistance region and
Resistance, active area and barrier region are formed, wherein the low-resistance region has doping particle；And
Step S16, it is respectively formed source electrode and drain electrode on the low-resistance region of the grid both sides.
Fig. 3 a-3f, 5a-5c show each step pair of manufacturing method for the HEMT device that according to embodiments of the present invention one provides
The structural section figure answered.
As shown in Figure 3a, substrate 100 is provided.
The material of substrate 100 can be the suitable growth III-V such as sapphire, silicon, silicon carbide, gallium nitride or rare earth oxide
The material of compounds of group.Preferably, the material of substrate 100 is gallium nitride.
As shown in Figure 3b, active layer 101 is formed on substrate 100.
If active layer 101 can be by dried layer aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1；X+y+z=1)) if or
Dried layer InxAlyGazN (0≤x, y, z≤1；X+y+z=1, x, y, z is different in each layer) it is formed with the lamination of semi-conducting material.It is excellent
The material of selection of land, active layer 101 is GaN.The method for forming active layer includes but not limited to chemical vapor deposition (CVD), hydrogenation
Object vapour phase epitaxy (HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) etc..
As shown in Figure 3c, barrier layer 102 is formed on active layer 101.
The semi-conducting material that barrier layer 102 can be formed hetero-junctions by one or more layers with active layer 101 forms, example
Such as InxAlyGazN (0≤x, y, z≤1；X+y+z=1).The method for forming barrier layer 102 includes but not limited to that chemical gaseous phase is formed sediment
Product (CVD), hydride gas-phase epitaxy (HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) etc..
Preferably, barrier layer 102 can be formed the semiconductor of hetero-junctions by one or more layers with the active area 101
Material (such as InxAlyGazN (0≤x, y, z≤1；X+y+z=1 it)) is formed with the lamination of insulating materials formed thereon.
As shown in Figure 3d, barrier layer 111 is formed on barrier layer 102.
The etching speed that is eclipsed of one or more materials in the material on barrier layer 111 is preferably less than in 103 material of grid
The rate that is etched of one or more materials.
Preferably, the material on the barrier layer 111 is non-crystalline material.
Specifically preferred, the material on barrier layer 111 is aluminium nitride in embodiment one.
Handling in this way is advantageous in that in 103 material of etching grid the barrier layer 102 is protected to be not etched.Another party
When face forms low-resistance region 104 using the method for ion implanting, 102 material of the barrier layer can weaken raceway groove effect when injection
It answers, so as to more accurately control injection ion distribution.
As shown in Figure 3 e, grid 103 is formed on barrier layer 111, grid 103 can be conductivity gate, can also be
Other form the grid of non-ohmic contact with barrier region.
Wherein, if 103 material of the grid can be refractory conductive material or refractory conductive material and dried layer
InxAlyGazN(0≤x,y,z≤1；X+y+z=1) or the lamination of dielectric material, the dielectric material can be silicon nitride, oxygen
Change aluminium or silica or hafnium oxide etc..
The fusing point of the refractory conductive material is moved back higher than impurity when forming low-resistance region using doping in the steps afterwards
Fiery activationary temperature and the annealing temperature when low-resistance region and source electrode and drain electrode form Ohmic contact.Optional material be selected from
It is one or more in the following group：Tungsten (W), molybdenum (Mo), tantalum (Ta), titanium, chromium and tantalum nitride；Or the nitrogen for the material in described group
Compound；Or the alloy for the material in described group；Or it is the lamination of material in described group；Or it is the material in described group
The material in described group nitride or described group in material alloy lamination；Or in described group material or institute
State the material in group nitride or described group in material alloy or insulating materials lamination, the insulating materials is for dropping
The leakage current of low grid.
Preferably, the grid 103 that formed on barrier layer 111 may include：Gate medium is formed on barrier layer 111
1031, refractory material 1032 is formed on the gate medium 1031.The material of the gate medium 1031 can be silicon nitride
(SiN), the growing method of the refractory material 1032 can be sputtering etc..
Preferably, the minimizing technology of grid refractory material uses etching technics.First in the gate medium on 111 surface of barrier layer
Refractory material 1032 is grown on 1031, then forms mask in area of grid, and remove the refractory material except masked areas
1032 and gate medium 1031, it finally removes mask and forms grid 103.The mask being etched when refractory material 1032 etches
Rate is less than the etch rate of refractory material 1032.The gate medium 1031 can reduce the leakage current of grid 103.
Optionally, the minimizing technology of grid refractory material can also be stripping technology.It can be to avoid quarter using stripping technology
Barrier layer damages caused by being etched in etching technique.
In the present embodiment, since grid 103 uses refractory material, low-resistance region 104 and source electrode are being subsequently formed
108 and drain electrode 109 during, avoid caused by high annealing grid knot and degenerate, to improve device yield rate and can
By property.
As illustrated in figure 3f, it is masking with the grid 103, is formed in 103 both sides of the grid by self-registered technology low
Resistance area 104, and form Resistance 112, active area 106 and barrier region 107.
Wherein, the low-resistance region 104 has doping particle, in order to reduce low-resistance region 104 and 103 short circuit of grid
Possibility, and reduce the leakage current between low-resistance region 104 and grid 103, the concentration that particle is adulterated in low-resistance region 104 exists
The peak value of vertical direction is located at and the corresponding part of the active area 106 or part corresponding with the barrier region 107.
It is respectively formed source electrode 108 and drain electrode 109 on the low-resistance region of the grid both sides, is formed as shown in Figure 1
HEMT device.
As shown in figure 4, Fig. 4 show the embodiment of the present invention one provide HEMT device manufacturing method in low-resistance region mix
The curve synoptic diagram of miscellaneous particle concentration, dotted line 1 indicates the concentration of doping particle in low-resistance region 104 at the peak of vertical direction in figure
Value is located at part corresponding with active area 106, and solid line 2 indicates the concentration of doping particle in low-resistance region 104 in vertical direction
Peak value is located at part corresponding with barrier region 107.For low resistance region the width of vertical direction can be according to specific requirements
It is adjusted, this, which is those skilled in the art, to realize.
In order to form such low-resistance region 104, in one example, step S15 includes：
Step S151, the region of 103 both sides of grid is doped using ion implantation, wherein doped chemical can be
Si, whole doping concentration is 1 × 1019cm-3Magnitude.Wherein in doping depth to active area 106 or barrier region 107, it is doped area
Domain forms low-resistance region 104 (as illustrated in figure 3f), and undoped barrier layer, barrier layer and active layer are respectively formed Resistance
112, barrier region 107 and active area 106, and wherein it is described doping particle concentration vertical direction peak value be located at it is described
106 corresponding part of active area or part corresponding with the barrier region 107, this can by adjust Doped ions distribution come
It realizes, such as forms Gaussian Profile, the peak value of Gaussian Profile corresponds to active area 106 or barrier region 107.
Since barrier layer 111 is non-crystalline material, the region of 103 both sides of grid is doped using ion implantation to be formed
When low-resistance region 104, barrier layer 111 reduces channelling effect of the injection ion in barrier layer and active layer, so as to more
Accurately control injection ion distribution.
In this example, in order to further decrease the possibility of low-resistance region 104 and 103 short circuit of grid, and reduce low electricity
The leakage current between area 104 and grid 103 is hindered, before the region to 103 both sides of grid is doped, the method is also wrapped
It includes：
Step S150, it is masking with grid 103, removes barrier layer and the part thickness of grid 103 both sides whole thickness
Barrier layer (as shown in Figure 5 a), or the barrier layer 102 of removal grid both sides whole thickness barrier layer 111 and whole thickness is to reveal
Go out the active layer 101 (as shown in Figure 5 b), or the gesture on the barrier layer 111 and whole thickness of removal grid both sides whole thickness
The active layer 101 (as shown in Figure 5 c) of barrier layer 102 and part thickness, the part that is not removed form Resistance 112, active
Area 106 and barrier region 107.In this way, the low-resistance region 104 formed has segment distance in the vertical direction with grid 103, may be implemented
Above-mentioned purpose.
Have when being doped to form low-resistance region 104 to the region of 103 both sides of grid using ion injection method following
Obvious advantage：First, ion implantation technology is relatively ripe, and cost is relatively low；Secondly ion implantation technology need not etch
And regrowth, reduce processing step, reduce technology difficulty, improves the reliability and stability of technique.
In the present embodiment, using grid as masking, low-resistance region is formed by self-registered technology, can effectively be contracted
Short grid source away from grid leak away from, and be not necessarily to alignment, it is simple for process.As shown in Figure 1, the low-resistance region 104 in 103 both sides of grid
On be respectively formed source electrode 108 and drain electrode 109.
When being doped to form source and drain low-resistance region 104 to the region of 103 both sides of grid using ion implantation,
It needs to consider two aspects when annealing, is on the one hand to activate highly doped impurity to form 104 required annealing of low-resistance region
On the other hand condition is that low-resistance region 104 forms the good required annealing item of Ohmic contact with source electrode 108 and drain electrode 109
Part.Preferably, annealing temperature is less than the fusing point of grid refractory material.
Wherein, the source electrode 108 and drain electrode 109 are formed to be respectively greater than source area and leakage apart from the lateral distance of grid
Lateral distance of the polar region apart from grid.
In the present embodiment, low-resistance region is formed in grid both sides using using ion implantation technology, then in low-resistance region
On be respectively formed source electrode and drain electrode, effectively improve the ohmic contact characteristic of source-drain electrode, reduce ohmic contact resistance, from
And improve the high frequency performance of device.
The manufacturing method of HEMT device and HEMT device that the embodiment of the present invention one provides, has by source and drain self-registered technology
Effect ground shorten grid source away from grid leak away from, reduce grid source series resistance and grid leak series resistance, improve device high frequency spy
Property；And accurate alignment need not be carried out when low-resistance region formation, the requirement to photoetching process alignment precision is reduced, improves
The yield rate of device reduces production cost, by increasing barrier layer between barrier layer and grid, can reduce barrier layer
Etch damage, and channelling effect when can reduce ion implanting, to the distribution of preferably control injection ion.Further,
In a preferred embodiment of the invention, grid avoids grid knot caused by Ohmic contact high annealing using refractory material and degenerates,
Improve the yield rate and reliability of device；Source and drain is highly doped or source and drain regrowth process effectively improves source-drain electrode
Ohmic contact characteristic reduces ohmic contact resistance, so as to improve the high frequency performance of device.
Embodiment two
Fig. 6 is the sectional view of the structure of HEMT device provided by Embodiment 2 of the present invention, as shown in Figure 6.In Fig. 6 and Fig. 1
Identical element is presented with like reference characters.
The structure of shown HEMT device includes：Substrate 100；Buffer layer 110 is formed on substrate 100；Active area 106,
It is formed on buffer layer 110；Barrier region 107 is formed on active area 106；Resistance 112 is formed on barrier region 107,
Grid 103 is formed on Resistance 112；Grid curb wall 113 and 114 is located at 103 both sides of grid；Low-resistance region 104,
103 both sides of grid are formed in, it is masking that wherein low-resistance region 104, which is with grid 103, is formed by self-registered technology, and
The low-resistance region 104 have doping particle, it is described doping particle concentration vertical direction peak value be located at it is described active
106 corresponding part of area or part corresponding with the barrier region 107；And source electrode 108 and drain electrode 109, be respectively formed at
On the low-resistance region 104 of 103 both sides of grid.
In the following, realizing that the manufacturing method of above-mentioned HEMT device elaborates to the present invention.
Fig. 7 shows the flow chart of the manufacturing method of HEMT device provided by Embodiment 2 of the present invention, as shown in fig. 7, institute
The manufacturing method for stating HEMT device includes：
Step S21, buffer layer is formed on substrate；
Step S22, active layer is formed on the buffer layer；
Step S23, barrier layer is formed on the active layer；
Step S24, barrier layer is formed on the barrier layer；
Step S25, grid is formed on the barrier layer；
Step S26, grid curb wall is formed on the grid both sides or the grid both sides and grid；
Step S27, with the grid be masking, by self-registered technology the grid both sides formed low-resistance region and
Resistance, active area and barrier region are formed, wherein the low-resistance region has doping particle；And
Step S28, it is respectively formed source electrode and drain electrode on the low-resistance region of the grid both sides.
The embodiment of the present invention two based on above-described embodiment one, with first of embodiment one the difference is that, this
Inventive embodiments two form buffer layer 110 between substrate 100 and active layer 101, and handling in this way is advantageous in that and can drop
Lattice mismatch between low substrate 100 and active area 101, so as to improve the lattice quality of active area 101.The material of buffer layer 110
Material can be by one layer of aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1；X+y+z=1)) or multilayer InxAlyGazN (0≤x,
y,z≤1；X+y+z=1, x, y, z is different in each layer) if lamination composition or by dried layer InxAlyGazN (0≤x, y, z≤
1；X+y+z=1) with the lamination of semi-conducting material.
Specifically, buffer layer 110 may include the nucleating layer 1101 being grown on substrate 100 and be grown in nucleating layer
Transition zone 1102 on 1101.Nucleating layer 1101 is used to reduce the lattice mismatch between substrate 100 and transition zone 1102.It crosses
Cross lattice quality of the layer 1102 for improving active area 106.The lattice quality of active area 106 is better than the lattice matter of buffer layer 110
Amount, and the carrier mobility of 106 material of active area is higher than 110 material of buffer layer.
Specific preferred, buffer layer 110 can also include the transition zone 1102 being grown on substrate 100 and be grown in
(the section graph structure of HEMT device is identical as the structure in Fig. 6 in this case, in figure not for the back of the body barrier layer 1103 for crossing on layer
Show), the material of the transition zone 1102 can be by one layer of aluminium gallium nitrogen (InxAlyGazN (0≤x, y, z≤1；X+y+z=
) or multilayer InxAlyGazN (0≤x, y, z≤1 1)；X+y+z=1, x, y, z is different in each layer) if lamination composition or by
Dried layer InxAlyGazN (0≤x, y, z≤1；X+y+z=1) with the lamination of semi-conducting material, transition zone 1102, which is used to improve, to be had
The lattice quality of source region 106, if material dried layer InxAlyGazN (0≤x, y, z≤1 of the back of the body barrier layer 1103；X+y+z=
Or InxAlyGazN (0≤x, y, z≤1 1)；X+y+z=1) with the lamination of semi-conducting material, back of the body barrier layer 1103 is for improving
The confinement of 106 carrier of active area.
The embodiment of the present invention two based on above-described embodiment one, with second of embodiment one the difference is that,
After grid 103 is formed, grid curb wall 114 and 113 is formed on 103 both sides of grid or 103 both sides of grid and grid 103.
The material of grid curb wall 113 and 114 is insulating materials, can be silicon nitride, aluminium oxide or silica etc., Ke Yiyong
It is short-circuit with grid 103 to further avoid low-resistance region 104, and reduce the leakage current between low-resistance region 104 and grid 103,
Grid curb wall 113 and 114 can further improve the breakdown characteristics of device and reduce gate leakage current.
It is specific preferred, it forms grid curb wall 114 and 113 in 103 both sides of grid and may include：After forming grid 103
Second dielectric layer is formed on device, is then carried out photoetching in device surface, is with photoresist covered grid 103 and side wall 114 and 113
Lid, the horizontal width of side wall 114 and 113 can be controlled by the cover of photoresist, then etched away and are not photo-etched glue cover
Second dielectric layer finally removes photoresist and etches away the second dielectric layer of 103 top of grid, then can form horizontal width can
With freely regulated side wall 114 and 113.Optionally, after removing above-mentioned photoresist, can not the top of etching grid 103 second
Dielectric layer, i.e. side wall 114 and 113 can be formed on the both sides and the grid 103 of grid 103.
Preferably, the lateral dimension close to the side wall 114 of 109 sides of drain electrode is more than the side wall 113 close to 108 side of source electrode
Lateral dimension.The grid leak of device can be increased away to improve the breakdown voltage of device by increasing the lateral dimension of side wall 114, and
The resistance between grid source can be reduced by reducing the lateral dimension of side wall 113, so as to improve the direct current and microwave property of device.
The embodiment of the present invention two based on above-described embodiment one, with the third of embodiment one the difference is that,
The step S26 carries out 103/ grid 103 of grid with the region of grid curb wall 113 and 114 both sides using ion injection method
Doping is when forming source and drain low-resistance region 104, the incident direction of the ion implanting not interface with barrier layer 102 and active layer 101
Vertically, but there is certain inclination angle.Schematic diagram is as shown in figure 12, that is, injects ion incidence direction and barrier layer 102 and active layer
The angle of 101 interface vertical direction along clockwise direction is α, and α's is ranging from more than or equal to 0 degree less than or equal to 40 degree.
Due to the blocking of 103/ grid curb wall 113 and 114 of the shadow effect of ion implanting and grid, drain electrode when injection
The low-resistance regions of 109 sides is not 0 with 103/ grid curb wall of grid, 114 right side lateral distance, such as length L in Figure 12, and should be away from
From can be adjusted by the inclination alpha of ion implanting.Increase 103 right sides of low-resistance region and grid of 109 sides of drain electrode laterally away from
From increase grid leak away from, so as to improve device breakdown characteristics and reduce gate leakage current.
The manufacturing method of HEMT device and HEMT device provided by Embodiment 2 of the present invention, has by source and drain self-registered technology
Effect ground shorten grid source away from grid leak away from, reduce grid source series resistance and grid leak series resistance, improve device high frequency spy
Property；And accurate alignment need not be carried out when low-resistance region formation, the requirement to photoetching process alignment precision is reduced, improves
The yield rate of device reduces production cost, by increasing barrier layer between barrier layer and grid, can reduce barrier layer
Etch damage.Further, in a preferred embodiment of the invention, grid avoids Ohmic contact high temperature using refractory material and moves back
Grid knot caused by fire is degenerated, and the yield rate and reliability of device are improved；The highly doped technique of source and drain effectively improves source and drain electricity
The ohmic contact characteristic of pole, reduces ohmic contact resistance, in addition, by increasing buffer layer, energy between substrate and active layer
The lattice mismatch between substrate and active layer is enough reduced, so as to improve the high frequency performance of device.Grid curb wall and angle-tilt ion
Injection can adjust grid source away from grid leak away from, so as to improve device breakdown characteristics and further decrease gate leakage current.
Embodiment three
Fig. 8 is the cross-sectional view of the structure for the HEMT device that the embodiment of the present invention three provides, as shown in figure 8, the present embodiment three carries
The HEMT device of confession includes：Substrate 201；Buffer layer 202, the buffer layer 202 are formed on substrate 201；Active area 210, this has
Source region 210 is formed on buffer layer 202；Barrier region 211, the barrier region 211 are formed on active area 210；Resistance 212, should
Resistance 212 is formed on barrier region 211；Grid 206, the grid 206 are formed on Resistance 212；Grid curb wall 215
With 216, which is formed in 206 both sides of grid or is formed on 206 both sides of grid and grid 206；Low electricity
Area 207 is hindered, 203 both sides of grid are formed in, wherein it is masking that low-resistance region 207, which is with grid 206, passes through self-registered technology shape
At, and the low-resistance region 207 has doping particle；Source electrode 208 and drain electrode 209, are respectively formed at 206 both sides of grid
On low-resistance region 207.
Wherein, the substrate 201 can be the suitable lifes such as sapphire (Sapphire), SiC, GaN, Si or rare earth oxide
The material of growth of III-V compounds of group, particularly preferably, the material of substrate 201 is GaN.
Wherein, if 202 material of the buffer layer is (0≤x, y, z≤1 dried layer InxAlyGazN；X+y+z=1) or
InxAlyGazN(0≤x,y,z≤1；X+y+z=1) with the lamination of other semi-conducting materials.Particularly preferably, buffer layer 202 wraps
The back of the body barrier layer 2022 for including the transition zone 2021 being grown on substrate 201 and being grown on transition zone 2021；Transition zone
If 2021 be (0≤x, y, z≤1 dried layer InxAlyGazN；) or InxAlyGazN (0≤x, y, z≤1 x+y+z=1；X+y+z=
1) with the lamination of other semi-conducting materials；If it is (0≤x, y, z≤1 dried layer InxAlyGazN to carry on the back barrier layer 2022；X+y+z=
Or InxAlyGazN (0≤x, y, z≤1 1)；X+y+z=1) with the lamination of other semi-conducting materials, for improving raceway groove current-carrying
The confinement of son, the other media material can be semi-conducting material or insulating materials.
The active area 210 is formed on buffer layer 202, and the material of active area 210 can be several layers of aluminium gallium nitrogen
(InxAlyGazN(0≤x,y,z≤1；)) or InxAlyGazN (0≤x, y, z≤1 x+y+z=1；X+y+z=1) with other half
The lamination of conductor material, specifically, the material of active area 210 is GaN, and the lattice quality of active area 210 is better than 202 material of buffer layer
Material, and the carrier mobility of 210 material of active area is higher than 202 material of buffer layer.
The barrier region 211 is formed on active area 210, if barrier region 211 be dried layer can be with the active area 210
If formed hetero-junctions semi-conducting material or dried layer can with the active area materials formed hetero-junctions semi-conducting material with absolutely
The lamination of edge material, the semi-conducting material such as InxAlyGazN (0≤x, y, z≤1；X+y+z=1) etc., the insulating materials
Such as silicon nitride, aluminium oxide or silica or hafnium oxide.
The Resistance 212 is formed on barrier region 211, and the material of Resistance 212 is the etching grid refractory material moment
It loses etch rate when rate is less than the material or etching grid refractory material of grid refractory material and is far below grid refractory material
Material and other semi-conducting materials or insulating materials lamination；206 refractory material of the grid refers to that the fusing point of the material is high
The material of source and drain annealing temperature in manufacturing process of the present invention, etch rate is far below grid when the etching grid refractory material
The material of refractory material can be InxAlyGazN (0≤x, y, z≤1；X+y+z=1) etc., other semi-conducting materials can
Think InxAlyGazN (0≤x, y, z≤1；X+y+z=1) etc., the insulating materials can be silicon nitride, aluminium oxide or dioxy
SiClx or hafnium oxide etc..
Specifically, in the embodiment of the present invention three, Resistance 212 includes the anti-etching area being grown on barrier region 211
2121 and the first medium area 2122 that is grown in anti-etching area 2121；The material in anti-etching area 2121 is in etching grid material
Etch rate be less than grid material in it is one or more, for protecting barrier region 211 not etched in etching grid material
It influences；First medium area 2122 is insulating materials, can be silicon nitride, aluminium oxide or silica or hafnium oxide etc., be used for
Reduce the leakage current of grid 206.
Wherein, the grid 206 is formed on Resistance 212, and grid 206 can be conductivity gate, can also be it
He forms the grid of non-ohmic contact with barrier region, and 206 material of the grid is refractory material.206 material of the grid can be with
If for refractory material or refractory conductive material and dried layer InxAlyGazN (0≤x, y, z≤1；) or dielectric material x+y+z=1
Lamination.The refractory material refers to fusing point when forming Ohmic contact higher than low-resistance region 207 and drain electrode 209 and source electrode 208
Annealing temperature.The dielectric material can be silicon nitride, aluminium oxide or silica or hafnium oxide etc., 206 infusibility material of grid
Expect optional material selected from one or more in the following group：Tungsten (W), molybdenum (Mo), tantalum (Ta), titanium, chromium and tantalum nitride；Or it is
The nitride of material in described group；Either for the alloy of the material in described group or be material in described group lamination；Or
Person be described group in material or described group in material nitride or described group in material alloy lamination；Or it is
The alloy of material in the nitride of material in described group or the material in described group or described group or the lamination of insulating materials,
The insulating materials for reducing grid leakage current.Specifically, in the present embodiment, 206 material of grid can be tungsten (W) and
The lamination of molybdenum (Mo).
In the present embodiment, since grid 206 uses refractory material, low-resistance region 207 and source electrode 208 are being subsequently formed
It during drain electrode 209, avoids caused by high annealing grid knot and degenerates, to improve the yield rate of device and reliable
Property.
The grid curb wall 215 and 216 materials are insulating materials, can be SiN, SiO2, Al2O3 or HfO2Deng being used for
Grid 206 and 209 short circuit of source electrode 208 or drain electrode are prevented, and reduces the leakage current of grid 206.Specifically, in the present embodiment
In, the material of grid curb wall 215 and 216 can be SiN.
Wherein, the low-resistance region 207 is formed by self-registered technology and regrowth techniques, and low-resistance region 207, which contains, to be mixed
Foreign particle.
The source electrode 208 and drain electrode 209 are respectively formed on the low-resistance region 207 of 206 both sides of grid, source electrode 208 and leakage
The contact type of pole 209 is Ohmic contact.The annealing temperature for forming Ohmic contact is less than the fusing point of 206 refractory material of grid.Its
In, the lateral distance of the source electrode 208 and drain electrode 209 apart from grid 206 can be respectively greater than low-resistance region 207 apart from grid
206 lateral distance.
In the following, realizing that the manufacturing method of above-mentioned HEMT device elaborates to the present invention.
Fig. 9 shows the flow chart of the manufacturing method for the HEMT device that the embodiment of the present invention three provides, as shown in Fig. 9, institute
The manufacturing method for stating HEMT device includes：
Step S31, buffer layer 202 is formed on substrate 201；
Step S32, active layer 203 is formed on buffer layer 202；
Step S33, barrier layer 204 is formed on active layer 203；
Step S34, barrier layer 205 is formed on barrier layer 204；
Step S35, grid 206 is formed on barrier layer 205；
Step S36, grid curb wall 215 and 216 is formed on 206 both sides of grid or 206 both sides of grid and grid 206；
Step S37, it is masking with grid 206, the region of 206 both sides of grid is performed etching, 206 both sides of removal grid is complete
The barrier layer 204 of the barrier layer 205 of portion's thickness and whole thickness is to expose active layer 203, or 206 both sides of removal grid whole
The barrier layer 205 of thickness and whole barrier layers 204 of thickness and the active layer 203 of part layer thickness, the blocking not being removed
Layer 205, barrier layer 204 and active layer 203 are respectively formed Resistance 212, barrier region 211 and active area 210；
Step S38, it is regrowed with doping particle in the region of 206 both sides of grid etched using regrowth techniques
Semi-conducting material, formed low-resistance region 207；
Step S39, source electrode 208 and drain electrode 209 are respectively formed on the low-resistance region 207 of 206 both sides of grid.
Figure 10 a- Figure 10 g show the corresponding knot of each step of manufacturing method for the HEMT device that the embodiment of the present invention three provides
Structure sectional view.
As shown in Figure 10 a, show that step S31 is to step S34 in the embodiment of the present invention three in Figure 10 a, i.e., in substrate 201
On sequentially form active layer 203, barrier layer 204 and barrier layer 205.
If the buffer layer 202 is (0≤x, y, z≤1 dried layer InxAlyGazN；) or InxAlyGazN (0 x+y+z=1
≤x,y,z≤1；X+y+z=1) with the lamination of other semi-conducting materials.
Specifically, in the present embodiment, step S31 forms buffer layer 202 on substrate 201 and may include on substrate 201
Transition zone 2021 is grown, forms back of the body barrier layer 2022 on transition zone 2021.Transition zone 2021 is for improving active layer 203
Crystal quality；Back of the body barrier layer is used to improve the confinement of channel carrier.
It includes but not limited to chemical vapor deposition (CVD), hydride that the method for active layer 203 is formed on buffer layer 202
Vapour phase epitaxy (HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) etc..
If the barrier layer 204 is the semi-conducting material or several that dried layer can form hetero-junctions with the active layer 203
Layer can form the lamination of the semi-conducting material and insulating materials of hetero-junctions, the semiconductor material with 203 material of the active layer
Material such as InxAlyGazN (0≤x, y, z≤1；X+y+z=1) etc., the insulating materials such as silicon nitride, aluminium oxide or silica
Or hafnium oxide etc..The method for forming barrier layer includes but not limited to chemical vapor deposition (CVD), hydride gas-phase epitaxy
(HVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE) etc..
Specifically, in the present embodiment, barrier layer 205 is formed on barrier layer 204 may include：The shape on barrier layer 204
At etch-resistant layer 2051, first medium layer 2052 is formed in etch-resistant layer 2051.The material of etch-resistant layer 2051 is in etching grid
Etch rate is less than one or more in grid material when the material of pole, for protecting barrier layer 204 in etching grid material
It is not influenced by etching；The material of first medium layer 2052 is insulating materials, can be silicon nitride, aluminium oxide or silica or two
Hafnium oxide etc., for reducing gate leakage current.Specifically preferred, 205 material of barrier layer is aluminium nitride in the present embodiment.
Handling in this way is advantageous in that in 206 material of etching grid the barrier layer 204 is protected to be not etched influence.
As shown in fig. lob, refractory material is grown on barrier layer 205 form grid 206.Grid 206 can be Schottky
Grid can also be the grid that other form non-ohmic contact with barrier region.
When the fusing point of the refractory conductive material higher than utilizing regrowth process to form low-resistance region in the steps afterwards
Impurity annealing activationary temperature and the annealing temperature when low-resistance region and source electrode and drain electrode form Ohmic contact.
Preferably, the minimizing technology of grid refractory material is using etching technics.First one is grown on 205 surface of barrier layer
Then layer tungsten/molybdenum lamination forms mask in area of grid, uses sulfur hexafluoride (SF6) get rid of tungsten/molybdenum except masked areas
Lamination, to form grid 206.Due to SF6Etch rate to barrier layer 205AlN is much larger than to the etch rate of tungsten/molybdenum,
Protect barrier layer 204 not by SF in barrier layer 2056Etching influences.
Optionally, the minimizing technology of grid refractory material can also be stripping technology.It can be to avoid quarter using stripping technology
Barrier layer damages caused by being etched in etching technique.
As shown in Figure 10 c and Figure 10 d, after grid 206 is formed, it is situated between in the surface growth regulation two of barrier layer 205 and grid 206
Matter layer 213, then removal is except the second dielectric layer of gate edge, and to form grid curb wall 215 and 216, second dielectric layer is
Insulating materials can be SiN, SiO2, Al2O3 or HfO2 etc..Grid curb wall 215 and 216 is for preventing grid 206 and source electrode
209 or 210 short circuit of drain electrode, and reduce the leakage current of grid 206.
As illustrated in figure 10e, it is masking with grid 206 and grid curb wall 215 and 216, the region of 206 both sides of grid is carried out
Etching, removes the barrier layer 205 of 206 both sides whole thickness of grid and the barrier layer 204 of whole thickness to expose active layer 203,
Or remove barrier layer 205 and whole barrier layers 204 of thickness and the having for part layer thickness of 206 both sides whole thickness of grid
Active layer 203, the barrier layer 205 not being removed, barrier layer 204 and active layer 203 are respectively formed Resistance 212,211 and of barrier region
Active area 210.
As shown in figure 10f, it is regrowed with doping in the region of 206 both sides of grid etched using regrowth techniques
The semi-conducting material of particle forms low-resistance region 207.
The semi-conducting material with doping particle can be (0≤x, y, z≤1 InxAlyGazN；X+y+z=1) or
The lamination of other semi-conducting materials or these semi-conducting materials.Wherein doped chemical can be Si, whole doping concentration 1 ×
1019cm-3Magnitude.
In this example, in order to further decrease the short-circuit possibility of low-resistance region 207 and grid 206, and reduce low resistance
Leakage current between area 207 and grid 206 is carrying out semi-conducting material of the regrowth with doping particle to low-resistance region 207
When so that they towards 206 side of grid surface A less than the Resistance 212 the surface B towards gate electrode side (such as Figure 11 institutes
Show).
As shown in Figure 10 g, source electrode 208 and drain electrode 209 are respectively formed on the low-resistance region 207 of 206 both sides of grid.
Source electrode 208 and the contact type of drain electrode 209 are Ohmic contact, form the annealing temperature needed for Ohmic contact and are less than grid
The fusing point of 206 refractory material of pole.
The manufacturing method of HEMT device and HEMT device that the embodiment of the present invention three provides, has by source and drain self-registered technology
Effect ground shorten grid source away from grid leak away from, reduce grid source series resistance and grid leak series resistance, improve device high frequency spy
Property；And accurate alignment need not be carried out when low-resistance region formation, the requirement to photoetching process alignment precision is reduced, improves
The yield rate of device reduces production cost, by increasing barrier layer between barrier layer and grid, can reduce barrier layer
Etch damage.Further, in a preferred embodiment of the invention, grid avoids Ohmic contact high temperature using refractory material and moves back
Grid knot caused by fire is degenerated, and the yield rate and reliability source and drain regrowth process for improving device effectively improve source-drain electrode
Ohmic contact characteristic, ohmic contact resistance is reduced, so as to improve the high frequency performance of device.
The foregoing is merely the preferred embodiment of the present invention, are not intended to restrict the invention, for those skilled in the art
For, the present invention can have various modifications and changes.Each embodiment of the present invention can phase on the basis of not violating logic
Mutually combination.All any modification, equivalent replacement, improvement and so within spirit and principles of the present invention should be included in this
Within the protection domain of invention.
Claims (15)
1. a kind of HEMT device, which is characterized in that including：
Substrate；
Active area is formed on the substrate；
Barrier region is formed on the active area；
Resistance is formed on the barrier region；
Grid is formed on the Resistance；
Low-resistance region is respectively formed at the grid both sides, wherein it is masking that the low-resistance region, which is with the grid, is passed through
What self-registered technology was formed, and the low-resistance region has doping particle, and the concentration of the doping particle is in vertical direction
Peak value be located at part corresponding with the active area other than Resistance corresponding part described in the low-resistance region or with it is described
The corresponding part in barrier region；And
Source electrode and drain electrode is respectively formed on the low-resistance region of the grid both sides；
The material of the grid is refractory material；
It is one or more in the Resistance material to be eclipsed etching speed less than in the grid material in the grid etch
The rate that is etched of one or more materials；
Wherein, the doping particle is Si.
2. HEMT device according to claim 1, which is characterized in that the surface towards gate electrode side of the low-resistance region is low
The surface towards gate electrode side in the Resistance.
3. HEMT device according to claim 1, which is characterized in that the HEMT device further includes grid curb wall, is formed
In the grid both sides or it is formed on the grid both sides and the grid.
4. HEMT device according to claim 1, which is characterized in that the HEMT device further includes gate medium, is formed in
Between the Resistance and the grid.
5. HEMT device according to claim 1, which is characterized in that the barrier region is the material shape with the active area
At the semiconductor material layer of hetero-junctions；Or it is
The lamination of semi-conducting material and insulating materials formed thereon.
6. HEMT device according to claim 1, which is characterized in that the HEMT device further includes buffer layer, is formed in
Between the substrate and the active area, for reducing the lattice mismatch between substrate and active area.
7. HEMT device according to claim 1, which is characterized in that the refractory material selected from in the following group one kind or
It is a variety of：Tungsten, molybdenum, tantalum, titanium and chromium；Or it is
The nitride of material in described group；Or it is
The alloy of material in described group；Or it is
The lamination of material in described group；Or it is
The lamination of the alloy of material in the nitride of material in described group or the material in described group or described group；Or it is
The alloy of material in the nitride of material in described group or the material in described group or described group or insulating materials
Lamination.
8. HEMT device according to claim 1, the Resistance include：
Anti-etching area is formed on the barrier region, for reducing etching etching injury caused by the barrier layer；
First medium area is formed in the anti-etching area；
The one or more materials that etching speed is preferably less than in the grid material that are eclipsed of anti-etching area's material are eclipsed
The rate at quarter；
The material in the first medium area is insulating materials.
9. HEMT device according to claim 3, width of the grid curb wall in grid source and grid leak direction is adjusted,
And the width of grid leak side grid curb wall is not less than the width of grid source side grid curb wall.
10. a kind of method of manufacture HEMT device, which is characterized in that including step：
S1, active layer is formed on substrate；
S2, barrier layer is formed on the active layer；
S3, barrier layer is formed on the barrier layer；
S4, grid is formed on the barrier layer；
S5, with the grid it is masking, is formed in the grid both sides by self-registered technology and low-resistance region and form blocking
Area, active area and barrier region, wherein the low-resistance region has doping particle；And
S6, the low-resistance region in the grid both sides are respectively formed source electrode and drain electrode；
Wherein, the material of the grid is refractory material；
It is one or more in the Resistance material to be eclipsed etching speed less than in the grid material in the grid etch
The rate that is etched of one or more materials；
Wherein, the concentration of the doping particle is located at Resistance described in the low-resistance region in the peak value of vertical direction and corresponds to portion
And the corresponding part of active area or part corresponding with the barrier region other than point；
Wherein, the doping particle is Si.
11. the method for manufacture HEMT device according to claim 10, which is characterized in that step S5 includes：
The region of grid both sides is doped, wherein in doping depth to active area or barrier region, be doped region formed it is low
Resistance area, undoped barrier layer, barrier layer and active layer are respectively formed the Resistance, barrier region and active area, and
Wherein it is described doping particle concentration the peak value of vertical direction be located at part corresponding with the active area or with the potential barrier
The corresponding part in area.
12. the method for manufacture HEMT device according to claim 11, which is characterized in that the regions of grid both sides into
Before row doping, the method further includes：
It is masking, the barrier layer on the barrier layer and part thickness of removal grid both sides whole thickness, or removal grid with grid
The barrier layer of the barrier layer of both sides whole thickness and whole thickness is to expose the active layer, or removal grid both sides whole layer
Thick barrier layer and whole barrier layers of thickness and the active layer of part thickness.
13. the method for manufacture HEMT device according to claim 10, which is characterized in that step S5 includes：
It is masking with grid, the barrier layer of removal grid both sides whole thickness and the barrier layer of whole thickness are described active to expose
Layer, or the barrier layer of removal grid both sides whole thickness and whole barrier layers of thickness and the active layer of part thickness；Not
Barrier layer, barrier layer and the active layer being removed are respectively formed the Resistance, barrier region and active area；
Region growing in grid both sides carries the semi-conducting material of doping particle, forms low-resistance region.
14. the method for manufacture HEMT device according to claim 10, which is characterized in that the method is in step S4 and S5
Between further include：Grid curb wall is formed on the grid both sides or the grid both sides and grid, the grid curb wall is in grid
The width in source and grid leak direction is adjusted, and the width of grid leak side grid curb wall is not less than the width of grid source side grid curb wall
Degree.
15. the method for manufacture HEMT device according to claim 11, which is characterized in that using ion injection method to grid
When the region of pole both sides is doped, ion implanting direction and barrier layer and active layer interface vertical direction are along clockwise direction
Angle is more than or equal to 0 degree, and is less than or equal to 40 degree.
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| JP7099255B2 (en) | 2018-11-01 | 2022-07-12 | 富士通株式会社 | Compound semiconductor equipment, high frequency amplifier and power supply equipment |
| CN109817710A (en) * | 2018-12-29 | 2019-05-28 | 英诺赛科（珠海）科技有限公司 | High electron mobility transistor and its manufacturing method |
| CN111081764A (en) * | 2019-12-30 | 2020-04-28 | 深圳第三代半导体研究院 | Transistor with embedded source and drain and preparation method thereof |
| CN111415987B (en) * | 2020-04-09 | 2020-12-29 | 浙江大学 | Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof |
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| JPH0691249B2 (en) * | 1991-01-10 | 1994-11-14 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Modulation-doped MISFET and manufacturing method thereof |
| WO2002052652A1 (en) * | 2000-12-26 | 2002-07-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and its manufacturing method |
| US7556976B2 (en) * | 2002-10-25 | 2009-07-07 | The University Of Connecticut | Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation |
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| US8936976B2 (en) * | 2009-12-23 | 2015-01-20 | Intel Corporation | Conductivity improvements for III-V semiconductor devices |
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| CN102945859A (en) * | 2012-11-07 | 2013-02-27 | 电子科技大学 | GaN heterojunction HEMT (High Electron Mobility Transistor) device |
| US9018056B2 (en) * | 2013-03-15 | 2015-04-28 | The United States Of America, As Represented By The Secretary Of The Navy | Complementary field effect transistors using gallium polar and nitrogen polar III-nitride material |
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