JP7099255B2 - Compound semiconductor equipment, high frequency amplifier and power supply equipment - Google Patents

Description

The present invention relates to a compound semiconductor device, a high frequency amplifier and a power supply device.

Nitride semiconductors have features such as high saturated electron velocities and wide band gaps. Therefore, various studies have been made on applying a nitride semiconductor to a semiconductor device having a high withstand voltage and a high output by utilizing these characteristics. For example, the bandgap of GaN, which is a kind of nitride semiconductor, is 3.4 eV, which is larger than the bandgap of Si (1.1 eV) and the bandgap of GaAs (1.4 eV). Therefore, GaN has a high breaking electric field strength and is extremely promising as a material for a semiconductor device for a power source that obtains high voltage operation and high output.

As a semiconductor device using a nitride semiconductor, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in the GaN-based HEMT, AlGaN / GaN-HEMT using GaN as an electron traveling layer (channel layer) and AlGaN as an electron supply layer is attracting attention. In AlGaN / GaN-HEMT, distortion due to the difference in lattice constant between GaN and AlGaN occurs in AlGaN. Then, a high-concentration two-dimensional electron gas (2DEG) is obtained by the piezo polarization generated by this strain and the spontaneous polarization of AlGaN. Therefore, AlGaN / GaN-HEMT is expected as a high-efficiency switch element, a high withstand voltage power device for electric vehicles, and the like.

A GaN-based HEMT using GaN having such a high breaking electric field strength is also promising as a transistor operating at a high frequency. Especially in high frequency applications, it is important to reduce the contact resistance at the interface between the metal source electrode and drain electrode and the nitride semiconductor layer. Therefore, in order to reduce the contact resistance, the carrier supply layer is removed in advance by dry etching or the like directly under the source electrode and the drain electrode, and a low resistance GaN layer doped with a high concentration donor impurity is provided in that portion. A technique has been proposed in which the electron traveling layer is formed so as to be in contact with the electronic traveling layer. According to this technique, since the source electrode and the drain electrode are in contact with the low resistance GaN layer instead of the AlGaN electron supply layer having a large band gap, the contact resistance can be reduced.

In order to improve the high frequency characteristics, it is effective not only to reduce the contact resistance but also to shorten the gate length. However, if the gate length is shortened, the off-leakage current tends to flow. An increase in off-leakage current leads to a decrease in withstand voltage.

Japanese Patent Publication No. 2007-538402 Japanese Unexamined Patent Publication No. 2016-115931 Japanese Unexamined Patent Publication No. 2006-134935

An object of the present disclosure is to provide a compound semiconductor device, a high frequency amplifier and a power supply device capable of reducing an off-leakage current while obtaining excellent high frequency characteristics.

According to one embodiment of the present disclosure, the nitride semiconductor laminated structure has a nitride semiconductor laminated structure and a source electrode, a gate electrode and a drain electrode formed above the nitride semiconductor laminated structure, and the nitride semiconductor laminated structure has a structure. A second nitride semiconductor layer of aluminum nitride or gallium nitride having a first lattice constant and a second nitride semiconductor layer formed above the first nitride semiconductor layer and larger than the first lattice constant. On the first nitride semiconductor layer so as to sandwich the second nitride semiconductor layer of gallium nitride or aluminum gallium nitride having the lattice constant of the above and the second nitride semiconductor layer in plan view. It has a third nitride semiconductor layer and a fourth nitride semiconductor layer of n-type gallium nitride formed in, and the third nitride semiconductor layer and the fourth nitride semiconductor layer are The n-type impurity contains silicon, germanium or oxygen or any combination thereof, and the first nitride semiconductor in the thickness direction in the third nitride semiconductor layer and the fourth nitride semiconductor layer. The closer to the interface with the layer, the higher the concentration of silicon and the lower the concentration of germanium and / or oxygen, the third lattice constant of the third nitride semiconductor layer and the fourth nitride semiconductor. The fourth lattice constant of the layer becomes closer to the first lattice constant as it approaches the interface with the first nitride semiconductor layer in the thickness direction, and the gate electrode is the second nitride semiconductor layer. The source electrode is formed on the third nitride semiconductor layer, and the drain electrode is provided on the compound semiconductor device formed on the fourth nitride semiconductor layer. ..

According to the present disclosure, the off-leakage current can be reduced while obtaining excellent high frequency characteristics.

It is sectional drawing which shows the compound semiconductor apparatus which concerns on 1st Embodiment. It is a figure which shows the distribution of the lattice constant of an n-type GaN layer. It is sectional drawing (the 1) which shows the manufacturing method of the compound semiconductor apparatus which concerns on 1st Embodiment. It is sectional drawing (the 2) which shows the manufacturing method of the compound semiconductor apparatus which concerns on 1st Embodiment. It is sectional drawing (the 3) which shows the manufacturing method of the compound semiconductor apparatus which concerns on 1st Embodiment. It is sectional drawing (the 4) which shows the manufacturing method of the compound semiconductor apparatus which concerns on 1st Embodiment. It is sectional drawing which shows the compound semiconductor apparatus which concerns on 2nd Embodiment. It is a figure which shows the distribution of the concentration of the donor impurity of the n-type GaN layer. It is sectional drawing (the 1) which shows the manufacturing method of the compound semiconductor apparatus which concerns on 2nd Embodiment. It is sectional drawing (the 2) which shows the manufacturing method of the compound semiconductor apparatus which concerns on 2nd Embodiment. It is sectional drawing (the 3) which shows the manufacturing method of the compound semiconductor apparatus which concerns on 2nd Embodiment. It is sectional drawing (the 4) which shows the manufacturing method of the compound semiconductor apparatus which concerns on 2nd Embodiment. It is a figure which shows the relationship between a drain voltage and a drain current. It is sectional drawing which shows the compound semiconductor apparatus which concerns on 3rd Embodiment. It is sectional drawing which shows the compound semiconductor apparatus which concerns on 4th Embodiment. It is sectional drawing which shows the compound semiconductor apparatus which concerns on 5th Embodiment. It is sectional drawing which shows the compound semiconductor apparatus which concerns on 6th Embodiment. It is a figure which shows the discrete package which concerns on 7th Embodiment. It is a wiring diagram which shows the PFC circuit which concerns on 8th Embodiment. It is a wiring diagram which shows the power supply device which concerns on 9th Embodiment. It is a wiring diagram which shows the amplifier which concerns on 10th Embodiment.

As one of the techniques for reducing the off-leakage current in the GaN-based HEMT, it is conceivable to form a thin electron traveling layer of GaN and provide a back barrier layer of aluminum nitride (AlN) under the electron traveling layer. However, when this technique is combined with the technique of using a low resistance GaN layer (re-growth layer) to reduce the above contact resistance, etching for removing the electron supply layer is stopped in the thin electron traveling layer. Is difficult. When the etching is stopped in the back barrier layer, the regrowth layer grows from the back barrier layer of AlN instead of the electron traveling layer of GaN. In this case, since there is a large lattice constant difference between AlN and GaN, the crystallinity of the regrowth layer tends to decrease, and the surface of the regrowth layer tends to be rough. As a result, a sufficiently low contact resistance cannot be obtained even though the regrowth layer is used.

The present inventors have made diligent studies to appropriately combine the technique of using the regrowth layer and the technique of using the back barrier layer in order to reduce the off-leakage current while obtaining excellent high-frequency characteristics. As a result, the following embodiments were conceived.

Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In the present specification and the drawings, components having substantially the same functional configuration may be designated by the same reference numerals to omit duplicate explanations.

(First Embodiment)
First, the first embodiment will be described. The first embodiment relates to a compound semiconductor device including a GaN-based HEMT. FIG. 1A is a cross-sectional view showing a compound semiconductor device according to the first embodiment.

As shown in FIG. 1A, the compound semiconductor device 100 according to the first embodiment has a nitride semiconductor laminated structure 190, a source electrode 1s formed above the nitride semiconductor laminated structure 190, a gate electrode 1g, and a drain electrode. It has 1d and. The nitride semiconductor laminated structure 190 has an aluminum nitride (AlN) or aluminum nitride gallium (AlGaN) back barrier layer 120 having a first lattice constant. The nitride semiconductor laminated structure 190 further comprises a gallium nitride (GaN) or AlGaN electron traveling layer 130 formed above the back barrier layer 120 and having a second lattice constant larger than the first lattice constant. Have. The nitride semiconductor laminated structure 190 further includes n-type GaN layers 160s and n-type GaN layers 160d containing donor impurities formed on the back barrier layer 120 so as to sandwich the electron traveling layer 130 in a plan view. Have. The nitride semiconductor laminated structure 190 further has an electron supply layer 150 of AlGaN or indium aluminum gallium nitride (InAlGaN) formed above the electron traveling layer 130. The band gap of the electron supply layer 150 is larger than the band gap of the electron traveling layer 130, and two-dimensional electron gas (2DEG) is generated in the vicinity of the surface of the electron traveling layer 130. The back barrier layer 120 is an example of a first nitride semiconductor layer, the electron traveling layer 130 is an example of a second nitride semiconductor layer, and the electron supply layer 150 is an example of a sixth nitride semiconductor layer. .. The n-type GaN layer 160s is an example of a third nitride semiconductor layer, and the n-type GaN layer 160d is an example of a fourth nitride semiconductor layer.

For example, the lower surface of the electron traveling layer 130 is in contact with the upper surface of the back barrier layer 120, and the interface between the back barrier layer 120 and the electron traveling layer 130 is the interface between the back barrier layer 120 and the n-type GaN layer 160s and the back barrier. It is located above the interface between the layer 120 and the n-type GaN layer 160d.

FIG. 1B is a diagram showing the distribution of the lattice constants of the n-type GaN layers 160s and 160d. The horizontal axis of FIG. 1B shows the lattice constant, and the vertical axis shows the distance from the interface with the back barrier layer 120 in the thickness direction. Here, the thickness of the n-type GaN layers 160s and 160d is t.

Since the n-type GaN layers 160s and 160d contain donor impurities, their lattice constants depend on the type and concentration of the donor impurities. In the present embodiment, as shown in FIG. 1B, the lattice constant of the n-type GaN layer 160s (third lattice constant) and the lattice constant of the n-type GaN layer 160d (fourth lattice constant) are in the thickness direction. The closer to the interface with the back barrier layer 120, the closer to the lattice constant (first lattice constant) of the back barrier layer 120. For example, the lattice constants of the n-type GaN layers 160s and 160d are _AB on their lower surface (interface with the back barrier layer 120), _AT on their upper surface, and the lattice is closer to the upper surface from the lower surface. The constant is large. For example, the lattice constant _AT on the upper surface is the closest to the lattice constant of GaN in the n-type GaN layers 160s and 160d. Further, the lattice constant of GaN is larger than the lattice constant of AlN or AlGaN. Therefore, the lattice constants _AB on the lower surfaces of the n-type GaN layers 160s and 160d are larger than the lattice constants of the back barrier layer 120 of AlN or AlGaN.

The gate electrode 1g is formed above the electron supply layer 150, the source electrode 1s is formed on the n-type GaN layer 160s, and the drain electrode 1d is formed on the n-type GaN layer 160d.

In the compound semiconductor device 100 configured as described above, the contact resistance between the source electrode 1s and the nitride semiconductor laminated structure 190 is low, and the contact resistance between the drain electrode 1d and the nitride semiconductor laminated structure 190 is low. This is because the source electrode 1s is formed on the n-type GaN layer 160s, and the drain electrode 1d is formed on the n-type GaN layer 160d. Therefore, low resistance ohmic contact can be realized. Further, since the back barrier layer 120 of AlN or AlGaN is provided below the electron traveling layer 130, the off-leakage current does not easily flow even if the gate length of the gate electrode 1g is shortened.

Further, the lattice constants of the n-type GaN layers 160s and 160d become closer to the lattice constants of the back barrier layer 120 as they approach the interface with the back barrier layer 120 in the thickness direction. That is, the difference in lattice constant between the n-type GaN layers 160s and 160d with the back barrier layer 120 is the smallest at these interfaces in the thickness direction. Therefore, the strain in the n-type GaN layers 160s and 160d due to the difference in lattice constant becomes smaller as it approaches the back barrier layer 120. Therefore, the crystallinity of the n-type GaN layers 160s and 160d is good, and the flatness of the upper surface thereof is also good.

Therefore, according to the compound semiconductor device 100, the off-leakage current can be reduced while obtaining excellent high frequency characteristics.

Next, a method for manufacturing the compound semiconductor device 100 according to the first embodiment will be described. 2A to 2D are cross-sectional views showing a method of manufacturing the compound semiconductor device according to the first embodiment.

First, as shown in FIG. 2A, a nitride semiconductor laminated structure 190 including a back barrier layer 120, an electron traveling layer 130, and an electron supply layer 150 is formed. As a result, 2DEG is generated near the surface of the electron traveling layer 130.

Next, as shown in FIG. 2B, the surface layer portions of the electron supply layer 150, the electron traveling layer 130, and the back barrier layer 120 are dry-etched in each of the region below the source electrode 1s and the region below the drain electrode 1d. Removed by. As a result, recesses 180s for the source and recesses 180d for the drain that expose the back barrier layer 120 are formed in the nitride semiconductor laminated structure 190.

Then, as shown in FIG. 2C, the n-type GaN layer 160s containing the donor impurities is formed in the recess 180s, and the n-type GaN layer 160d containing the donor impurities is formed in the recess 180d. At this time, the distribution of the lattice constant shown in FIG. 1B is obtained by adjusting the type and concentration of the donor impurities. The n-type GaN layers 160s and 160d are also included in the nitride semiconductor laminated structure 190.

Subsequently, as shown in FIG. 2D, the source electrode 1s is formed on the n-type GaN layer 160s, and the drain electrode 1d is formed on the n-type GaN layer 160d. Further, a gate electrode 1g is formed on the electron supply layer 150 between the source electrode 1s and the drain electrode 1d.

Then, if necessary, a protective film, wiring, and the like are formed to complete the compound semiconductor device 100.

In the present embodiment, when the recesses 180s and 180d are formed, not only the electron supply layer 150 and the electron traveling layer 130 but also the surface layer portion of the back barrier layer 120 is removed by dry etching. When a plurality of GaN-based HEMTs are formed on one wafer, it is difficult to align the etching stop points in the plane of the wafer even if the dry etching is stopped in the electron traveling layer 130. Therefore, it is difficult to obtain sufficient in-plane uniformity for the thickness of the electronic traveling layer 130 after etching. Since the thickness of the electron traveling layer 130 after etching affects the contact resistance, the in-plane uniformity of the contact resistance also decreases. On the other hand, when the surface layer portion of the back barrier layer 120 is also removed by dry etching as in the present embodiment, even if the etching stop point varies, the contact resistance is less likely to be affected. Therefore, the in-plane uniformity of contact resistance can be stabilized.

(Second embodiment)
Next, the second embodiment will be described. The second embodiment relates to a compound semiconductor device including a GaN-based HEMT. FIG. 3A is a cross-sectional view showing the compound semiconductor device according to the second embodiment.

As shown in FIG. 3A, the compound semiconductor device 200 according to the second embodiment is formed above the substrate 210, the nitride semiconductor laminated structure 290 formed above the substrate 210, and the nitride semiconductor laminated structure 290. It has a source electrode 1s, a gate electrode 1g, and a drain electrode 1d. The substrate 210 is, for example, an AlN substrate. The nitride semiconductor laminated structure 290 has an AlN or AlGaN back barrier layer 220 having a first lattice constant. The thickness of the back barrier layer 220 is, for example, 400 nm to 600 nm. The nitride semiconductor laminated structure 290 further has a GaN or AlGaN electron traveling layer 230 formed above the back barrier layer 220 and having a second lattice constant larger than the first lattice constant. The thickness of the electron traveling layer 230 is, for example, 10 nm to 30 nm. The nitride semiconductor laminated structure 290 further has a spacer layer 240 of AlN, AlGaN or InAlGaN formed on the electron traveling layer 230. The nitride semiconductor laminated structure 290 further has an AlGaN or InAlGaN electron supply layer 250 formed above the spacer layer 240. The band gap of the spacer layer 240 and the electron supply layer 250 is larger than the band gap of the electron traveling layer 230, and two-dimensional electron gas is generated in the vicinity of the surface of the electron traveling layer 230. The back barrier layer 220 is an example of a first nitride semiconductor layer, the electronic traveling layer 230 is an example of a second nitride semiconductor layer, and the spacer layer 240 is an example of a fifth nitride semiconductor layer. The electron supply layer 250 is an example of the sixth nitride semiconductor layer.

In the region below the source electrode 1s and the region below the drain electrode 1d, the recess 280s for the source and the recess for the drain are on the surface layers of the electron supply layer 250, the spacer layer 240, the electron traveling layer 230 and the back barrier layer 220, respectively. A recess 280d is formed. An n-type GaN layer 260s containing a donor impurity is formed in the recess 280s, and an n-type GaN layer 260d containing a donor impurity is formed in the recess 280d. The n-type GaN layer 260s and the n-type GaN layer 260d are formed on the back barrier layer 220 so as to sandwich the electron traveling layer 230, the spacer layer 240, and the electron supply layer 250 in a plan view. The n-type GaN layer 260s is an example of a third nitride semiconductor layer, and the n-type GaN layer 260d is an example of a fourth nitride semiconductor layer.

For example, the lower surface of the electron traveling layer 230 is in contact with the upper surface of the back barrier layer 220, and the interface between the back barrier layer 220 and the electron traveling layer 230 is the interface between the back barrier layer 220 and the n-type GaN layer 260s and the back barrier. It is located above the interface between the layer 220 and the n-type GaN layer 260d.

FIG. 3B is a diagram showing the distribution of the concentrations of donor impurities in the n-type GaN layers 260s and 260d. The horizontal axis of FIG. 3B shows the concentration of donor impurities, and the vertical axis shows the distance from the interface with the back barrier layer 220 in the thickness direction. Here, the thickness of the n-type GaN layers 260s and 260d is t.

In the present embodiment, the n-type GaN layers 260s and 260d contain silicon (Si) and germanium (Ge) as donor impurities. As shown in FIG. 3B, the Si concentration is highest on the lower surface (interface with the back barrier layer 220) and decreases as the distance from the interface increases. For example, the Si concentration in the vicinity of the lower surface is about 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²⁰ cm ^-3 . On the other hand, as shown in FIG. 3B, the Ge concentration is highest on the upper surface (interface with the back barrier layer 220) and decreases as it approaches the interface. For example, the Ge concentration in the vicinity of the upper surface is about 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²⁰ cm ^-3 . For example, Ge is not contained in the vicinity of the lower surface of the n-type GaN layers 260s and 260d, and Si is not contained in the vicinity of the upper surface. As described above, the closer to the interface with the back barrier layer 220 in the thickness direction, the higher the Si concentration and the lower the Ge concentration.

Si functions as a donor impurity. Further, the atomic radius (111 pm) of Si is about 82% of the atomic radius (135 pm) of Ga, and Si has a function of being added to GaN to reduce the lattice constant of GaN. Therefore, the higher the Si concentration, the smaller the difference in lattice constant between the AlN or AlGaN back barrier layer 220 and the back barrier layer 220. On the other hand, since Si distorts GaN significantly, good crystallinity may not be obtained when the Si concentration is high over the entire thickness direction.

Ge functions as a donor impurity. Further, the atomic radius (122 pm) of Ge is about 90% of the atomic radius of Ga, and even if Ge is added to GaN, it does not affect the lattice constant of GaN as much as Si. Therefore, the higher the Ge concentration, the more the contact resistance with the electrode can be reduced while suppressing the distortion of GaN.

Therefore, in the present embodiment, the lattice constants of the n-type GaN layer 260s and the n-type GaN layer 260d are the same as those of the back barrier layer 220 in the thickness direction, as in the n-type GaN layers 160s and 160d of the first embodiment. The closer to the interface, the closer to the lattice constant of the back barrier layer 220. For example, the lattice constants of the n-type GaN layers 260s and 260d increase from the lower surface to the upper surface. For example, the lattice constant on the upper surface is the closest to the lattice constant of GaN in the n-type GaN layers 260s and 260d.

The gate electrode 1g is formed above the electron supply layer 250, the source electrode 1s is formed on the n-type GaN layer 260s, and the drain electrode 1d is formed on the n-type GaN layer 260d.

In the compound semiconductor device 200 configured as described above, the contact resistance between the source electrode 1s and the nitride semiconductor laminated structure 290 is low, and the contact resistance between the drain electrode 1d and the nitride semiconductor laminated structure 290 is low. This is because the source electrode 1s is formed on the n-type GaN layer 260s, and the drain electrode 1d is formed on the n-type GaN layer 260d. Therefore, low resistance ohmic contact can be realized. Further, since the back barrier layer 220 of AlN or AlGaN is provided below the electron traveling layer 230, the off-leakage current does not easily flow even if the gate length of the gate electrode 1g is shortened.

Further, the concentration distribution of Si and Ge in the n-type GaN layers 260s and 260d is appropriate, and the lattice constant of the n-type GaN layers 260s and 260d is such that the closer to the interface with the back barrier layer 220 in the thickness direction, the more the back barrier. It is close to the lattice constant of layer 220. That is, the difference in lattice constant between the n-type GaN layer 260s and the back barrier layer 220 in the n-type GaN layer 260s and 260d is the smallest at these interfaces in the thickness direction. Therefore, the strain in the n-type GaN layers 260s and 260d due to the difference in lattice constant becomes smaller as it approaches the back barrier layer 220. Therefore, the crystallinity of the n-type GaN layers 260s and 260d is good, and the flatness of the upper surface thereof is also good.

Therefore, according to the compound semiconductor device 200, the off-leakage current can be reduced while obtaining excellent high frequency characteristics.

Next, a method for manufacturing the compound semiconductor device 200 according to the second embodiment will be described. 4A to 4D are cross-sectional views showing a method of manufacturing the compound semiconductor device according to the second embodiment.

First, as shown in FIG. 4A, a nitride semiconductor laminate including an AlN back barrier layer 220, a GaN electron traveling layer 230, an AlN spacer layer 240, and an AlGaN or InGaN electron supply layer 250 on an AlN substrate 210. Form structure 290. The nitride semiconductor laminated structure 290 can be formed by a crystal growth method such as a metal organic chemical vapor deposition (MOCVD) method and a molecular beam epitaxy (MBE) method. As a result, two-dimensional electron gas (2DEG) is generated in the vicinity of the surface of the electron traveling layer 230.

When the nitride semiconductor laminated structure 290 is formed by the MOCVD method, for example, trimethylaluminum (TMA) gas as an Al source, trimethylgallium (TMG) gas as a Ga source, and ammonia (NH ₃ ) gas as an N source. Use a mixed gas. At this time, the presence / absence and flow rate of trimethylaluminum gas and trimethylgallium gas are appropriately set according to the composition of the nitride semiconductor layer to be grown. The flow rate of ammonia gas, which is a common raw material for each nitride semiconductor layer, is, for example, about 100 ccm to 10 LM. Further, for example, the growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C. The growth temperature of the AlN layer (back barrier layer 220, spacer layer 240) may be about 1400 ° C. When forming the electron traveling layer 230 of GaN, for example, the surface of the electron traveling layer 230 can be easily flattened by lowering the growth temperature. When forming the InAlGaN layer as the spacer layer 240 or the electron supply layer 250, trimethylindium (TMI) gas is added as an In source to the mixed gas.

After forming the nitride semiconductor laminated structure 290, an element separation region defining the element region is formed. In the formation of the device separation region, for example, a photoresist pattern that exposes the region where the device separation region is to be formed is formed on the nitride semiconductor laminated structure 290, and ion implantation such as Ar is performed using this pattern as a mask. Dry etching using a chlorine-based gas may be performed using this pattern as an etching mask.

Next, as shown in FIG. 4B, in each of the region below the source electrode 1s and the region below the drain electrode 1d, the surface layers of the electron supply layer 250, the spacer layer 240, the electron traveling layer 230, and the back barrier layer 220. Remove the part. This removal can be performed, for example, by dry etching using a resist mask. As a result, recesses 280s for the source and recesses 280d for the drain that expose the back barrier layer 220 are formed in the nitride semiconductor laminated structure 290.

Then, as shown in FIG. 4C, an n-type GaN layer 260s containing Si and Ge as a donor impurity is formed in the recess 280s, and an n-type GaN layer 260d containing Si and Ge as a donor impurity is formed in the recess 280d. .. The n-type GaN layers 260s and 260d can be formed by a crystal growth method such as the MOCVD method and the MBE method. When the n-type GaN layers 260s and 260d are formed by the MOCVD method, for example, a monosilane (SiH ₄ ) gas as a Si source and a monogerman (GeH ₄ ) gas as a Ge source are mixed with a trimethylgallium gas and an ammonia gas. Add to. Then, as the n-type GaN layers 260s and 260d grow, the flow rate of the monosilane gas decreases and the flow rate of the monogerman gas increases. In this way, the distribution of the impurity concentration shown in FIG. 3B is obtained. The n-type GaN layers 260s and 260d are also included in the nitride semiconductor laminated structure 290.

Subsequently, as shown in FIG. 4D, the source electrode 1s is formed on the n-type GaN layer 260s, and the drain electrode 1d is formed on the n-type GaN layer 260d. The source electrode 1s and the drain electrode 1d can be formed by, for example, a lift-off method. That is, the region where the source electrode 1s is to be formed and the region where the drain electrode 1d is to be formed are exposed to form a photoresist pattern covering the other regions, and a metal film is formed by a vapor deposition method using this pattern as a growth mask. It forms and removes this pattern with the metal film on it. In the formation of the metal film, for example, a Ti film having a thickness of about 100 nm is formed, and an Al film having a thickness of about 300 nm is formed on the Ti film. Then, for example, heat treatment (for example, rapid thermal annealing (RTA)) is performed at 400 ° C. to 1000 ° C. (for example, 600 ° C.) in the atmosphere of N ₂ to obtain ohmic contact. Further, a gate electrode 1g is formed on the electron supply layer 250 between the source electrode 1s and the drain electrode 1d. The gate electrode 1g can be formed by, for example, a lift-off method. That is, a pattern of a photoresist that exposes a region where the gate electrode 1 g is to be formed is formed, a metal film is formed by a vapor deposition method using this pattern as a growth mask, and this pattern is removed together with the metal film on the pattern. In the formation of the metal film, for example, a Ni film having a thickness of about 50 nm is formed, and an Au film having a thickness of about 300 nm is formed on the Ni film.

Then, if necessary, a protective film, wiring, and the like are formed to complete the compound semiconductor device 200.

In the present embodiment, when the recesses 280s and 280d are formed, not only the electron supply layer 250, the spacer layer 240 and the electron traveling layer 230 but also the surface layer portion of the back barrier layer 220 is removed by dry etching. Therefore, as in the first embodiment, the in-plane uniformity of contact resistance can be stabilized.

In the formation of the n-type GaN layers 260s and 260d, the flow rate of the monosilane gas decreases and the flow rate of the monogerman gas increases as the n-type GaN layers 260s and 260d grow, so that distortion due to the difference in lattice constant occurs. Can be doped with donor impurities at a sufficient concentration while suppressing. Therefore, in the compound semiconductor device 200, the off-leakage current can be reduced while obtaining excellent high frequency characteristics.

Of the donor impurities contained in the n-type GaN layers 260s and 260d, oxygen (O) may be used in place of all or part of Ge. O can be contained in the n-type GaN layers 260s and 260d using, for example, t-butyl alcohol. Carbon monoxide (CO) or carbon dioxide (CO ₂ ) can also be contained in the n-type GaN layers 260s and 260d.

Here, the effect obtained by reducing the contact resistance will be described. Generally, the mutual conductance gm of the GaN-based _HEMT is expressed by the following equation 1. In Equation 1, g _m0 is the true mutual conductance and _RS is the source resistance.

As can be seen from Equation 1, the lower the contact resistance, the lower the source resistance _RS , and therefore the larger the mutual conductance _gm .

The cutoff frequency f _T is expressed by the following equation 2. In Equation 2, _{CGS is the capacitance between the gate and the source and CGD is} the capacitance between the gate and the drain.

As can be seen from Equation 2, the larger the mutual conductance gm, the larger the cutoff frequency _{f T.}

Further, the maximum oscillation frequency f _max is expressed by the following equation 3. In Equation 3, _RG is the gate resistance, Ri is the channel resistance, and _{g d} is the drain conductance.

As can be seen from Equation 3, the larger the cutoff frequency f _T and the lower the source resistance _RS , the larger the maximum oscillation frequency _fmax .

In this way, the maximum oscillation frequency _fmax can be improved by reducing the contact resistance in the source electrode 1s.

Further, the drain current can be increased by reducing the contact resistance of the drain electrode 1d. FIG. 5 is a diagram showing the relationship between the drain voltage and the drain current. The horizontal axis of FIG. 5 indicates the drain voltage Vd, and the vertical axis indicates the drain current Id. As shown in FIG. 5, according to the second embodiment, it is possible to obtain an extremely large drain current Id than in the reference example. Here, the reference example has a structure in which the recesses 280s and 280d and the n-type GaN layers 260s and 260d are not formed, and the source electrode 1s and the drain electrode 1d are in contact with the electron supply layer 250.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment relates to a compound semiconductor device including a GaN-based HEMT. FIG. 6 is a cross-sectional view showing the compound semiconductor device according to the third embodiment.

As shown in FIG. 6, the compound semiconductor device 300 according to the third embodiment is formed above the substrate 310, the nitride semiconductor laminated structure 390 formed above the substrate 310, and the nitride semiconductor laminated structure 390. It has a source electrode 1s, a gate electrode 1g, and a drain electrode 1d. The substrate 310 is, for example, a Si substrate, a SiC substrate, a sapphire substrate, a GaN substrate, or the like. The nitride semiconductor laminated structure 390 includes a back barrier layer 220, an electron traveling layer 230, a spacer layer 240, an electron supply layer 250, an n-type GaN layer 260s, and an n-type GaN layer 260d, as in the second embodiment. The nitride semiconductor laminated structure 390 further includes an AlN layer 370 between the substrate 310 and the back barrier layer 220.

According to such a third embodiment, since the AlN layer 370 is formed, the back barrier layer 220 having good crystallinity can be obtained even if a substrate 310 different from the AlN substrate is used. Then, the same effect as that of the second embodiment can be obtained. Further, various substrates 310 can be used in response to various requests. For example, when a Si substrate is used, the cost can be reduced.

The AlN layer 370 can be formed by a crystal growth method such as a MOCVD method and an MBE method, like other nitride semiconductor laminates.

(Fourth Embodiment)
Next, a fourth embodiment will be described. A fourth embodiment relates to a compound semiconductor device including a GaN-based HEMT. FIG. 7 is a cross-sectional view showing the compound semiconductor device according to the fourth embodiment.

As shown in FIG. 7, the compound semiconductor device 400 according to the fourth embodiment is formed above the substrate 210, the nitride semiconductor laminated structure 490 formed above the substrate 210, and the nitride semiconductor laminated structure 490. It has a source electrode 1s, a gate electrode 1g, and a drain electrode 1d. The nitride semiconductor laminated structure 490 includes a back barrier layer 220, an electron traveling layer 230, a spacer layer 240, an electron supply layer 250, an n-type GaN layer 260s, and an n-type GaN layer 260d, as in the second embodiment. The nitride semiconductor laminated structure 490 further includes a buffer layer 470 between the back barrier layer 220 and the electron traveling layer 230. The buffer layer 470 is, for example, an AlGaN layer whose Al composition decreases as it approaches from the lower surface to the upper surface. At this time, for example, the composition of the lower surface of the buffer layer 470 is AlN, and the composition of the upper surface of the buffer layer 470 is GaN. The Al composition may be continuously changed or may be changed stepwise. The buffer layer 470 is included in the first nitride semiconductor layer.

The same effect as that of the second embodiment can be obtained by such a fourth embodiment. Further, since the buffer layer 470 is formed, it is easy to form the electron traveling layer 230 having good crystallinity even if there is a large lattice constant difference between the back barrier layer 220 and the electron traveling layer 230.

The buffer layer 470 can be formed by a crystal growth method such as a MOCVD method and an MBE method, like other nitride semiconductor laminates.

The recesses 280s and 280d may reach the back barrier layer 220 as in the second embodiment. The recesses 280s and 280d may be formed halfway through the buffer layer 470 in the thickness direction, and a part of the buffer layer 470 may remain between the n-type GaN layers 260s and 260d. In this case, for example, the Ga concentration in the portion of the buffer layer 470 in contact with the electron traveling layer 230, which is a part of the first nitride semiconductor layer, is in the portion of the buffer layer 470 in contact with the n-type GaN layer 260s in the thickness direction. It is higher than the Ga concentration and the Ga concentration in the portion in contact with the n-type GaN layer 260d.

(Fifth Embodiment)
Next, a fifth embodiment will be described. A fifth embodiment relates to a compound semiconductor device including a GaN-based HEMT. FIG. 8 is a cross-sectional view showing the compound semiconductor device according to the fifth embodiment.

As shown in FIG. 8, the compound semiconductor device 500 according to the fifth embodiment is formed above the substrate 210, the nitride semiconductor laminated structure 590 formed above the substrate 210, and the nitride semiconductor laminated structure 590. It has a source electrode 1s, a gate electrode 1g, and a drain electrode 1d. The nitride semiconductor laminated structure 590 includes a back barrier layer 220, an electron traveling layer 230, a spacer layer 240, an electron supply layer 250, an n-type GaN layer 560s and an n-type GaN layer 560d. In a plan view, the end of the n-type GaN layer 560s on the gate electrode 1g side is located closer to the gate electrode 1g than the end of the source electrode 1s on the gate electrode 1g side, and is located on the gate electrode 1g side of the n-type GaN layer 560d. The end portion is located closer to the gate electrode 1g than the end portion of the drain electrode 1d on the gate electrode 1g side.

The same effect as that of the second embodiment can be obtained by such a fifth embodiment. Further, since the n-type GaN layer 560s and the n-type GaN layer 560d are located close to the gate electrode 1g in a plan view, the channel resistance can be reduced.

For example, by changing the pattern of the resist mask used when forming the recesses 280s and 280d, the n-type GaN layers 560s and 560d can be formed in the same manner as the n-type GaN layers 260s and 260d.

(Sixth Embodiment)
Next, the sixth embodiment will be described. A sixth embodiment relates to a compound semiconductor device including a GaN-based HEMT. FIG. 9 is a cross-sectional view showing the compound semiconductor device according to the sixth embodiment.

As shown in FIG. 9, the compound semiconductor device 600 according to the sixth embodiment is formed above the substrate 210, the nitride semiconductor laminated structure 290 formed above the substrate 210, and the nitride semiconductor laminated structure 290. It has a source electrode 1s, a gate electrode 1g, and a drain electrode 1d. The compound semiconductor device 600 further has an insulating film 670 formed on the nitride semiconductor laminated structure 290 between the source electrode 1s and the drain electrode 1d, and the gate electrode 1g is formed on the insulating film 670. .. The insulating film 670 is, for example, aluminum oxide or a silicon nitride film.

The same effect as that of the second embodiment can be obtained by such a sixth embodiment. Further, since the insulating film 670 is formed, the withstand voltage can be further improved.

(7th Embodiment)
Next, a seventh embodiment will be described. A seventh embodiment relates to a discrete package of HEMTs. FIG. 10 is a diagram showing a discrete package according to the seventh embodiment.

In the seventh embodiment, as shown in FIG. 10, the back surface of the compound semiconductor device 1210 having the same structure as that of any one of the first to sixth embodiments is landed using a die attachant 1234 such as solder. Die pad) It is fixed to 1233. Further, a wire 1235d such as an Al wire is connected to the drain pad 1226d to which the drain electrode 1d is connected, and the other end of the wire 1235d is connected to the drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to the source pad 1226s connected to the source electrode 1s, and the other end of the wire 1235s is connected to a source lead 1232s independent of the land 1233. A wire 1235 g such as an Al wire is connected to a gate pad 1226 g connected to the gate electrode 1 g, and the other end of the wire 1235 g is connected to a gate lead 1232 g independent of the land 1233. The land 1233, the compound semiconductor device 1210, and the like are packaged with the mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s project.

Such a discrete package can be manufactured, for example, as follows. First, the compound semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attachant 1234 such as solder. The gate pad 1226g is then connected to the lead frame gate lead 1232g, the drain pad 1226d is connected to the lead frame drain lead 1232d, and the source pad 1226s is the lead frame source by bonding with wires 1235g, 1235d and 1235s. Connect to the lead 1232s. After that, sealing is performed using the mold resin 1231 by the transfer molding method. Then, the lead frame is separated.

(8th Embodiment)
Next, the eighth embodiment will be described. An eighth embodiment relates to a PFC (Power Factor Correction) circuit including a HEMT. FIG. 11 is a wiring diagram showing the PFC circuit according to the eighth embodiment.

The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an alternating current power supply (AC) 1257. Then, the drain electrode of the switch element 1251 and the anode terminal of the diode 1252 and one terminal of the choke coil 1253 are connected. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 and the other terminal of the choke coil 1253 are connected. The other terminal of the capacitor 1255 and the cathode terminal of the diode 1252 are connected. Further, a gate driver is connected to the gate electrode of the switch element 1251. AC1257 is connected between both terminals of the capacitor 1254 via a diode bridge 1256. A direct current (DC) is connected between both terminals of the capacitor 1255. In the present embodiment, the switch element 1251 uses a compound semiconductor device having the same structure as that of any of the first to sixth embodiments.

In manufacturing the PFC circuit 1250, for example, the switch element 1251 is connected to the diode 1252, the choke coil 1253, etc. by using solder or the like.

(9th embodiment)
Next, a ninth embodiment will be described. A ninth embodiment relates to a power supply device including a HEMT, which is suitable for a server power supply. FIG. 12 is a wiring diagram showing a power supply device according to a ninth embodiment.

The power supply device is provided with a high voltage primary circuit 1261 and a low voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.

The primary side circuit 1261 is provided with an inverter circuit connected between both terminals of the PFC circuit 1250 and the capacitor 1255 of the PFC circuit 1250 according to the eighth embodiment, for example, a full bridge inverter circuit 1260. The full bridge inverter circuit 1260 is provided with a plurality of (four in this case) switch elements 1264a, 1264b, 1264c, and 1264d.

The secondary circuit 1262 is provided with a plurality of (three in this case) switch elements 1265a, 1265b, and 1265c.

In the present embodiment, the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261 and the switch elements 1264a, 1264b, 1264c and 1264d of the full bridge inverter circuit 1260 are the same as those of the first to sixth embodiments. A compound semiconductor device having the above structure is used. On the other hand, ordinary MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b and 1265c of the secondary circuit 1262.

(10th Embodiment)
Next, a tenth embodiment will be described. A tenth embodiment relates to an amplifier equipped with a HEMT. FIG. 13 is a wiring diagram showing the amplifier according to the tenth embodiment.

The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

The digital predistortion circuit 1271 compensates for the non-linear distortion of the input signal. The mixer 1272a mixes the input signal compensated for the non-linear distortion and the AC signal. The power amplifier 1273 includes a compound semiconductor device having a structure similar to that of any one of the first to sixth embodiments, and amplifies an AC signal and a mixed input signal. In the present embodiment, for example, the output side signal can be mixed with the AC signal by the mixer 1272b and transmitted to the digital predistortion circuit 1271 by switching the switch. This amplifier can be used as a high frequency amplifier and a high output amplifier. The high frequency amplifier can be used, for example, in a transmission / reception device for a mobile phone base station, a radar device, and a microwave generator.

Hereinafter, various aspects of the present disclosure will be described together as an appendix.

(Appendix 1)
Nitride semiconductor laminated structure and
The source electrode, the gate electrode, and the drain electrode formed above the nitride semiconductor laminated structure,
Have,
The nitride semiconductor laminated structure is
A first nitride semiconductor layer of aluminum nitride or aluminum gallium nitride with a first lattice constant.
A second nitride semiconductor layer of gallium nitride or aluminum gallium nitride formed above the first nitride semiconductor layer and having a second lattice constant larger than the first lattice constant.
A third nitride semiconductor layer and a fourth nitride of n-type gallium nitride formed on the first nitride semiconductor layer so as to sandwich the second nitride semiconductor layer in a plan view. With the semiconductor layer,
Have,
The third lattice constant of the third nitride semiconductor layer and the fourth lattice constant of the fourth nitride semiconductor layer are closer to the interface with the first nitride semiconductor layer in the thickness direction. Close to the first lattice constant,
The gate electrode is formed above the second nitride semiconductor layer and is formed.
The source electrode is formed on the third nitride semiconductor layer, and the source electrode is formed on the third nitride semiconductor layer.
The compound semiconductor device is characterized in that the drain electrode is formed on the fourth nitride semiconductor layer.
(Appendix 2)
The first nitride semiconductor layer is an aluminum nitride layer.
The compound semiconductor device according to Appendix 1, wherein the second nitride semiconductor layer is a gallium nitride layer.
(Appendix 3)
The nitride semiconductor laminated structure has a fifth nitride semiconductor layer of aluminum nitride, aluminum nitride gallium or indium aluminum gallium nitride formed on the second nitride semiconductor layer.
The compound semiconductor device according to Appendix 1 or 2, wherein the bandgap of the fifth nitride semiconductor layer is larger than the bandgap of the second nitride semiconductor layer.
(Appendix 4)
The compound semiconductor device according to Appendix 3, wherein the fifth nitride semiconductor layer is an aluminum nitride layer.
(Appendix 5)
The nitride semiconductor laminated structure has a sixth nitride semiconductor layer formed above the second nitride semiconductor layer.
The compound semiconductor device according to any one of Supplementary note 1 to 4, wherein the bandgap of the sixth nitride semiconductor layer is larger than the bandgap of the second nitride semiconductor layer.
(Appendix 6)
The third nitride semiconductor layer and the fourth nitride semiconductor layer include silicon, germanium, oxygen, or any combination thereof as n-type impurities. The compound semiconductor device according to the section.
(Appendix 7)
In the third nitride semiconductor layer and the fourth nitride semiconductor layer, the closer to the interface with the first nitride semiconductor layer in the thickness direction, the higher the concentration of silicon, and germanium or oxygen or The compound semiconductor device according to Appendix 6, wherein the concentrations of both of these are low.
(Appendix 8)
The compound semiconductor device according to any one of Supplementary note 1 to 7, wherein the thickness of the second nitride semiconductor layer is 10 nm or more and 30 nm or less.
(Appendix 9)
The lower surface of the second nitride semiconductor layer is in contact with the upper surface of the first nitride semiconductor layer.
The interface between the first nitride semiconductor layer and the second nitride semiconductor layer is the interface between the first nitride semiconductor layer and the third nitride semiconductor layer and the first nitride semiconductor. The compound semiconductor device according to any one of Supplementary note 1 to 8, wherein the compound semiconductor device is located above the interface between the layer and the fourth nitride semiconductor layer.
(Appendix 10)
The concentration of gallium in the portion of the first nitride semiconductor layer in contact with the second nitride semiconductor layer is
From the concentration of gallium in the portion of the first nitride semiconductor layer in contact with the third nitride semiconductor layer and the concentration of gallium in the portion of the first nitride semiconductor layer in contact with the fourth nitride semiconductor layer. The compound semiconductor device according to Appendix 9, which is characterized in that it is also expensive.
(Appendix 11)
A high frequency amplifier comprising the compound semiconductor device according to any one of Supplementary note 1 to 10.
(Appendix 12)
A power supply device comprising the compound semiconductor device according to any one of Supplementary note 1 to 10.

1s: Source electrode 1d: Drain electrode 1g: Gate electrode 100, 200, 300, 400, 500, 600: Compound semiconductor device 120, 220: Back barrier layer 130, 230: Electron traveling layer 150, 250: Electron supply layer 160s, 160d, 260s, 260d: n-type GaN layer 190: 290, 390, 490, 590: Nitride semiconductor laminated structure 240: Spacer layer

Claims (6)

Nitride semiconductor laminated structure and
The source electrode, the gate electrode, and the drain electrode formed above the nitride semiconductor laminated structure,
Have,
The nitride semiconductor laminated structure is
A first nitride semiconductor layer of aluminum nitride or aluminum gallium nitride with a first lattice constant.
A second nitride semiconductor layer of gallium nitride or aluminum gallium nitride formed above the first nitride semiconductor layer and having a second lattice constant larger than the first lattice constant.
A third nitride semiconductor layer and a fourth nitride of n-type gallium nitride formed on the first nitride semiconductor layer so as to sandwich the second nitride semiconductor layer in a plan view. With the semiconductor layer,
Have,
The third nitride semiconductor layer and the fourth nitride semiconductor layer contain silicon, germanium, oxygen, or any combination thereof as n-type impurities.
In the third nitride semiconductor layer and the fourth nitride semiconductor layer, the closer to the interface with the first nitride semiconductor layer in the thickness direction, the higher the concentration of silicon, and germanium or oxygen or The concentration of both of these is low,
The third lattice constant of the third nitride semiconductor layer and the fourth lattice constant of the fourth nitride semiconductor layer are closer to the interface with the first nitride semiconductor layer in the thickness direction. Close to the first lattice constant,
The gate electrode is formed above the second nitride semiconductor layer and is formed.
The source electrode is formed on the third nitride semiconductor layer, and the source electrode is formed on the third nitride semiconductor layer.
The compound semiconductor device is characterized in that the drain electrode is formed on the fourth nitride semiconductor layer. The first nitride semiconductor layer is an aluminum nitride layer.
The compound semiconductor device according to claim 1, wherein the second nitride semiconductor layer is a gallium nitride layer. The nitride semiconductor laminated structure has a fifth nitride semiconductor layer of aluminum nitride, aluminum nitride gallium or indium aluminum gallium nitride formed on the second nitride semiconductor layer.
The compound semiconductor device according to claim 1 or 2, wherein the bandgap of the fifth nitride semiconductor layer is larger than the bandgap of the second nitride semiconductor layer. The compound semiconductor device according to claim 3, wherein the fifth nitride semiconductor layer is an aluminum nitride layer. A high frequency amplifier comprising the compound semiconductor device according to any one of claims 1 to 4 . A power supply device comprising the compound semiconductor device according to any one of claims 1 to 4 .

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