JP2022016950A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device that can increase the threshold voltage.SOLUTION: A semiconductor device includes: a foundation of a first nitride semiconductor; a channel layer of a second nitride semiconductor provided over the foundation; a barrier layer provided over the channel layer; a first opening and a second opening provided to the channel layer and the barrier layer; a first contact layer of a third nitride semiconductor provided in the first opening in contact with the channel layer; a second contact layer of a fourth nitride semiconductor having conductivity and provided in the second opening in contact with the channel layer; a source electrode provided on the first contact layer; a drain electrode provided on the second contact layer; and a gate electrode provided over the barrier layer and between the source electrode and the drain electrode. A lower end of a conduction band of the channel layer is higher than the Fermi level in a state where voltage is not applied to the gate electrode.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to semiconductor devices.

As a semiconductor device using a nitride semiconductor, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). As a HEMT using a nitride semiconductor, a HEMT using a GaN layer as a channel layer and an AlGaN layer as a barrier layer is known. In such a GaN-based HEMT, strain due to the difference in lattice constant between AlGaN and GaN occurs in the AlGaN layer, and piezopolarization occurs with this strain, resulting in high-concentration two-dimensional electron gas. : 2DEG) is generated near the upper surface of the GaN layer under the AlGaN layer. Therefore, a high output can be obtained.

Conventionally, in order to realize a normally-off operation, a semiconductor device in which a p-type GaN layer or an InGaN layer is provided under a gate electrode has been proposed.

Japanese Unexamined Patent Publication No. 2009-76845 Japanese Unexamined Patent Publication No. 2008-21172 Japanese Unexamined Patent Publication No. 2016-046320 Japanese Patent Application Laid-Open No. 2013-500606 Japanese Unexamined Patent Publication No. 2016-115931 JP-A-2019-96739 Japanese Unexamined Patent Publication No. 2019-165172

T. Mizutani, M. Ito, S. Kishimoto and F. Nakamura, IEEE Electron Device Letters, vol. 28, no. 7, pp. 549-551 (2007)

However, with a conventional transistor, it is difficult to increase the threshold voltage, and stable normally-off operation cannot be realized.

An object of the present disclosure is to provide a semiconductor device capable of increasing the threshold voltage.

According to one embodiment of the present disclosure, the substrate of the first nitride semiconductor, the channel layer of the second nitride semiconductor provided above the substrate, the barrier layer provided above the channel layer, and the above. The first opening and the second opening provided in the channel layer and the barrier layer, and the first of the third nitride semiconductor provided in the first opening and in contact with the channel layer and having conductivity. A contact layer, a second contact layer of a fourth nitride semiconductor provided in the second opening and in contact with the channel layer and having conductivity, and a source electrode provided on the first contact layer. And a drain electrode provided on the second contact layer, and a gate electrode provided between the source electrode and the drain electrode above the barrier layer, and the channel layer. A semiconductor device having a lower end of the conduction band higher than the Fermi level is provided in a state where no voltage is applied to the gate electrode.

According to the present disclosure, the threshold voltage can be increased.

It is sectional drawing which shows the semiconductor device which concerns on 1st Embodiment. It is a band diagram which shows the lower end of the conduction band of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the relationship between the thickness and the sheet resistance in the GaN layer provided on the AlN layer. It is sectional drawing (the 1) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 2) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 3) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 4) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. It is a band diagram which shows the lower end of the conduction band of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing (the 1) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing (the 2) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the discrete package which concerns on 3rd Embodiment. It is a wiring diagram which shows the PFC circuit which concerns on 4th Embodiment. It is a wiring diagram which shows the power supply device which concerns on 5th Embodiment. It is a wiring diagram which shows the amplifier which concerns on 6th Embodiment.

Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In the present specification and the drawings, components having substantially the same functional configuration may be designated by the same reference numerals to omit duplicate explanations.

(First Embodiment)
The first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT). FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment.

As shown in FIG. 1, the semiconductor device 100 according to the first embodiment has a nitride semiconductor laminated structure 104. The nitride semiconductor laminated structure 104 includes a substrate 101, a channel layer 102, and a barrier layer 103. The channel layer 102 is formed on the substrate 101. The barrier layer 103 is formed on the channel layer 102.

The substrate 101 is, for example, an AlN self-supporting substrate, and the upper surface of the substrate 101 is an Al polar surface. That is, the Miller index on the upper surface of the substrate 101 is (0001). The channel layer 102 is, for example, a GaN layer having a thickness of 50 nm or less. The barrier layer 103 is, for example, an In _x1 Al _y1 Ga _1-x1-y1 N layer (0.00≤x1≤0.20, 0.00 <y1≤1.00) having a thickness of 4 nm to 20 nm. The substrate 101 is an example of a substrate. AlN of the substrate 101 is an example of a first nitride semiconductor. The GaN of the channel layer 102 is an example of a second nitride semiconductor. In _x1 Al _y1 Ga _1-x1-y1 N (0.00 ≦ x1 ≦ 0.20, 0.00 ≦ y1 ≦ 1.00) of the barrier layer 103 is an example of the fifth nitride semiconductor. An AlN buffer layer may be included between the substrate 101 and the channel layer 102. This buffer layer is also included in the base.

An element separation region defining an element region is formed in the nitride semiconductor laminated structure 104, and an opening 111s for a source and an opening 111d for a drain are formed in the barrier layer 103 and the channel layer 102 in the element region. Has been done. The openings 111s and 111d are formed apart from each other. For example, the distance L1 between the opening 111s and the opening 111d is about 40 nm to 1000 nm. The openings 111s and 111d are formed so as to enter the substrate 101. That is, the bottom surfaces of the openings 111s and 111d are located below (lower surface side) the upper surface (interface 12 between the substrate 101 and the channel layer 102) of the portion between the openings 111s and 111d of the substrate 101. is doing. For example, the depth D of each bottom surface of the openings 111s and 111d with respect to the interface 12 is about 10 nm to 100 nm.

A conductive contact layer 112s for a source is formed in the opening 111s, and a conductive contact layer 112d for a drain is formed in the opening 111d. The contact layers 112s and 112d are n-type GaN layers having a thickness of, for example, about 50 nm to 200 nm. The contact layers 112s and 112d are doped with Si, for example, as an n-type impurity at a concentration of about 5 × 10 ¹⁸ cm ^-3 . The contact layers 112s and 112d may be doped with Ge, O or the like as n-type impurities. The n-type GaN of the contact layers 112s and 112d may contain n-type impurities at a concentration of, for example, 1 × 10 ¹⁷ cm ^-3 to 5 × 10 ²⁰ cm ^-3 . The contact layers 112s and 112d are also included in the nitride semiconductor laminated structure 104. The opening 111s is an example of the first opening, and the opening 111d is an example of the second opening. The contact layer 112s is an example of the first contact layer, and the contact layer 112d is an example of the second contact layer. The n-type GaN of the contact layer 112s is an example of a third nitride semiconductor, and the n-type GaN of the contact layer 112d is an example of a fourth nitride semiconductor.

The source electrode 1s is formed on a part of the upper surface of the contact layer 112s, and the drain electrode 1d is formed on a part of the upper surface of the contact layer 112d. The end of the source electrode 1s on the drain electrode 1d side is farther from the drain electrode 1d than the end of the contact layer 112s on the drain electrode 1d side. The end of the drain electrode 1d on the source electrode 1s side is farther from the source electrode 1s than the end of the contact layer 112d on the source electrode 1s side.

A passivation film 108 covering the source electrode 1s and the drain electrode 1d is formed on the barrier layer 103. The passivation film 108 is formed with an opening 108 g located between the source electrode 1s and the drain electrode 1d in a plan view, and a gate electrode 1 g in contact with the barrier layer 103 through the opening 108 g is formed on the passivation film 108. ing.

For example, the width (dimension in the gate length direction) L2 of the opening 108 g is smaller than the distance L1 and is about 20 nm to 500 nm. For example, the width L3 of the portion of the gate electrode 1 g on the passivation film 108 is larger than the distance L1 and is about 50 nm to 2000 nm. In a plan view, a part of the contact layer 112s and a part of the gate electrode 1g overlap each other, and a part of the contact layer 112d and a part of the gate electrode 1g overlap each other.

The source electrode 1s and the drain electrode 1d include, for example, a Ta film having a thickness of 10 nm to 50 nm and an Al film having a thickness above the Ta film having a thickness of 100 nm to 500 nm. The source electrode 1s is in ohmic contact with the contact layer 112s, and the drain electrode 1d is in ohmic contact with the contact layer 112d. The gate electrode 1g includes, for example, a Ni film having a thickness of 10 nm to 50 nm and an Au film having a thickness of 300 nm to 500 nm on the Ni film, and is in Schottky contact with the barrier layer 103. The passivation film 108 is, for example, an oxide, nitride or oxynitride film of Si, Al, Hf, Zr, Ti, Ta or W, preferably a Si nitride (SiN) film. The thickness of the passivation film 108 is, for example, 2 nm to 500 nm, preferably about 100 nm.

Next, the band structure of the semiconductor device 100 will be described. FIG. 2 is a band diagram showing the lower end Ec of the conduction band of the semiconductor device 100. FIG. 2 also shows Fermi level Ef. FIG. 2 shows a band diagram below the opening 108g of the passivation film 108 when no voltage is applied to the gate electrode 1g. In the semiconductor device 100, the GaN channel layer 102 is formed on the AlN substrate 101, and the In _x1 Aly1 Ga _{1-x1-y1 N} (0.00 ≦ x1 ≦ 0.20, 0) is formed on the GaN channel layer 102. The barrier layer 103 of .00 ≦ y1 ≦ 1.00) is formed. The lower end Ec of the conduction band of the channel layer 102 is lower than the lower end Ec of the conduction band of the substrate 101, and the lower end Ec of the conduction band of the barrier layer 103 is higher than the lower end Ec of the conduction band of the channel layer 102. AlN has a strong spontaneous polarization and pulls up the lower end Ec of the conduction band of the channel layer 102. Further, the thickness of the channel layer 102 is, for example, 50 nm or less, which is relatively thin. Therefore, as shown in FIG. 2, when no voltage is applied to the gate electrode 1g, the lower end Ec of the conduction band of the channel layer 102 is higher than the Fermi level Ef over the entire thickness direction of the channel layer 102. Therefore, there is no two-dimensional electron gas (2DEG) in the channel layer 102.

As described above, in the first embodiment, 2DEG is prevented from being generated in the channel layer 102 due to the strong spontaneous polarization of AlN of the substrate 101. Therefore, the threshold voltage can be easily increased, and stable normally-off operation can be realized.

Further, in a plan view, a part of the contact layer 112s and a part of the gate electrode 1g overlap each other, and a part of the contact layer 112d and a part of the gate electrode 1g overlap each other. Therefore, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 1g, 2DEG is generated so as to connect the contact layer 112s and the contact layer 112d, and a current flows between the source electrode 1s and the drain electrode 1d.

The channel layer 102 does not need to be lattice-matched to the substrate 101. For example, in the direction parallel to the interface 12 between the substrate 101 and the channel layer 102 (in-plane direction), the lattice constant at the interface 12 of the substrate 101 is equal to the lattice constant a _AlN in the a-axis direction of AlN, and the channel layer 102 The lattice constant at the interface 12 may be equal to the lattice constant a _GaN in the a-axis direction of GaN. When no external force is applied and no strain is generated, the lattice constant a GaN in the a-axis direction of _GaN is 3.189 Å, and the lattice constant a _{AlN in the a-axis direction of AlN} is 3.112 Å. Therefore, in the in-plane direction, the first lattice constant at the interface 12 of the substrate 101 may be smaller than the second lattice constant at the interface 12 of the channel layer 102. When the channel layer 102 is not lattice-matched to the substrate 101, the strain in the channel layer 102 is small and more excellent electron mobility can be obtained as compared with the case where the channel layer 102 is lattice-matched.

The thickness of the channel layer 102 is preferably 50 nm or less, more preferably 20 nm or less. This is because the influence of the spontaneous polarization of the substrate 101 is low on the entire thickness direction of the channel layer 102. FIG. 3 shows the relationship between the thickness and the sheet resistance in the GaN layer provided on the AlN layer. FIG. 3 shows the result of the simulation by the inventor of the present application.

As shown in FIG. 3, when the thickness of the GaN layer is 50 nm or less, the sheet resistance is remarkably high. This means that when the thickness of the channel layer 102 is 50 nm or less, the normally-off operation can be easily realized.

Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. 4 to 7 are cross-sectional views showing a method of manufacturing the semiconductor device 100 according to the first embodiment.

First, as shown in FIG. 4A, the channel layer 102 and the barrier layer 103 are formed on the (0001) plane of the substrate 101 by, for example, a metal organic vapor phase epitaxy (MOVPE) method. In forming the channel layer 102 and the barrier layer 103, as raw material gases, for example, trimethylaluminum (TMAl) gas as an Al source, trimethylgallium (TMGa) gas as a Ga source, and trimethylindium (TMIn) as an In source. A mixed gas of gas and ammonia (NH ₃ ) gas, which is an N source, is used. Hydrogen (H ₂ ) gas or nitrogen (N ₂ ) gas is used as the carrier gas. Depending on the composition of the nitride semiconductor layer to be grown, the presence or absence of supply of TMAl gas, TMGa gas and TMIn gas and the flow rate are appropriately set. For example, the growth pressure is about 1 kPa to 100 kPa, and the growth temperature is about 600 ° C. to 1500 ° C.

Next, as shown in FIG. 4B, the surface protective film 110 is formed on the barrier layer 103. The surface protective film 110 is, for example, a film of an oxide of Si, Al, Hf, Zr, Ti, Ta or W, a nitride or an acid nitride, and is preferably a film of a Si oxide (SiO ₂ ). The surface protective film 110 can be formed, for example, by a plasma chemical vapor deposition (CVD) method. The surface protective film 110 may be formed by an atomic layer deposition (ALD) method or a sputtering method.

Then, as shown in FIG. 5A, the opening 111s for the source and the opening 111d for the drain are formed in the surface protective film 110, the barrier layer 103, and the channel layer 102. In the formation of the openings 111s and 111d, for example, a photoresist pattern that exposes the region where the openings 111s and 111d are to be formed is formed on the surface protective film 110 by photolithography, and this pattern is used as an etching mask for a fluorine system. Perform dry etching using gas or chlorine-based gas. The openings 111s and 111d are formed so as to enter the substrate 101. That is, each bottom surface of the openings 111s and 111d is located below (lower surface side) the upper surface (interface 12 between the substrate 101 and the channel layer 102) of the portion between the openings 111s and 111d of the substrate 101. As such, the openings 111s and 111d are formed. The substrate 101 is exposed to the openings 111s and 111d.

Subsequently, as shown in FIG. 5B, the contact layer 112s is formed in the opening 111s, and the contact layer 112d is formed in the opening 111d. The contact layers 112s and 112d can be formed, for example, by the MOVPE method. In forming the contact layers 112s and 112d, H ₂ gas or N ₂ gas is used as the carrier gas, and a mixed gas of TMGa gas and NH ₃ gas is used as the raw material gas. At this time, in order to make the contact layers 112s and 112d n-type, for example, a silane (SiH ₄ ) gas containing Si is added to the mixed gas at a predetermined flow rate, and the contact layers 112s and 112d are doped with Si. For example, when the contact layers 112s and 112d are grown, the growth pressure is about 1 kPa to 100 kPa, and the growth temperature is about 600 ° C. to 1500 ° C. After forming the contact layers 112s and 112d, the surface protective film 110 is removed. Ge or O may be used as the n-type impurity to be doped into the contact layers 112s and 112d. The upper surfaces of the contact layers 112s and 112d may be above the upper surface of the barrier layer 103, may be flush with the upper surface of the barrier layer 103, or may be below the upper surface of the barrier layer 103.

A nitride semiconductor laminated structure 104 including a substrate 101, a channel layer 102, a barrier layer 103, a contact layer 112s, and a contact layer 112d can be obtained.

Next, an element separation region that defines the element region is formed in the nitride semiconductor laminated structure 104. In the formation of the device separation region, for example, a photoresist pattern that exposes the region where the device separation region is to be formed is formed on the nitride semiconductor laminated structure 104, and ion implantation such as Ar is performed using this pattern as a mask. Dry etching using a chlorine-based gas may be performed using this pattern as an etching mask.

Then, as shown in FIG. 6A, the source electrode 1s is formed on the contact layer 112s, and the drain electrode 1d is formed on the contact layer 112d. The source electrode 1s is formed so that the end of the source electrode 1s on the drain electrode 1d side is separated from the end of the contact layer 112s on the drain electrode 1d side. The drain electrode 1d is formed so that the end of the drain electrode 1d on the source electrode 1s side is separated from the end of the contact layer 112d on the source electrode 1s side. The source electrode 1s and the drain electrode 1d can be formed by, for example, a lift-off method. That is, a pattern of a photoresist that exposes the region where the source electrode 1s and the drain electrode 1d are to be formed is formed, a metal film is formed by a vapor deposition method using this pattern as a growth mask, and this pattern is formed together with the metal film on the pattern. Remove. In the formation of the metal film, for example, a Ta film is formed and an Al film is formed on the Ta film. Then, for example, heat treatment is performed at 400 ° C. to 1000 ° C., preferably about 550 ° C. in a nitrogen atmosphere to establish ohmic characteristics.

Subsequently, as shown in FIG. 6B, a passivation film 108 covering the source electrode 1s and the drain electrode 1d is formed on the barrier layer 103. The passivation film 108 can be formed by, for example, a plasma CVD method. The passivation film 108 may be formed by an ALD method or a sputtering method.

Next, as shown in FIG. 7A, an opening 108 g is formed in the passivation film 108. In the formation of the opening 108g, for example, a photoresist pattern that exposes the region where the opening 108g is to be formed is formed on the passion film 108 by photolithography, and this pattern is used as an etching mask to form a fluorine-based gas or a chlorine-based gas. Perform dry etching using. Instead of dry etching, wet etching using fluoroacid, buffered fluoroacid, or the like may be performed.

Then, as shown in FIG. 7B, a gate electrode 1g in contact with the barrier layer 103 is formed on the passivation film 108 through the opening 108g. The gate electrode 1g can be formed by, for example, a lift-off method. That is, a pattern of a photoresist that exposes a region where the gate electrode 1 g is to be formed is formed, a metal film is formed by a vapor deposition method using this pattern as a growth mask, and this pattern is removed together with the metal film on the pattern. In the formation of the metal film, for example, a Ni film is formed and an Au film is formed on the Ni film.

In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

As the structure of the gate electrode, the shotkey type gate structure is used in the first embodiment, but a MIS (metal-insulator-semiconductor) type gate structure may be used.

(Second Embodiment)
The second embodiment will be described. The second embodiment relates to a semiconductor device including a HEMT. FIG. 8 is a cross-sectional view showing the semiconductor device according to the second embodiment.

As shown in FIG. 8, the semiconductor device 200 according to the second embodiment has a nitride semiconductor laminated structure 204 instead of the nitride semiconductor laminated structure 104 in the first embodiment, and has a barrier layer instead of the barrier layer 103. It has 203. The nitride semiconductor laminated structure 204 includes a substrate 101, a channel layer 102, a contact layer 112s, and a contact layer 112d. The barrier layer 203 is, for example, an amorphous AlN layer having a thickness of 4 nm to 20 nm. Other configurations are the same as in the first embodiment.

Next, the band structure of the semiconductor device 200 will be described. FIG. 9 is a band diagram showing the lower end Ec of the conduction band of the semiconductor device 200. FIG. 9 also shows Fermi level Ef. FIG. 9 shows a band diagram below the opening 108g of the passivation film 108 when no voltage is applied to the gate electrode 1g. In the semiconductor device 200, the GaN channel layer 102 is formed on the AlN substrate 101, and the amorphous AlN barrier layer 203 is formed on the GaN channel layer 102. The lower end Ec of the conduction band of the channel layer 102 is lower than the lower end Ec of the conduction band of the substrate 101, and the lower end Ec of the conduction band of the barrier layer 203 is higher than the lower end Ec of the conduction band of the channel layer 102. AlN has a strong spontaneous polarization and pulls up the conduction band of the channel layer 102. Further, the thickness of the channel layer 102 is, for example, 50 nm or less, which is relatively thin. Further, in the second embodiment, since the barrier layer 203 is provided, the lower end Ec of the conduction band of the channel layer 102 is higher than that in the first embodiment. Therefore, as shown in FIG. 9, when no voltage is applied to the gate electrode 1g, the lower end Ec of the conduction band of the channel layer 102 is higher than the Fermi level Ef over the entire thickness direction of the channel layer 102. Therefore, there is no 2DEG in the channel layer 102. Further, the lower end Ec of the conduction band of the channel layer 102 is higher than that of the first embodiment.

As described above, in the second embodiment, 2DEG is prevented from being generated in the channel layer 102 due to the strong spontaneous polarization of AlN of the substrate 101 and the barrier layer 203. Therefore, the threshold voltage can be further increased, and more stable normally-off operation can be realized.

As the barrier layer 203, a layer of an oxide, nitride or oxynitride of Si, In, Ga, Al, Hf, Zr, Ti, Ta or W may be used. The barrier layer 203 may be an amorphous layer.

Next, a method of manufacturing the semiconductor device 200 according to the second embodiment will be described. 10 to 11 are cross-sectional views showing a method of manufacturing the semiconductor device 200 according to the second embodiment.

First, as shown in FIG. 10A, the channel layer 102 is formed on the (0001) plane of the substrate 101 by, for example, the MOVPE method, in the same manner as in the first embodiment.

Next, as shown in FIG. 10 (b), the barrier layer 203 is formed on the channel layer 102. The barrier layer 203 is, for example, an oxide, nitride or oxynitride layer of Si, In, Ga, Al, Hf, Zr, Ti, Ta or W, and is preferably an amorphous AlN layer. The barrier layer 203 can be formed by, for example, the ALD method. The barrier layer 203 may be formed by a MOVPE method, a thermal CVD method, a plasma CVD method, or a sputtering method.

After that, as shown in FIG. 11A, the surface protective film 110 is formed on the barrier layer 203.

Subsequently, as shown in FIG. 11B, the processing after the formation of the opening 111s for the source and the opening 111d for the drain is performed in the same manner as in the first embodiment.

In this way, the semiconductor device 200 according to the second embodiment can be manufactured.

In the first embodiment and the second embodiment, the cap layer may be formed on the barrier layer 103.

(Third Embodiment)
Next, the third embodiment will be described. A third embodiment relates to a discrete package of HEMTs. FIG. 12 is a diagram showing a discrete package according to the third embodiment.

In the third embodiment, as shown in FIG. 12, the back surface of the semiconductor device 1210 having the same structure as that of the first or second embodiment is fixed to the land (die pad) 1233 using a die attachant 1234 such as solder. Has been done. Further, a wire 1235d such as an Al wire is connected to the drain pad 1226d to which the drain electrode 1d is connected, and the other end of the wire 1235d is connected to the drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to the source pad 1226s connected to the source electrode 1s, and the other end of the wire 1235s is connected to a source lead 1232s independent of the land 1233. A wire 1235 g such as an Al wire is connected to a gate pad 1226 g connected to the gate electrode 1 g, and the other end of the wire 1235 g is connected to a gate lead 1232 g independent of the land 1233. The land 1233, the semiconductor device 1210, and the like are packaged with the mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s project.

Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attachant 1234 such as solder. The gate pad 1226g is then connected to the lead frame gate lead 1232g, the drain pad 1226d is connected to the lead frame drain lead 1232d, and the source pad 1226s is the lead frame source by bonding with wires 1235g, 1235d and 1235s. Connect to the lead 1232s. After that, sealing is performed using the mold resin 1231 by the transfer molding method. Then, the lead frame is separated.

(Fourth Embodiment)
Next, the fourth embodiment will be described. A fourth embodiment relates to a PFC (Power Factor Correction) circuit including HEMT. FIG. 13 is a wiring diagram showing the PFC circuit according to the fourth embodiment.

The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an alternating current power supply (AC) 1257. Then, the drain electrode of the switch element 1251 and the anode terminal of the diode 1252 and one terminal of the choke coil 1253 are connected. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 and the other terminal of the choke coil 1253 are connected. The other terminal of the capacitor 1255 and the cathode terminal of the diode 1252 are connected. Further, a gate driver is connected to the gate electrode of the switch element 1251. AC1257 is connected between both terminals of the capacitor 1254 via a diode bridge 1256. A direct current (DC) is connected between both terminals of the capacitor 1255. In the present embodiment, the switch element 1251 uses a semiconductor device having the same structure as that of the first or second embodiment.

In manufacturing the PFC circuit 1250, for example, the switch element 1251 is connected to the diode 1252, the choke coil 1253, etc. by using solder or the like.

(Fifth Embodiment)
Next, the fifth embodiment will be described. A fifth embodiment relates to a power supply device including a HEMT, which is suitable for a server power supply. FIG. 14 is a wiring diagram showing a power supply device according to a fifth embodiment.

The power supply device is provided with a high voltage primary side circuit 1261 and a low voltage secondary side circuit 1262, and a transformer 1263 disposed between the primary side circuit 1261 and the secondary side circuit 1262.

The primary side circuit 1261 is provided with an inverter circuit connected between both terminals of the PFC circuit 1250 according to the fourth embodiment and the capacitor 1255 of the PFC circuit 1250, for example, a full bridge inverter circuit 1260. The full-bridge inverter circuit 1260 is provided with a plurality of (four in this case) switch elements 1264a, 1264b, 1264c, and 1264d.

The secondary circuit 1262 is provided with a plurality of (three in this case) switch elements 1265a, 1265b, and 1265c.

In the present embodiment, the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261 and the switch elements 1264a, 1264b, 1264c and 1264d of the full bridge inverter circuit 1260 have the same structure as that of the first or second embodiment. The provided semiconductor device is used. On the other hand, ordinary MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b and 1265c of the secondary circuit 1262.

(Sixth Embodiment)
Next, the sixth embodiment will be described. A sixth embodiment relates to an amplifier equipped with a HEMT. FIG. 15 is a wiring diagram showing the amplifier according to the sixth embodiment.

The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

The digital predistortion circuit 1271 compensates for the non-linear distortion of the input signal. The mixer 1272a mixes the input signal compensated for the non-linear distortion and the AC signal. The power amplifier 1273 includes a semiconductor device having the same structure as that of the first or second embodiment, and amplifies an AC signal and a mixed input signal. In the present embodiment, for example, the output side signal can be mixed with the AC signal by the mixer 1272b and transmitted to the digital predistortion circuit 1271 by switching the switch. This amplifier can be used as a high frequency amplifier and a high output amplifier. The high frequency amplifier can be used, for example, in a transmitter / receiver for a mobile phone base station, a radar device, and a microwave generator.

As the substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate may be used. The substrate may be conductive, semi-insulating or insulating.

The structures of the gate electrode, the source electrode and the drain electrode are not limited to those of the above-described embodiment. For example, these may be composed of a single layer. Further, these forming methods are not limited to the lift-off method. Further, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode and the drain electrode may be omitted. Heat treatment may be performed after the formation of the gate electrode.

Although the preferred embodiments and the like have been described in detail above, they are not limited to the above-described embodiments and the like, and various embodiments and the like described above can be applied without departing from the scope of the claims. Modifications and substitutions can be added.

Hereinafter, various aspects of the present disclosure will be described together as an appendix.

(Appendix 1)
The base of the first nitride semiconductor and
The channel layer of the second nitride semiconductor provided above the substrate and
A barrier layer provided above the channel layer and
The first opening and the second opening provided in the channel layer and the barrier layer, and
A first contact layer of a third nitride semiconductor, which is provided in the first opening and is in contact with the channel layer and has conductivity.
A second contact layer of a fourth nitride semiconductor, which is provided in the second opening and is in contact with the channel layer and has conductivity.
With the source electrode provided on the first contact layer,
The drain electrode provided on the second contact layer and
Above the barrier layer, a gate electrode provided between the source electrode and the drain electrode, and
Have,
A semiconductor device characterized in that the lower end of the conduction band of the channel layer is higher than the Fermi level in a state where no voltage is applied to the gate electrode.
(Appendix 2)
The semiconductor device according to Appendix 1, wherein the thickness of the channel layer is 50 nm or less.
(Appendix 3)
In plan view,
A part of the first contact layer and a part of the gate electrode overlap each other,
The semiconductor device according to Appendix 1 or 2, wherein a part of the second contact layer and a part of the gate electrode overlap each other.
(Appendix 4)
The semiconductor device according to any one of Supplementary note 1 to 3, wherein the barrier layer is an amorphous layer.
(Appendix 5)
The semiconductor device according to any one of Supplementary note 1 to 3, wherein the barrier layer is a semiconductor layer of a fifth nitride semiconductor.
(Appendix 6)
The first opening and the second opening have penetrated into the base.
The semiconductor device according to any one of Supplementary note 1 to 5, wherein the first contact layer and the second contact layer are in contact with the substrate.
(Appendix 7)
The first nitride semiconductor is AlN and is
The semiconductor device according to any one of Supplementary note 1 to 6, wherein the second nitride semiconductor is GaN.
(Appendix 8)
The semiconductor device according to Appendix 7, wherein the surface of the base is a (0001) plane.
(Appendix 9)
The substrate and the channel layer are in contact with each other via an interface,
The item according to any one of Supplementary note 1 to 8, wherein the first lattice constant at the interface of the substrate is smaller than the second lattice constant at the interface of the channel layer in a direction parallel to the interface. Semiconductor equipment.
(Appendix 10)
The third nitride semiconductor and the fourth nitride semiconductor are any of the appendices 1 to 9 characterized by containing n-type impurities at a concentration of 1 × 10 ¹⁷ cm ^-3 to 5 × 10 ²⁰ cm ^-3 . The semiconductor device according to item 1.
(Appendix 11)
The item according to any one of Supplementary note 1 to 10, wherein the third nitride semiconductor and the fourth nitride semiconductor contain Si, Ge or O or any combination thereof as n-type impurities. Semiconductor device.
(Appendix 12)
An amplifier comprising the semiconductor device according to any one of Supplementary note 1 to 11.
(Appendix 13)
A power supply device comprising the semiconductor device according to any one of Supplementary note 1 to 11.

1s: Source electrode 1d: Drain electrode 1g: Gate electrode 100, 200: Semiconductor device 101: Substrate 102: Channel layer 103, 203: Barrier layer 112d: Contact layer 112s: Contact layer

Claims (7)

The base of the first nitride semiconductor and
The channel layer of the second nitride semiconductor provided above the substrate and
A barrier layer provided above the channel layer and
The first opening and the second opening provided in the channel layer and the barrier layer, and
A first contact layer of a third nitride semiconductor, which is provided in the first opening and is in contact with the channel layer and has conductivity.
A second contact layer of a fourth nitride semiconductor, which is provided in the second opening and is in contact with the channel layer and has conductivity.
With the source electrode provided on the first contact layer,
The drain electrode provided on the second contact layer and
Above the barrier layer, a gate electrode provided between the source electrode and the drain electrode, and
Have,
A semiconductor device characterized in that the lower end of the conduction band of the channel layer is higher than the Fermi level in a state where no voltage is applied to the gate electrode. The semiconductor device according to claim 1, wherein the thickness of the channel layer is 50 nm or less. In plan view,
A part of the first contact layer and a part of the gate electrode overlap each other,
The semiconductor device according to claim 1 or 2, wherein a part of the second contact layer and a part of the gate electrode overlap each other. The semiconductor device according to any one of claims 1 to 3, wherein the barrier layer is an amorphous layer. The semiconductor device according to any one of claims 1 to 3, wherein the barrier layer is a semiconductor layer of a fifth nitride semiconductor. The first opening and the second opening have penetrated into the base.
The semiconductor device according to any one of claims 1 to 5, wherein the first contact layer and the second contact layer come into contact with the substrate. The first nitride semiconductor is AlN and is
The semiconductor device according to any one of claims 1 to 6, wherein the second nitride semiconductor is GaN.

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