JP2022110730A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device and a manufacturing method of the semiconductor device, which can achieve both high current and high withstand voltage with easy processing.SOLUTION: A semiconductor device includes a substrate, a semiconductor laminated structure including a nitride semiconductor channel layer and a barrier layer provided above the substrate, and a gate electrode, a source electrode, and a drain electrode above the barrier layer, and the barrier layer has an amorphous region spaced apart from the surface of the barrier layer on the substrate side in a first portion that overlaps the end of the gate electrode on the drain electrode side in plan view.SELECTED DRAWING: Figure 7

Description

The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Nitride semiconductors have characteristics such as a high saturated electron velocity and a wide bandgap. For this reason, various studies have been made on the application of nitride semiconductors to high withstand voltage and high output semiconductor devices by utilizing these characteristics. For example, the bandgap of GaN, which is a type of nitride semiconductor, is 3.4 eV, which is larger than the bandgap of Si (1.1 eV) and the bandgap of GaAs (1.4 eV). For this reason, GaN has a high breakdown electric field strength, and is extremely promising as a material for semiconductor devices for power supplies that can operate at high voltages and obtain high output.

As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, among GaN-based HEMTs, AlGaN/GaN-HEMTs using GaN as a channel layer and AlGaN as a barrier layer have attracted attention.

A technique for modulating the concentration of a two-dimensional gas (2DEG) has been proposed in order to achieve both a high current and a high breakdown voltage in a GaN-based HEMT.

JP 2009-10216 A JP 2008-235347 A

Influence of surface states on the two-dimensional electron gas in AlGaN/GaN heterojunction field-effect transistors, J. Appl. Phys., 93 No.12, 15 (2003)

However, in the conventional technique, the process for modulating the density of the 2DEG is complicated, and it is difficult to achieve both a high current and a high withstand voltage with a simple process.

An object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can achieve both high current and high withstand voltage with easy processing.

According to one aspect of the present disclosure, a semiconductor laminated structure including a substrate, a nitride semiconductor channel layer and a barrier layer provided above the substrate, and a gate electrode, a source electrode, and a drain above the barrier layer and an electrode, wherein the barrier layer has an amorphous region spaced from a surface of the barrier layer on the substrate side in a first portion overlapping an end portion of the gate electrode on the drain electrode side in plan view. An apparatus is provided.

According to the present disclosure, it is possible to achieve both high current and high withstand voltage with easy processing.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment; FIG. FIG. 3 is a cross-sectional view (part 1) showing the method for manufacturing the semiconductor device according to the first embodiment; 2 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view (part 3) showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view (part 4) showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. FIG. 10 is a cross-sectional view (No. 5) showing the method for manufacturing the semiconductor device according to the first embodiment; It is a cross-sectional view showing a semiconductor device according to a second embodiment. 4A to 4C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; 1 is a cross-sectional view showing a semiconductor device according to a first reference example; FIG. FIG. 11 is a cross-sectional view showing a semiconductor device according to a second reference example; It is a figure which shows distribution of electric field strength. It is a figure which shows the relationship between a gate voltage and an electric current. It is a figure which shows the discrete package which concerns on 3rd Embodiment. FIG. 11 is a wiring diagram showing a PFC circuit according to a fourth embodiment; It is a connection diagram which shows the power supply device which concerns on 5th Embodiment. FIG. 11 is a connection diagram showing an amplifier according to a sixth embodiment;

Embodiments of the present disclosure will be specifically described below with reference to the accompanying drawings. In the present specification and drawings, constituent elements having substantially the same functional configuration may be denoted by the same reference numerals, thereby omitting redundant description.

(First embodiment)
First, the first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT). FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

A semiconductor device 100 according to the first embodiment has a substrate 110 and a nitride semiconductor multilayer structure 120 formed on the substrate 110, as shown in FIG. The nitride semiconductor layered structure 120 includes a nucleation layer 121 , a buffer layer 122 , a channel layer 123 , a spacer layer 124 , a barrier layer 125 and a cap layer 126 . A nucleation layer 121 is formed over the substrate 110 . A buffer layer 122 is formed over the nucleation layer 121 . A channel layer 123 is formed on the buffer layer 122 . A spacer layer 124 is formed over the channel layer 123 . A barrier layer 125 is formed over the spacer layer 124 . A cap layer 126 is formed over the barrier layer 125 layer. The nitride semiconductor laminated structure 120 is an example of a semiconductor laminated structure.

The substrate 110 is, for example, a Si substrate. The nucleation layer 121 is, for example, an AlN layer with a thickness of 150 nm to 170 nm. The buffer layer 122 includes, for example, a plurality of Al _x Ga _1-x N layers (0.20<x<0.80) with different Al compositions x. The Al composition x may be highest on the nucleation layer 121 side and lowest on the channel layer 123 side. The thickness of the buffer layer 122 is, for example, 400 nm to 600 nm. The channel layer 123 is, for example, a GaN layer (i-GaN layer) with a thickness of 800 nm to 1200 nm and not intentionally doped with impurities. The spacer layer 124 is, for example, an Al _0.2 Ga _0.8 N layer (i-Al _0.2 Ga _0.8 N layer) with a thickness of 4 nm to 6 nm and not intentionally doped with impurities. . The barrier layer 125 is, for example, an n-type Al _0.2 Ga _0.8 N layer with a thickness of 10 nm to 40 nm. InAlGaN may be used as the material of the barrier layer 125 . The cap layer 126 is, for example, a 2 nm to 15 nm In _y Al _z Ga _1-yz N layer (0.0<y≦1.0, 0.0≦z<1.0).

An element isolation region that defines an element region is formed in the nitride semiconductor multilayer structure 120. Within the element region, an opening 132 for a source and an opening 132 for a drain are formed in the spacer layer 124, the barrier layer 125 and the cap layer 126. An opening 133 is formed. The openings 132 and 133 may be formed to enter the surface layer of the channel layer 123 . A source electrode 102 is formed in the opening 132 and a drain electrode 103 is formed in the opening 133 . The source electrode 102 and drain electrode 103 include, for example, a Ta film with a thickness of 10 nm to 50 nm and an Al film thereon with a thickness of 100 nm to 500 nm. The source electrode 102 and the drain electrode 103 are in ohmic contact with the nitride semiconductor multilayer structure 120 .

An insulating film 141 is formed on the nitride semiconductor multilayer structure 120 to cover the source electrode 102 and the drain electrode 103 . The insulating film 141 is, for example, a Si nitride film. The insulating film 141 has a gate opening 131 positioned between the source electrode 102 and the drain electrode 103 in plan view. It is formed on the insulating film 141 . The gate electrode 101 includes, for example, a Ni film with a thickness of 10 nm to 50 nm and an Au film thereon with a thickness of 300 nm to 500 nm, and is in Schottky contact with the nitride semiconductor multilayer structure 120 . The gate electrode 101 may contain Ni, Pt, Au, Mo, W, Al, Pd, Ti, or two or more of these.

The gate electrode 101 has a portion overlapping with the opening 131 , a portion closer to the drain electrode 103 than the opening 131 , and a portion closer to the source electrode 102 in plan view. In plan view, the portion closer to the drain electrode 103 than the opening 131 and the portion closer to the source electrode 102 are above the insulating film 141 .

The barrier layer 125 has an amorphous region 129 spaced from the bottom surface of the barrier layer 125 (substrate 110 side surface) in a first portion that overlaps the drain electrode 103 side end of the gate electrode 101 in plan view. Amorphous region 129 may also be formed in cap layer 126 .

In the semiconductor device 100 , a two-dimensional electron gas (2DEG) 105 exists near the upper surface of the channel layer 123 . The concentration of the 2DEG 105 depends on, for example, the amount of polarization charges in the barrier layer 125, and becomes higher below the portion where there are more polarization charges. Barrier layer 125 is crystallized except for amorphous region 129 , in which no polarization charges are formed, and polarization charges are formed in crystallized regions of barrier layer 125 . Moreover, in this embodiment, the thickness of the barrier layer 125 is substantially uniform. Accordingly, the concentration of the 2DEG 105 is low immediately below the amorphous region 129 . Therefore, electric field concentration in the vicinity of the end of the gate electrode 101 on the drain electrode 103 side is suppressed, and the withstand voltage is improved.

Further, since the barrier layer 125 is crystallized on the source electrode 102 side of the gate electrode 101, the sheet resistance can be kept low. Furthermore, since the drain electrode 103 side of the gate electrode 101 is also crystallized except for the amorphous region 129, the sheet resistance can be kept low on the drain electrode 103 side as well. Therefore, sufficient ON current can be obtained.

Thus, according to the present embodiment, it is possible to achieve both high current and high withstand voltage. Furthermore, the amorphous region 129 can be formed by a simple process, which will be described later in detail.

Note that the spacer layer 124, the cap layer 126, or both may not be provided.

Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. 2 to 6 are cross-sectional views showing the method of manufacturing the semiconductor device 100 according to the first embodiment.

First, as shown in FIG. 2, the nitride semiconductor multilayer structure 120 is formed on the substrate 110 . In forming the nitride semiconductor layer stack 120, the nucleation layer 121, the buffer layer 122, the channel layer 123, the barrier layer 125, and the cap layer 126 are deposited, for example, by metal organic chemical vapor deposition. deposition (MOCVD) method or molecular beam epitaxy (MBE) method. Here, it is assumed that the nitride semiconductor multilayer structure 120 is formed by the MOCVD method. When the nitride semiconductor multilayer structure 120 is formed by the MOCVD method, source gases include, for example, trimethyl aluminum (TMAl) gas as an Al source, trimethyl gallium (TMGa) gas as a Ga source, and trimethyl gallium (TMGa) gas as an In source. A mixed gas of indium (TMIn) gas and ammonia (NH ₃ ) gas as an N source is used. Hydrogen (H ₂ ) gas or nitrogen (N ₂ ) gas is used as a carrier gas. Whether or not to supply TMAl gas, TMGa gas, and TMIn gas and their flow rates are appropriately set according to the composition of the nitride semiconductor layer to be grown. The flow rate of NH ₃ gas is, for example, about 100 ccm to 10 Lm.

For example, when forming the nitride semiconductor multilayer structure 120, the growth pressure is about 1 kPa to 100 kPa, preferably about 7 kPa (50 Torr) to about 40 kPa (300 Torr), and the growth temperature is about 1000.degree. The formation of the barrier layer 125 causes the 2DEG 105 near the upper surface of the channel layer 123 . At this point, the concentration of the 2DEG 105 is substantially uniform within the plane.

After forming the nitride semiconductor multilayer structure 120 , an element isolation region that defines an element region is formed in the nitride semiconductor multilayer structure 120 . In the formation of the element isolation region, for example, a photoresist pattern that exposes the region where the element isolation region is to be formed is formed on the nitride semiconductor multilayer structure 120, and ion implantation of Ar or the like is performed using this pattern as a mask. . Dry etching using a chlorine-based gas may be performed using this pattern as an etching mask.

Next, as shown in FIG. 3, an amorphous region 129 is formed in the cap layer 126 and the barrier layer 125 by ion implantation. Ion implantation can be performed using, for example, a focused ion beam (FIB) device. The implanted ions are, for example, Ar ions. For example, the acceleration voltage is about 10 keV to 100 keV. When Ar ions are implanted at an acceleration voltage of 10 keV, the Ar ions penetrate to a depth of about 7 μm from the surface, forming an amorphous region 129 with a depth of about 7 μm. Si ions, Ge ions, N ions, Ne ions, or the like may be used for ion implantation.

Thereafter, as shown in FIG. 4, a source opening 132 and a drain opening 133 are formed in the spacer layer 124, the barrier layer 125 and the cap layer 126. Then, as shown in FIG. The openings 132 and 133 may be formed to enter the surface layer of the channel layer 123 . In forming the openings 132 and 133, for example, a pattern of photoresist that exposes the regions where the openings 132 and 133 are to be formed is formed on the nitride semiconductor multilayer structure 120 by photolithography. Dry etching is performed using a chlorine-based gas using the pattern as an etching mask.

Subsequently, the source electrode 102 is formed inside the opening 132 and the drain electrode 103 is formed inside the opening 133 . The source electrode 102 and drain electrode 103 can be formed by, for example, a lift-off method. That is, a pattern of photoresist is formed to expose the regions where the source electrode 102 and the drain electrode 103 are to be formed, a metal film is formed by vapor deposition using this pattern as a growth mask, and this pattern is deposited together with the metal film thereon. Remove. In forming the metal film, for example, a Ta film is formed and an Al film is formed thereon. Then, for example, heat treatment is performed at 400° C. to 1000° C. (eg, 550° C.) in a nitrogen atmosphere to establish ohmic characteristics.

Next, as shown in FIG. 5 , an insulating film 141 is formed on the nitride semiconductor multilayer structure 120 to cover the source electrode 102 and the drain electrode 103 . The insulating film 141 can be formed by plasma CVD, for example. The insulating film 141 may be formed by an atomic layer deposition (ALD) method or a sputtering method.

After that, an opening 131 for a gate is formed in the insulating film 141 . In forming the opening 131, for example, a photoresist pattern exposing a region where the opening 131 is to be formed is formed on the insulating film 141 by photolithography, and a fluorine-based gas or a chlorine-based gas is applied using this pattern as an etching mask. Dry etching is performed using gas. Wet etching using hydrofluoric acid, buffered hydrofluoric acid, or the like may be performed instead of dry etching.

Subsequently, as shown in FIG. 6 , the gate electrode 101 is formed on the insulating film 141 so as to contact the nitride semiconductor multilayer structure 120 through the opening 131 . The gate electrode 101 can be formed by, for example, a lift-off method. That is, a photoresist pattern is formed to expose a region where the gate electrode 101 is to be formed, a metal film is formed by vapor deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In forming the metal film, for example, a Ni film is formed and an Au film is formed thereon.

Thus, the semiconductor device 100 according to the first embodiment can be manufactured.

In this embodiment, the amorphous region 129 is formed by ion implantation. Therefore, the amorphous regions 129 can be easily formed at desired positions. Further, when ion implantation is performed using an FIB device, processes such as mask formation and removal are not required.

Note that the amorphous region 129 may be formed after the source electrode 102 and the drain electrode 103 are formed.

(Second embodiment)
Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the amorphous region. FIG. 7 is a cross-sectional view showing the semiconductor device according to the second embodiment.

In the semiconductor device 200 according to the second embodiment, the barrier layer 125 has an amorphous region 229 instead of the amorphous region 129, as shown in FIG. The amorphous region 229 is formed over the entire region of the barrier layer 125 on the side of the drain electrode 103 from the position overlapping the wall surface of the opening 131 on the side of the drain electrode 103 in plan view. Amorphous region 229 , like amorphous region 129 , is spaced from the lower surface of barrier layer 125 . The depth of the amorphous region 229 is not constant, and the amorphous region 229 becomes deeper from the drain electrode 103 side to the gate electrode 101 side. For example, the depth of amorphous region 229 varies continuously. The depth of the amorphous region 229 may change stepwise. Amorphous region 229 may also be formed in cap layer 126 .

Other configurations are the same as those of the first embodiment.

According to the second embodiment, as in the first embodiment, both high current and high withstand voltage can be achieved. Further, the concentration of the 2DEG 105 can be continuously changed on the drain electrode 103 side of the gate electrode 101 . Furthermore, as will be described later, amorphous region 229 can be formed by easy processing.

Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. FIG. 8 is a cross-sectional view showing a method of manufacturing a semiconductor device 200 according to the second embodiment.

First, in the same manner as in the first embodiment, the processes up to the formation of the nitride semiconductor multilayer structure 120 and the element isolation regions are performed (see FIG. 2). Next, as shown in FIG. 8, an amorphous region 229 is formed in the cap layer 126 and the barrier layer 125 by ion implantation. Ion implantation can be performed using, for example, an FIB device. The implanted ions are, for example, Ar ions. For example, the acceleration voltage is about 10 keV to 100 keV. In the second embodiment, for example, ion implantation is performed while moving the focused ion beam irradiation position from the region where the drain electrode 103 is to be formed to the region where the gate electrode 101 is to be formed. In addition, the accelerating voltage is continuously increased in accordance with the movement of the irradiation position. As a result, as shown in FIG. 8, an amorphous region 229 is formed which is deep from the region where the drain electrode 103 is to be formed to the region where the gate electrode 101 is to be formed. Si ions, Ge ions, N ions, Ne ions, or the like may be used for ion implantation.

After that, the processes after forming the openings 132 and 133 are performed in the same manner as in the first embodiment.

Thus, the semiconductor device 200 according to the second embodiment can be manufactured.

In this embodiment, the amorphous region 229 is formed by ion implantation. Therefore, the amorphous regions 229 can be easily formed at desired positions. Further, by performing ion implantation using an FIB device, the concentration of the 2DEG 105 can be changed continuously.

Here, the results of the simulation of the characteristics of the second embodiment will be described in comparison with two reference examples (first reference example and second reference example). FIG. 9 is a cross-sectional view showing a semiconductor device according to a first reference example, and FIG. 10 is a cross-sectional view showing a semiconductor device according to a second reference example.

In the semiconductor device 800 according to the first reference example, as shown in FIG. 9, the amorphous region 229 is not formed in the cap layer 126 and the barrier layer 125, and the concentration of the 2DEG 105 is from the vicinity of the source electrode 102 to the vicinity of the drain electrode 103. Almost uniform. Other configurations are the same as those of the second embodiment.

In the semiconductor device 900 according to the second reference example, as shown in FIG. 10, the insulating film 141 is provided only on the source electrode 102 side of the gate electrode 101, and the insulating film 141 is provided on the drain electrode 103 side of the gate electrode 101. An insulating film 941 is provided instead. The insulating film 941 has the effect of relaxing the strain of the barrier layer 125, and the concentration of the 2DEG 105 is lower on the drain electrode 103 side than on the source electrode 102 side than on the gate electrode 101 side. Other configurations are the same as those of the second embodiment.

In the simulation, the electric field intensity below the end of the gate electrode 101 on the drain electrode 103 side was calculated. Also, the relationship between the gate voltage and the current flowing between the source electrode 102 and the drain electrode 103 was calculated. These results are shown in FIGS. 11 and 12. FIG. FIG. 11 is a diagram showing distribution of electric field intensity. FIG. 12 is a diagram showing the relationship between gate voltage and current.

As shown in FIG. 11, according to the second embodiment and the second reference example, the electric field intensity can be relaxed more than the first reference example. Therefore, high breakdown voltage is possible. 11 corresponds to the interface between the gate electrode 101 and the insulating film 141 at the end on the drain electrode 103 side. Further, as shown in FIG. 12, according to the second embodiment, a higher current than that of the second reference example can be obtained in the range where the gate voltage exceeds 0V. Therefore, it is possible to increase the current.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment relates to a HEMT discrete package. FIG. 13 is a diagram showing a discrete package according to the third embodiment.

In the third embodiment, as shown in FIG. 13, a land (die pad) 1233 is formed on the back surface of a semiconductor device 1210 having a structure similar to that of any one of the first and second embodiments using a die attach agent 1234 such as solder. is fixed to A wire 1235 d such as an Al wire is connected to the drain pad 1226 d to which the drain electrode 103 is connected, and the other end of the wire 1235 d is connected to a drain lead 1232 d integrated with the land 1233 . A wire 1235 s such as an Al wire is connected to a source pad 1226 s connected to the source electrode 102 , and the other end of the wire 1235 s is connected to a source lead 1232 s independent of the land 1233 . A wire 1235g such as an Al wire is connected to a gate pad 1226g connected to the gate electrode 101, and the other end of the wire 1235g is connected to a gate lead 1232g independent of the land 1233. FIG. A land 1233, a semiconductor device 1210, and the like are packaged with a mold resin 1231 so that a portion of the gate lead 1232g, a portion of the drain lead 1232d, and a portion of the source lead 1232s protrude.

Such a discrete package can be manufactured, for example, as follows. First, a semiconductor device 1210 is fixed to a land 1233 of a lead frame using a die attach agent 1234 such as solder. Gate pad 1226g is then connected to leadframe gate lead 1232g, drain pad 1226d to leadframe drain lead 1232d, and source pad 1226s to the leadframe source by bonding using wires 1235g, 1235d and 1235s. Connect to lead 1232s. After that, sealing using a mold resin 1231 is performed by a transfer molding method. Then, the lead frame is separated.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment relates to a PFC (Power Factor Correction) circuit with HEMT. FIG. 14 is a wiring diagram showing a PFC circuit according to the fourth embodiment.

The PFC circuit 1250 includes a switch element (transistor) 1251 , a diode 1252 , a choke coil 1253 , capacitors 1254 and 1255 , a diode bridge 1256 and an alternating current power supply (AC) 1257 . A drain electrode of the switch element 1251, an anode terminal of the diode 1252, and one terminal of the choke coil 1253 are connected. A source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255 . The other terminal of capacitor 1254 and the other terminal of choke coil 1253 are connected. The other terminal of capacitor 1255 and the cathode terminal of diode 1252 are connected. A gate driver is connected to the gate electrode of the switch element 1251 . AC 1257 is connected across capacitor 1254 via diode bridge 1256 . A direct current power supply (DC) is connected between both terminals of the capacitor 1255 . In this embodiment, a semiconductor device having a structure similar to that of any one of the first and second embodiments is used for the switch element 1251 .

When manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252, the choke coil 1253, and the like using, for example, solder.

(Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment relates to a power supply device having a HEMT suitable for server power supply. FIG. 15 is a wiring diagram showing a power supply device according to the fifth embodiment.

The power supply device includes a high-voltage primary circuit 1261 , a low-voltage secondary circuit 1262 , and a transformer 1263 arranged between the primary circuit 1261 and the secondary circuit 1262 .

The primary side circuit 1261 is provided with the PFC circuit 1250 according to the fourth embodiment and an inverter circuit, for example, a full bridge inverter circuit 1260 connected between both terminals of the capacitor 1255 of the PFC circuit 1250 . The full bridge inverter circuit 1260 is provided with a plurality (here, four) of switch elements 1264a, 1264b, 1264c and 1264d.

The secondary circuit 1262 is provided with a plurality of (here, three) switch elements 1265a, 1265b, and 1265c.

In this embodiment, the switch element 1251 of the PFC circuit 1250 that constitutes the primary side circuit 1261 and the switch elements 1264a, 1264b, 1264c and 1264d of the full bridge inverter circuit 1260 are the same as those in any of the first and second embodiments. A semiconductor device having a structure is used. On the other hand, the switching elements 1265a, 1265b, and 1265c of the secondary circuit 1262 are ordinary MIS type FETs (field effect transistors) using silicon.

(Sixth embodiment)
Next, a sixth embodiment will be described. The sixth embodiment relates to an amplifier with HEMT. FIG. 16 is a connection diagram showing an amplifier according to the sixth embodiment.

The amplifier includes a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273. FIG.

Digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the nonlinear distortion-compensated input signal and the AC signal. The power amplifier 1273 includes a semiconductor device having a structure similar to that of any one of the first and second embodiments, and amplifies an input signal mixed with an AC signal. In this embodiment, for example, by switching a switch, the signal on the output side can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. FIG. This amplifier can be used as a high frequency amplifier and a high power amplifier. High-frequency amplifiers can be used, for example, in mobile phone base station transceivers, radar devices, and microwave generators.

In the present disclosure, the structures of the gate electrode, source electrode and drain electrode are not limited to those of the above embodiments. For example, they may consist of a single layer. Also, the formation method for these is not limited to the lift-off method. Furthermore, if ohmic characteristics can be obtained, the heat treatment after forming the source and drain electrodes may be omitted. Heat treatment may be performed after the formation of the gate electrode.

A silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate may be used as the substrate. The substrate may be conductive, semi-insulating or insulating.

As the structure of the gate electrode, a Schottky type gate structure is used in the above embodiments, but a MIS (metal-insulator-semiconductor) type gate structure may be used.

The composition of the nitride semiconductor layer included in the semiconductor laminated structure is not limited to that described in the above embodiments. For example, nitride semiconductors such as InAlN and InGaAlN may be used.

Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope of the claims. Modifications and substitutions can be made.

Hereinafter, various aspects of the present disclosure will be collectively described as appendices.

(Appendix 1)
a substrate;
a semiconductor laminated structure including a nitride semiconductor channel layer and a barrier layer provided above the substrate;
a gate electrode, a source electrode and a drain electrode above the barrier layer;
has
The semiconductor device according to claim 1, wherein the barrier layer has an amorphous region spaced from a surface of the barrier layer on the substrate side in a first portion overlapping an end portion of the gate electrode on the drain electrode side in plan view.
(Appendix 2)
The semiconductor device according to Supplementary Note 1, wherein the amorphous region is provided on the drain electrode side of the barrier layer with respect to the first portion.
(Appendix 3)
3. The semiconductor device according to appendix 1 or 2, wherein the amorphous region is deep from the drain electrode side to the gate electrode side.
(Appendix 4)
3. The semiconductor device according to claim 3, wherein the depth of the amorphous region is continuously changed.
(Appendix 5)
5. The semiconductor device according to any one of appendices 1 to 4, wherein the barrier layer is crystallized except for the amorphous region.
(Appendix 6)
forming a semiconductor laminated structure including a nitride semiconductor channel layer and a barrier layer over a substrate;
forming a gate electrode, a source electrode and a drain electrode over the barrier layer;
has
In the step of forming the semiconductor laminated structure, ions are implanted into the barrier layer so that a first portion overlapping an end portion of the gate electrode on the drain electrode side in a plan view is formed with the substrate side of the barrier layer. 1. A method of manufacturing a semiconductor device, comprising the step of forming an amorphous region spaced apart from the surface of the semiconductor device.
(Appendix 7)
7. The method of manufacturing a semiconductor device according to claim 6, wherein the amorphous region is also formed closer to the drain electrode than the first portion of the barrier layer.
(Appendix 8)
8. The method of manufacturing a semiconductor device according to appendix 6 or 7, wherein the amorphous region is formed deeply from the drain electrode side to the gate electrode side.
(Appendix 9)
9. The method of manufacturing a semiconductor device according to any one of Appendices 6 to 8, wherein the ion implantation is performed using a focused ion beam device.
(Appendix 10)
10. The method of manufacturing a semiconductor device according to any one of Appendices 6 to 9, wherein in the step of implanting ions, Ar ions, Si ions, Ge ions, N ions, or Ne ions are implanted.
(Appendix 11)
An amplifier comprising the semiconductor device according to any one of Appendices 1 to 5.
(Appendix 12)
A power supply device comprising the semiconductor device according to any one of Appendices 1 to 5.

100, 200: semiconductor device 101: gate electrode 102: source electrode 103: drain electrode 110: substrate 120: nitride semiconductor multilayer structure 123: channel layer 125: barrier layer 129, 229: amorphous region

Claims (7)

a substrate;
a semiconductor laminated structure including a nitride semiconductor channel layer and a barrier layer provided above the substrate;
a gate electrode, a source electrode and a drain electrode above the barrier layer;
has
The semiconductor device according to claim 1, wherein the barrier layer has an amorphous region spaced from a surface of the barrier layer on the substrate side in a first portion overlapping an end portion of the gate electrode on the drain electrode side in plan view. 2. The semiconductor device according to claim 1, wherein the amorphous region is also provided closer to the drain electrode than the first portion of the barrier layer. 3. The semiconductor device according to claim 1, wherein said amorphous region is deep from said drain electrode side to said gate electrode side. forming a semiconductor laminated structure including a nitride semiconductor channel layer and a barrier layer over a substrate;
forming a gate electrode, a source electrode and a drain electrode over the barrier layer;
has
In the step of forming the semiconductor laminated structure, ions are implanted into the barrier layer so that a first portion overlapping an end portion of the gate electrode on the drain electrode side in a plan view is formed with the substrate side of the barrier layer. 1. A method of manufacturing a semiconductor device, comprising the step of forming an amorphous region spaced apart from the surface of the semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the amorphous region is also formed closer to the drain electrode than the first portion of the barrier layer. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the amorphous region is formed deeply from the drain electrode side to the gate electrode side. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the ion implantation is performed using a focused ion beam device.

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