JP2014090033A - Compound semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a highly reliable compound semiconductor device which achieves successful normally-off without causing problems such as increase in electrical resistance and an unstable operation, which are caused by dry etching of a p-type semiconductor layer though the p-type semiconductor layer is used for controlling 2DEG.SOLUTION: An AlGaN/GaN HEMT comprises: a compound semiconductor lamination structure 2; a gate electrode 7 formed above the compound semiconductor lamination structure 2; and a p-type semiconductor layer 3a locally formed between the compound semiconductor lamination structure 2 and the gate electrode 7. The compound semiconductor lamination structure 2 has flatness to an atomic step level on a surface in an unformed surface where the p-type semiconductor layer 3a is not formed.

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  Nitride semiconductors have been studied for application to high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. For example, the band gap of GaN, which is a nitride semiconductor, is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, GaN is extremely promising as a material for a semiconductor device for a power supply that obtains high voltage operation and high output.

  As devices using nitride semiconductors, many reports have been made on field effect transistors, in particular, high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT (GaN-HEMT), AlGaN / GaN.HEMT using GaN as an electron transit layer and AlGaN as an electron supply layer has attracted attention. In AlGaN / GaN.HEMT, strain caused by the difference in lattice constant between GaN and AlGaN is generated in AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization of AlGaN. Therefore, it is expected as a high-efficiency power device for high-efficiency switching elements, electric vehicles and the like.

JP-A-10-189533 JP 2009-38175 A

Yasuhiro Uemoto, Masahiro Hikita, Hiroaki Ueno, Hisayoshi Matsuo, Hidetoshi Ishida, Manabu Yanagihara, Tetsuzo Ueda, Tsuyoshi Tanaka, and Daisuke Ueda, "Gate Injection Transistor (GIT)-A Normally-off AlGaN / GaN Power Transistor Using Conductivity Modulation", IEEE TRANSACTIONS ON ELECTRON DEVICES, 54, 3393 (2007). Masahiro Hikida, Manabu Yanagihara, Yasuhiro Uemoto, Tetsuzo Ueda, Kei Tanaka, Daisuke Ueda, "GaN Power Device", Panasonic Technical Journal Vol.55, No.2, (2009)

In nitride semiconductor devices, a technique for locally controlling the amount of 2DEG generated is required. For example, in the case of HEMT, from the viewpoint of so-called fail-safe, it is desired to realize so-called normally-off in which no current flows when the voltage is turned off. For this purpose, it is necessary to devise a technique for suppressing the amount of 2DEG generated below the gate electrode when the voltage is turned off.
As one of the methods for realizing a normally-off GaN / HEMT, a p-type semiconductor layer such as a p-type GaN layer or a p-type AlGaN layer is formed between a compound semiconductor multilayer structure and a gate electrode. A method for controlling the concentration of 2DEG by a modulation effect has been proposed.

  In a structure in which a p-type semiconductor layer is arranged on a compound semiconductor multilayer structure, 2DEG does not exist due to the diffusion potential of the pn junction when no voltage is applied, and the diffusion potential of the pn junction is decreased by applying a positive voltage. By doing so, 2DEG is generated and conduction is obtained. Therefore, when a p-type semiconductor layer is used, it is necessary to remove the p-type semiconductor layer existing in a region other than under the gate electrode to which a voltage is applied by dry etching and generate 2DEG in the region.

However, in this case, the following problems are caused due to dry etching of the p-type semiconductor layer.
The compound semiconductor multilayer structure is damaged by dry etching of the p-type semiconductor layer, and the electrical resistance of the 2DEG traveling region in the compound semiconductor multilayer structure increases.
Roughness occurs on the surface of the compound semiconductor multilayer structure, and the instability of operation is caused by the formation of interface states due to the rough surface.
Non-uniformity occurs in the remaining amount of the p-type semiconductor layer during etching, and electrical resistance increases due to over-etching of the compound semiconductor multilayer structure. Due to the non-uniformity of the remaining amount and over-etching, instability and non-uniformity are exerted on the formation of the ohmic electrode. Further, in a mass production process using a large-diameter substrate, there is a problem that a large distribution of electric resistance is formed in the substrate surface due to non-uniformity of the remaining amount and over-etching.

  The present invention has been made in view of the above problems. The object of the present invention is to use a p-type semiconductor layer to control 2DEG, but without causing problems such as an increase in electrical resistance and operational instability caused by dry etching of the p-type semiconductor layer. It is an object to provide a highly reliable compound semiconductor device that realizes a normally-off and a manufacturing method thereof.

  One aspect of the compound semiconductor device includes a compound semiconductor multilayer structure, an electrode formed above the compound semiconductor multilayer structure, and a p-type semiconductor layer locally formed between the compound semiconductor multilayer structure and the electrode In the compound semiconductor multilayer structure, the non-formation surface of the p-type semiconductor layer has an atomic step level flatness on the surface thereof.

  One aspect of a method for manufacturing a compound semiconductor device includes a step of forming a compound semiconductor multilayer structure, a step of forming a p-type semiconductor layer above the compound semiconductor multilayer structure, and heat-treating the p-type semiconductor layer, A step of leaving a part of the p-type semiconductor layer and a step of forming an electrode above the remaining p-type semiconductor layer, and the compound semiconductor multilayer structure is formed on the surface of the p-type semiconductor layer by the heat treatment. The non-formed surface has flatness at the atomic step level.

  According to each aspect described above, a p-type semiconductor layer is used for controlling 2DEG, but without causing problems such as an increase in electrical resistance and operational instability caused by dry etching of the p-type semiconductor layer. Thus, a highly reliable compound semiconductor device that realizes reliable normally-off is realized.

It is a schematic sectional drawing which shows the manufacturing method of AlGaN / GaN * HEMT by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 1. FIG. 3 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 2. 1 is a schematic plan view showing a HEMT chip using an AlGaN / GaN.HEMT according to a first embodiment. 1 is a schematic plan view showing a discrete package of a HEMT chip using an AlGaN / GaN.HEMT according to a first embodiment. It is a connection diagram which shows the PFC circuit by 2nd Embodiment. It is a connection diagram which shows schematic structure of the power supply device by 3rd Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 4th Embodiment.

Hereinafter, embodiments will be described in detail with reference to the drawings. In the following embodiments, the structure of a compound semiconductor device will be described along with its manufacturing method.
In the following drawings, there are constituent members that are not shown in a relatively accurate size and thickness for convenience of illustration.

(First embodiment)
In this embodiment, AlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
1 to 3 are schematic cross-sectional views showing the AlGaN / GaN HEMT manufacturing method according to the present embodiment in the order of steps.

  First, as shown in FIGS. 1A and 1B, a compound semiconductor multilayer structure 2 and a p-type semiconductor layer 3 are formed on a semi-insulating SiC substrate 1 as a growth substrate, for example. As the growth substrate, a sapphire substrate, GaAs substrate, Si substrate, GaN substrate, or the like may be used instead of the SiC substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.

  The compound semiconductor multilayer structure 2 includes a buffer layer 2a, an electron transit layer 2b, an intermediate layer (spacer layer) 2c, and an electron supply layer 2d. A p-type semiconductor layer 3 is formed on the electron supply layer 2d. Note that thin n-GaN may be formed as a cap layer on the electron supply layer 2d, and a p-type semiconductor layer may be formed on the cap layer.

  In detail, the following compound semiconductors are epitaxially grown on the SiC substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.

On the SiC substrate 1, the respective compound semiconductors to be the buffer layer 2a, the electron transit layer 2b, the intermediate layer 2c, the electron supply layer 2d, and the p-type semiconductor layer 3 are sequentially grown. The buffer layer 2a is formed on the SiC substrate 1 by growing AlN to a thickness of about 0.1 μm, for example. The electron transit layer 2b is formed by growing i (intentional undoped) -GaN to a thickness of about 1 μm to 3 μm, for example, about 1 μm. The intermediate layer 2c is formed by growing i-AlGaN to a thickness of about 5 nm, for example. The electron supply layer 2d is formed by growing n-AlGaN to a thickness of about 20 nm, for example. The Al composition of n-AlGaN is about 10% to 30%, for example about 20% (Al _0.2 Ga _0.8 N). The p-type semiconductor layer 3 is formed by growing p-GaN to a thickness of about 60 nm, for example. The intermediate layer 2c may not be formed. The electron supply layer 2d may be formed of i-AlGaN. The p-type semiconductor layer 3 may be formed of p-AlGaN instead of p-GaN.

For the growth of GaN, a mixed gas of trimethylgallium (TMGa) gas and ammonia (NH ₃ ) gas, which is a Ga source, is used as a source gas. For the growth of AlGaN, a mixed gas of trimethylaluminum (TMAl) gas, TMGa gas and NH ₃ gas is used as a source gas. The presence / absence and flow rate of TMAl gas and TMGa gas are appropriately set according to the compound semiconductor layer to be grown. The flow rate of NH ₃ gas, which is a common raw material, is about 100 sccm to 10 slm. The growth pressure is about 50 Torr to 760 Torr, and the growth temperature is about 800 ° C. to 1200 ° C.

When growing AlGaN as n-type, that is, for forming the electron supply layer 2d (n-AlGaN), an n-type impurity is added to the AlGaN source gas. Here, for example, silane (SiH ₄ ) gas containing Si, for example, is added to the source gas at a predetermined flow rate, and AlGaN is doped with Si. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

When growing GaN as p-type, that is, for forming the p-type semiconductor layer 3 (p-GaN), a p-type impurity, for example, selected from Mg and Be, is added to the GaN source gas, and p-GaN is added. A polarity reversal crystal region is formed therein. In this embodiment, Mg is used as the p-type impurity. Mg is added to the source gas at a predetermined flow rate, and GaN is doped with Mg. The doping concentration of Mg is, for example, about 5 × 10 ¹⁹ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ . When the doping concentration is lower than about 5 × 10 ¹⁹ / cm ³ , the p-type is not sufficiently obtained and normally-on is obtained. If it is higher than about 1 × 10 ²⁰ / cm ³ , the crystallinity deteriorates and sufficient characteristics cannot be obtained. Therefore, by setting the Mg doping concentration to about 5 × 10 ¹⁹ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , a p-type semiconductor with sufficient characteristics can be obtained. In the present embodiment, the Mg doping concentration of the p-type semiconductor layer 3 is about 5 × 10 ¹⁹ / cm ³ .

As shown in FIG. 1A, in the state where the compound semiconductor multilayer structure 2 is formed, the interface between the electron transit layer 2c and the electron supply layer 2e (more precisely, the interface with the intermediate layer 2d. Hereinafter, GaN / AlGaN). Piezo polarization due to strain caused by the difference between the lattice constant of GaN and the lattice constant of AlGaN occurs at the interface). The piezoelectric polarization effect and the spontaneous polarization effect of the electron transit layer 2c and the electron supply layer 2e combine to generate a two-dimensional electron gas (2DEG) having a high electron concentration throughout the GaN / AlGaN interface.
When the p-type semiconductor layer 3 is formed on the compound semiconductor multilayer structure 2 as shown in FIG. 1B, the concentration of 2DEG is controlled by the band modulation effect, and 2DEG disappears in this embodiment.

Subsequently, an element isolation structure is formed.
Specifically, for example, argon (Ar) is implanted into the element isolation region of the compound semiconductor multilayer structure 2. Thereby, an element isolation structure is formed in the compound semiconductor multilayer structure 2. An active region is defined on the compound semiconductor multilayer structure 2 by the element isolation structure.
Note that element isolation may be performed using another known method such as an STI (Shallow Trench Isolation) method instead of the above implantation method. At this time, for example, a chlorine-based etching gas is used for the dry etching of the compound semiconductor multilayer structure 2.

Subsequently, as shown in FIG. 1C, a mask 10 is formed on the p-type semiconductor layer 3.
Specifically, high heat resistance such as SiO ₂ , Al ₂ O ₃ , SiN or the like is formed on the p-type semiconductor layer 3 by a film forming method such as CVD (Chemical Vapor Deposition), sputtering, vacuum deposition, or ALD (Atomic Layer Deposition). Deposit protective material. In this embodiment, SiO ₂ is formed to a thickness of about 30 nm by, for example, CVD. The deposited SiO ₂ is processed by lithography and dry etching to leave SiO ₂ in the region where the gate electrode is to be formed on the p-type semiconductor layer 3. Thus, the mask 10 made of SiO ₂ is formed on the p-type semiconductor layer 3.

Subsequently, as shown in FIG. 2A, the p-type semiconductor layer 3 is heat-treated.
Specifically, the SiC substrate 1 is placed in the chamber of the MOCVD apparatus, and the p-type semiconductor layer 3 is heat-treated with the mask 10 formed. The heat treatment conditions are such that hydrogen is introduced into the chamber to form a hydrogen atmosphere, and the temperature is in the range of about 900 ° C. to about 1100 ° C., here about 1000 ° C. By this heat treatment, p-GaN of the p-type semiconductor layer 3 evaporates due to thermal desorption in a region where the mask 10 does not exist, and p-GaN locally remains under the mask 10 in a region where the mask 10 exists. . The remaining p-GaN is defined as a p-type semiconductor layer 3a. At this time, a high Al composition AlGaN layer 4 having high heat resistance is formed on the surface layer of the electron supply layer 2d, and the progress of thermal desorption is suppressed. The high Al composition AlGaN layer 4 has a higher Al composition than other parts of the electron supply layer 2d (parts where the high Al composition AlGaN layer 4 is not formed). Specifically, the Al composition of the high Al composition AlGaN layer 4 is about 50% to 100%, for example, about 75% (Al _0.75 Ga _0.25 N). In the present embodiment, the high Al composition AlGaN layer 4 is formed on the surface layer of the electron supply layer 2d to a thickness of about 1 nm to 2 nm, for example, about 2 nm, and thermal desorption of GaN stops.

  By the heat treatment, the p-type semiconductor layer 3 other than the region under the mask 10 is completely removed. Among the surfaces of the electron supply layer 2d, the non-formation surface of the p-type semiconductor layer 3, that is, the surface of the high Al composition AlGaN layer 4 has extremely excellent flatness, here, the atomic step level (several atoms constituting the AlGaN). Flatness of a level difference (for example, about 0.26 nm level).

  If the temperature in the heat treatment is lower than about 900 ° C., sufficient thermal desorption of the p-type semiconductor layer 3 becomes difficult. If the temperature is higher than about 1100, it is difficult to leave the p-type semiconductor layer 3 under the mask 10. By setting the temperature within the range of about 900 ° C. to about 1100 ° C., the p-type semiconductor layer 3 outside the region under the mask 10 is completely removed, and the p-type semiconductor layer 3 is placed under the mask 10 by a predetermined amount. It can be left.

Due to the formation of the p-type semiconductor layer 3a, 2DEG disappears only in the region aligned below the p-type semiconductor layer 3a, and 2DEG is restored and generated in other regions.
Since the high Al composition AlGaN layer 4 is formed on the non-formation surface of the p-type semiconductor layer 3a in the surface of the electron supply layer 2d, the concentration of 2DEG is increased and a transistor with lower resistance is realized. On the other hand, since the high Al composition AlGaN layer 4 is not formed in the region where the gate electrode is to be formed, the concentration of 2DEG does not become higher than necessary.

Subsequently, as shown in FIG. 2B, the mask 10 is removed.
Specifically, the mask 10 is wet-treated using a predetermined chemical solution, for example, hydrofluoric acid. Thereby, the mask 10 is removed.

Subsequently, as shown in FIG. 2C, electrode recesses 2A and 2B are formed in the electron supply layer 2d.
Specifically, electrode recesses 2A and 2B are formed in regions where the source and drain electrodes are to be formed on the surface of the electron supply layer 2d of the compound semiconductor multilayer structure 2.
A resist mask is formed that opens the planned positions for forming the source electrode and the drain electrode on the surface of the electron supply layer 2 d, that is, on the surface of the high Al composition AlGaN layer 4. Using this resist mask, the high Al composition AlGaN layer 4 at the electrode formation scheduled position is removed by dry etching. The dry etching may be performed so as to remove part of the electron supply layer 2d under the high Al composition AlGaN layer 4. As the etching gas, for example, an inert gas such as Ar and a chlorine-based gas such as Cl ₂ are used. Thus, the electrode recesses 2A and 2B are formed in the electron supply layer 2d.

  The surface of the electron supply layer 2d (high Al composition AlGaN layer 4) on which the electrode recesses 2A and 2B are formed is a flat surface at the atomic step level as described above. Therefore, even when the electrode recesses 2A and 2B are formed by dry etching, the formation surfaces (surfaces to be etched) of the electrode recesses 2A and 2B are uniformly formed over the entire surface of the substrate.

Subsequently, as shown in FIG. 3A, a source electrode 5 and a drain electrode 6 which are a pair of ohmic electrodes are formed.
First, a resist mask for forming a source electrode and a drain electrode is formed. A resist is applied on the compound semiconductor multilayer structure 2 to form openings for exposing the electrode recesses 2A and 2B of the electron supply layer 2d. Thus, a resist mask having the opening is formed.

  Using this resist mask, for example, Ta / Al is deposited as an electrode material on the resist mask including the inside of the opening, for example, by vapor deposition. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thereafter, the SiC substrate 1 is heat-treated in a nitrogen atmosphere, for example, at a temperature of about 400 ° C. to 1000 ° C., for example, about 550 ° C., and the remaining Ta / Al is brought into ohmic contact with the electron supply layer 2d. If an ohmic contact with the Ta / Al electron supply layer 2d is obtained, heat treatment may be unnecessary. As a result, the source electrode 5 and the drain electrode 6 that fill the electrode recesses 2A and 2B of the electron supply layer 2d are formed.

  The electrode recesses 2A and 2B in which the source electrode 5 and the drain electrode 6 are formed have a uniform formation surface (surface to be etched) over the entire surface of the substrate. Therefore, the source electrode 5 and the drain electrode 6 can be formed uniformly, and a low-resistance ohmic electrode is realized.

Subsequently, as shown in FIG. 3B, a gate electrode 7 is formed.
Specifically, first, a resist mask for forming the gate electrode is formed. A resist is applied on the compound semiconductor multilayer structure 2 to form an opening that exposes the surface of the p-type semiconductor layer 3a. Thus, a resist mask having the opening is formed.

  Using this resist mask, for example, Ni / Au is deposited as an electrode material on the resist mask including the inside of the opening exposing the surface of the p-type semiconductor layer 3a by, for example, vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 7 is formed on the p-type semiconductor layer 3a.

Subsequently, as shown in FIG. 3C, a protective insulating film 8 is formed.
Specifically, an insulator is deposited so as to cover the entire surface of SiC substrate 1. As the insulator, for example, SiN is deposited by PECVD. Thus, the protective insulating film 8 is formed.

  Thereafter, the AlGaN / GaN.HEMT according to the present embodiment is formed through various processes such as formation of wirings connected to the source electrode 5, the drain electrode 6, and the gate electrode 7.

  In the present embodiment, since the p-type semiconductor layer 3a that lifts the energy band is disposed immediately below the gate electrode 7, normally-off is achieved. In order to leave the p-type semiconductor layer 3 in the region of the gate electrode 7, dry etching is not used when removing portions other than the region of the p-type semiconductor layer 3. It becomes a transistor of resistance. In the region where the p-type semiconductor layer 3 is removed by the electron supply layer 2d, the surface has flatness at the atomic step level, so that interface states due to surface roughness caused by dry etching are not formed, and stable operation is possible. Become. Since the high Al composition AlGaN layer 4 is formed on the surface layer of the electron supply layer 2d other than the region of the gate electrode 7 and thermal desorption of p-GaN is stopped, there is no non-uniformity in the remaining amount of p-GaN. It becomes. In addition, since there is no concern about overetching of the surface of the electron supply layer 2d, on-resistance non-uniformity does not occur.

  Since the high Al composition AlGaN layer 4 is formed on the surface layer of the electron supply layer 2d other than the region of the gate electrode 7, the concentration of 2DEG is increased, and the transistor has a lower resistance. On the other hand, since the high Al composition AlGaN layer 4 does not exist in the region of the gate electrode 7, the concentration of 2DEG is not increased more than necessary, and normally-off is not inhibited. As a result, a low-resistance highly reliable normally-off AlGaN / GaN HEMT is realized.

  In addition, even if a film thickness distribution is formed in the p-type semiconductor layer 3 due to the epitaxial crystal growth of the p-type semiconductor layer 3 in the substrate surface, in the heat treatment process of the p-type semiconductor layer 3, the electron supply layer 2d The high Al composition AlGaN layer 4 in the surface layer functions as a thermal desorption stopper. Therefore, only the p-type semiconductor layer 3 is removed, the non-uniformity of the remaining amount of p-GaN due to the film thickness distribution of the p-type semiconductor layer 3 does not occur, and the on-resistance in the substrate plane does not vary. .

  As described above, according to the present embodiment, although the p-type semiconductor layer 3a is locally formed in the region under the gate electrode 7 on the electron supply layer 2d, the p-type semiconductor layer 3a of the electron supply layer 2d Non-formed surfaces achieve atomic step level flatness. As a result, a highly reliable AlGaN / GaN, which realizes reliable normally-off without causing problems such as an increase in electrical resistance and operational instability caused by dry etching of the p-type semiconductor layer. HEMT is realized.

The AlGaN / GaN HEMT according to the present embodiment is applied to a so-called discrete package.
In this discrete package, the AlGaN / GaN HEMT chip according to the present embodiment is mounted. Hereinafter, the discrete package of the AlGaN / GaN.HEMT chip (hereinafter referred to as a HEMT chip) according to the present embodiment will be exemplified.

FIG. 4 shows a schematic configuration of the HEMT chip.
In the HEMT chip 100, the AlGaN / GaN.HEMT transistor region 101, the drain pad 102 connected to the drain electrode, the gate pad 103 connected to the gate electrode, and the source electrode are connected to the surface. A source pad 104 is provided.

FIG. 5 is a schematic plan view showing the discrete package.
In order to manufacture a discrete package, first, the HEMT chip 100 is fixed to the lead frame 112 using a die attach agent 111 such as solder. A drain lead 112 a is integrally formed on the lead frame 112, and the gate lead 112 b and the source lead 112 c are arranged separately from the lead frame 112.

Subsequently, the drain pad 102 and the drain lead 112a, the gate pad 103 and the gate lead 112b, and the source pad 104 and the source lead 112c are electrically connected by bonding using the Al wire 113, respectively.
Thereafter, the HEMT chip 100 is resin-sealed by a transfer molding method using the mold resin 114, and the lead frame 112 is separated. Thus, a discrete package is formed.

(Second Embodiment)
In the present embodiment, a PFC (Power Factor Correction) circuit including the AlGaN / GaN HEMT according to the first embodiment is disclosed.
FIG. 6 is a connection diagram showing the PFC circuit.

  The PFC circuit 20 includes a switching element (transistor) 21, a diode 22, a choke coil 23, capacitors 24 and 25, a diode bridge 26, and an AC power supply (AC) 27. The AlGaN / GaN HEMT according to the first embodiment is applied to the switch element 21.

  In the PFC circuit 20, the drain electrode of the switch element 21 is connected to the anode terminal of the diode 22 and one terminal of the choke coil 23. The source electrode of the switch element 21 is connected to one terminal of the capacitor 24 and one terminal of the capacitor 25. The other terminal of the capacitor 24 and the other terminal of the choke coil 23 are connected. The other terminal of the capacitor 25 and the cathode terminal of the diode 22 are connected. An AC 27 is connected between both terminals of the capacitor 24 via a diode bridge 26. A direct current power supply (DC) is connected between both terminals of the capacitor 25. A PFC controller (not shown) is connected to the switch element 21.

  In the present embodiment, the AlGaN / GaN HEMT according to the first embodiment is applied to the PFC circuit 20. Thereby, a highly reliable PFC circuit 30 is realized.

(Third embodiment)
In the present embodiment, a power supply device including the AlGaN / GaN.HEMT according to the first embodiment is disclosed.
FIG. 7 is a connection diagram illustrating a schematic configuration of the power supply device according to the third embodiment.

The power supply device according to this embodiment includes a high-voltage primary circuit 31 and a low-voltage secondary circuit 32, and a transformer 33 disposed between the primary circuit 31 and the secondary circuit 32. The
The primary circuit 31 includes the PFC circuit 20 according to the second embodiment and an inverter circuit connected between both terminals of the capacitor 25 of the PFC circuit 20, for example, a full bridge inverter circuit 30. The full bridge inverter circuit 30 includes a plurality (four in this case) of switch elements 34a, 34b, 34c, and 34d.
The secondary circuit 32 includes a plurality (three in this case) of switch elements 35a, 35b, and 35c.

  In the present embodiment, the PFC circuit constituting the primary circuit 31 is the PFC circuit 20 according to the second embodiment, and the switch elements 34a, 34b, 34c, and 34d of the full bridge inverter circuit 30 are the first embodiment. AlGaN / GaN.HEMT. On the other hand, the switch elements 35a, 35b, and 35c of the secondary circuit 32 are normal MIS • FETs using silicon.

  In the present embodiment, the PFC circuit 20 according to the second embodiment and the AlGaN / GaN HEMT according to the first embodiment are applied to the primary circuit 31 that is a high-voltage circuit. As a result, a highly reliable high-power power supply device is realized.

(Fourth embodiment)
In the present embodiment, a high-frequency amplifier including the AlGaN / GaN HEMT according to the first embodiment is disclosed.
FIG. 8 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the fourth embodiment.

The high-frequency amplifier according to the present embodiment includes a digital predistortion circuit 41, mixers 42a and 42b, and a power amplifier 43.
The digital predistortion circuit 41 compensates for nonlinear distortion of the input signal. The mixer 42a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 43 amplifies the input signal mixed with the AC signal, and includes the AlGaN / GaN HEMT according to the first embodiment. In FIG. 8, for example, by switching the switch, the output side signal is mixed with the AC signal by the mixer 42b and sent to the digital predistortion circuit 41.

  In this embodiment, the AlGaN / GaN HEMT according to the first embodiment is applied to a high frequency amplifier. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

(Other embodiments)
In the first embodiment, AlGaN / GaN.HEMT is exemplified as the compound semiconductor device. As a compound semiconductor device, besides the AlGaN / GaN.HEMT, the following HEMT can be applied.

・ Other device example 1
In this example, InAlN / GaN.HEMT is disclosed as a compound semiconductor device.
InAlN and GaN are compound semiconductors that can have a lattice constant close to the composition. In this case, in the first embodiment described above, the electron transit layer is formed of i-GaN, the intermediate layer is formed of AlN, the electron supply layer is formed of n-InAlN, and the p-type semiconductor layer is formed of p-GaN. In this case, the piezoelectric polarization hardly occurs, so that the two-dimensional electron gas is mainly generated by the spontaneous polarization of InAlN.

  According to this example, similarly to the AlGaN / GaN HEMT described above, the p-type semiconductor layer is used to control 2DEG, but the increase in electrical resistance and operational instability caused by dry etching of the p-type semiconductor layer are achieved. A highly reliable InAlN / GaN.HEMT that realizes reliable normally-off without causing various problems such as the above is realized.

・ Other device example 2
In this example, InAlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
GaN and InAlGaN are compound semiconductors in which the latter can make the lattice constant smaller by the composition than the former. In this case, in the first embodiment described above, the electron transit layer is formed of i-GaN, the intermediate layer is formed of i-InAlGaN, the electron supply layer is formed of n-InAlGaN, and the p-type semiconductor layer is formed of p-GaN.

  According to this example, similarly to the AlGaN / GaN HEMT described above, the p-type semiconductor layer is used to control 2DEG, but the increase in electrical resistance and operational instability caused by dry etching of the p-type semiconductor layer are achieved. Thus, a highly reliable InAlGaN / GaN HEMT that realizes reliable normally-off without causing various problems such as these is realized.

  Hereinafter, various aspects of the compound semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as appendices.

(Additional remark 1) Compound semiconductor laminated structure,
An electrode formed above the compound semiconductor multilayer structure;
A p-type semiconductor layer locally formed between the compound semiconductor multilayer structure and the electrode,
In the compound semiconductor multilayer structure, a non-formation surface of the p-type semiconductor layer has flatness at an atomic step level on the surface thereof.

  (Appendix 2) The compound semiconductor multilayer structure is characterized in that a surface layer having a higher Al composition ratio than other parts is formed on a non-formation surface of the p-type semiconductor layer having flatness at an atomic step level. The compound semiconductor device according to appendix 1.

  (Supplementary note 3) The compound semiconductor device according to supplementary note 2, wherein the surface layer has a thickness in a range of 1 nm to 2 nm.

(Appendix 4) Above the compound semiconductor multilayer structure, further includes a pair of ohmic electrodes formed on both sides of the electrode,
The compound semiconductor device according to appendix 2 or 3, wherein the surface layer is not formed between the compound semiconductor multilayer structure and the ohmic electrode.

(Additional remark 5) The process of forming a compound semiconductor laminated structure,
Forming a p-type semiconductor layer above the compound semiconductor multilayer structure;
Heat-treating the p-type semiconductor layer to leave a part of the p-type semiconductor layer;
Forming an electrode above the remaining p-type semiconductor layer,
In the compound semiconductor multilayer structure, the non-formation surface of the p-type semiconductor layer has an atomic step level flatness on the surface by the heat treatment.

  (Appendix 6) In the compound semiconductor multilayer structure, a surface layer having a higher Al composition ratio than other portions is formed on the non-formation surface of the p-type semiconductor layer, which is a flat surface at an atomic step level, by the heat treatment. Item 6. The method for manufacturing a compound semiconductor device according to appendix 5.

  (Supplementary note 7) The method for manufacturing a compound semiconductor device according to supplementary note 6, wherein the surface layer has a thickness in a range of 1 nm to 2 nm.

(Appendix 8) The method further includes the step of forming a pair of ohmic electrodes on both sides of the electrode above the compound semiconductor multilayer structure,
8. The method of manufacturing a compound semiconductor device according to appendix 6 or 7, wherein the surface layer is not formed between the compound semiconductor multilayer structure and the ohmic electrode.

  (Additional remark 9) The temperature of the said heat processing shall be a value within the range of 900 degreeC-1100 degreeC, The manufacturing method of the compound semiconductor device of any one of Additional remarks 5-8 characterized by the above-mentioned.

(Supplementary note 10) A power supply device comprising a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
Compound semiconductor multilayer structure,
An electrode formed above the compound semiconductor multilayer structure;
A p-type semiconductor layer locally formed between the compound semiconductor multilayer structure and the electrode,
In the compound semiconductor multilayer structure, a non-formation surface of the p-type semiconductor layer has an atomic step level flatness on a surface thereof.

(Appendix 11) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
Compound semiconductor multilayer structure,
An electrode formed above the compound semiconductor multilayer structure;
A p-type semiconductor layer locally formed between the compound semiconductor multilayer structure and the electrode,
The high-frequency amplifier characterized in that the non-formation surface of the p-type semiconductor layer has an atomic step level flatness on the surface of the compound semiconductor multilayer structure.

DESCRIPTION OF SYMBOLS 1 SiC substrate 2,11 Compound semiconductor laminated structure 2a Buffer layer 2b Electron travel layer 2c Intermediate layer 2d Electron supply layer 2A, 2B Electrode recess 3 P-type semiconductor layer 4 High Al composition AlGaN layer 5 Source electrode 6 Drain electrode 7 Gate electrode 8 Protective insulating film 10 Mask 20 PFC circuit 21, 34a, 34b, 34c, 34d, 35a, 35b, 35c Switch element 22 Diode 23 Choke coil 24, 25 Capacitor 26 Diode bridge 30 Full bridge inverter circuit 31 Primary side circuit 32 Secondary Side circuit 33 Transformer 41 Digital predistortion circuit 42a, 42b Mixer 43 Power amplifier 100 HEMT chip 101 Transistor region 102 Drain pad 103 Gate pad 104 Source pad 111 Die attach agent 112 Lead frame 112a Drain lead 112b Gate lead 112c Source lead 113 Al wire 114 Mold resin

Claims (9)

Compound semiconductor multilayer structure,
An electrode formed above the compound semiconductor multilayer structure;
A p-type semiconductor layer locally formed between the compound semiconductor multilayer structure and the electrode,
In the compound semiconductor multilayer structure, a non-formation surface of the p-type semiconductor layer has flatness at an atomic step level on the surface thereof.   2. The compound semiconductor multilayer structure according to claim 1, wherein a surface layer having a higher Al composition ratio than other portions is formed on a non-formation surface of the p-type semiconductor layer having flatness at an atomic step level. The compound semiconductor device described in 1.   The compound semiconductor device according to claim 2, wherein the surface layer has a thickness in a range of 1 nm to 2 nm. Above the compound semiconductor multilayer structure, further comprising a pair of ohmic electrodes formed on both sides of the electrode,
4. The compound semiconductor device according to claim 2, wherein the surface layer is not formed between the compound semiconductor multilayer structure and the ohmic electrode. 5. Forming a compound semiconductor multilayer structure;
Forming a p-type semiconductor layer above the compound semiconductor multilayer structure;
Heat-treating the p-type semiconductor layer to leave a part of the p-type semiconductor layer;
Forming an electrode above the remaining p-type semiconductor layer,
In the compound semiconductor multilayer structure, the non-formation surface of the p-type semiconductor layer has an atomic step level flatness on the surface by the heat treatment.   The compound semiconductor multilayer structure is characterized in that a surface layer having a higher Al composition ratio than other portions is formed on the non-formation surface of the p-type semiconductor layer, which is a flat surface at an atomic step level, by the heat treatment. A method for manufacturing a compound semiconductor device according to claim 5.   The method of manufacturing a compound semiconductor device according to claim 6, wherein the surface layer has a thickness in a range of 1 nm to 2 nm. The method further includes forming a pair of ohmic electrodes on both sides of the electrode above the compound semiconductor multilayer structure,
The method for manufacturing a compound semiconductor device according to claim 6, wherein the surface layer is not formed between the compound semiconductor multilayer structure and the ohmic electrode.   9. The method of manufacturing a compound semiconductor device according to claim 5, wherein the temperature of the heat treatment is set to a value within a range of 900 ° C. to 1100 ° C. 10.

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