CN111415987B - Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof - Google Patents

Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof Download PDF

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CN111415987B
CN111415987B CN202010275014.XA CN202010275014A CN111415987B CN 111415987 B CN111415987 B CN 111415987B CN 202010275014 A CN202010275014 A CN 202010275014A CN 111415987 B CN111415987 B CN 111415987B
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gallium nitride
etching
electrode structure
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CN111415987A (en
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莫炯炯
王志宇
陈华
刘家瑞
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Zhejiang University ZJU
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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    • H01L29/45—Ohmic electrodes
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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Abstract

The invention provides a gallium nitride device structure combining secondary epitaxy and self-alignment process and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate, forming an epitaxial structure comprising a gallium nitride layer, protecting through a mask layer, epitaxially growing a source electrode structure and a drain electrode structure, forming a grid side wall and forming a grid structure. According to the invention, the source electrode structure and the drain electrode structure are formed through secondary epitaxial growth, so that ohmic contact resistance can be effectively reduced, and before secondary epitaxial growth, the etching rate and material damage caused by etching are balanced through multi-step ion etching, oxidation and acid solvent digital etching, so that the material quality is ensured, and meanwhile, the process cost is considered. By utilizing the self-alignment technology, the error caused by the alignment process in the photoetching process is avoided, and the size of the grid electrode is accurately defined. The size of the grid electrode is controlled by the thickness of the isolation side wall, the step of grid foot photoetching is omitted, and the process is simplified. The invention can realize the heteroepitaxy of the GaN material on the large-size wafer, and saves the epitaxy cost of unit size.

Description

Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a gallium nitride device structure combining secondary epitaxy and a self-alignment process and a preparation method thereof.
Background
At present, the ohmic contact resistance obtained in the preparation of some semiconductor device structures is not ideal enough, for example, the ohmic contact resistance obtained in the existing GaNHEMT (high electron mobility transistor) devices is not ideal enough. In addition, in the device preparation process, the ion implantation technology needs subsequent high-temperature annealing treatment to activate implanted ions, meanwhile, material lattice damage caused by ion implantation is recovered, the material is damaged, and the ion activation rate is not high enough, so that the ohmic contact resistance always restricts the development of the GaN device to a higher frequency direction. Meanwhile, the preparation of the GaN device grid is usually realized through photoetching and alignment processes, the grid size, the grid source and the grid drain distance are strictly controlled to improve the frequency characteristic of the device, and the alignment requirement becomes more rigorous along with the small size of the device, so that the generated error becomes fatal, and the photoetching alignment error also restricts the development of the GaN device to a higher frequency direction.
Therefore, it is necessary to provide a semiconductor device structure and a method for manufacturing the same to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a gallium nitride device structure combining a double epitaxy and a self-alignment process and a method for fabricating the same, which are used to solve the problems of the prior art, such as insufficient ohmic contact resistance and strict requirement on lithographic dimension.
In order to achieve the above and other related objects, the present invention provides a method for fabricating a gan device structure by a double epitaxy and self-alignment process, the method comprising the steps of:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a gallium nitride layer;
forming an etching mask layer on the epitaxial structure, wherein the etching mask layer is provided with a covering part at least covering a grid electrode area of a grid electrode structure to be formed, and a first opening and a second opening which expose the epitaxial structure;
epitaxially growing a source electrode structure and a drain electrode structure at positions corresponding to the first opening and the second opening based on the etching mask layer, wherein the source electrode structure and the drain electrode structure are both grown on the surface of the gallium nitride layer;
forming a grid side wall between the source electrode structure and the drain electrode structure, wherein the grid side wall defines a grid region;
and forming a gate structure on the epitaxial structure corresponding to the gate region to prepare the gallium nitride device.
Optionally, the step of forming the epitaxial structure on the semiconductor substrate includes: and epitaxially forming a buffer layer on the semiconductor substrate, epitaxially forming the gallium nitride layer on the buffer layer, and epitaxially forming a barrier layer on the gallium nitride layer.
Optionally, the step of epitaxially growing the source structure and the drain structure on the epitaxial structure includes:
etching the epitaxial structure based on the etching mask layer, respectively forming a source opening and a drain opening corresponding to the first opening and the second opening, and exposing the gallium nitride layer from the source opening and the drain opening;
and epitaxially growing the doped source electrode structure on the surface of the gallium nitride layer corresponding to the source electrode opening, and epitaxially growing the doped drain electrode structure on the surface of the gallium nitride layer corresponding to the drain electrode opening.
Optionally, etching the epitaxial structure based on the etching mask layer includes sequentially performing a first etching step and a second etching step on the epitaxial structure, where the first etching step includes a step of multi-step ion etching, and the second etching step includes a step of oxidizing and combining an acid solvent for etching.
Optionally, in the process of performing the multi-step ion etching, the etching power of each step of ion etching is gradually reduced; and in the technological process of etching by the acid pickling solvent, stopping the etching process by the acid pickling solvent on the two-dimensional electron gas surface of the gallium nitride layer.
Optionally, the step of growing the source structure and the drain structure on the surface of the gallium nitride layer includes:
placing the structure obtained after the epitaxial structure is etched in a reaction chamber of epitaxial equipment;
raising the temperature in the reaction chamber to 1200-1250 ℃, and introducing impurity-removing gas;
and controlling the temperature in the reaction chamber to be 1150-1170 ℃, and introducing a gas source to grow the doped source electrode structure and the doped drain electrode structure, wherein the source electrode structure and the drain electrode structure both comprise doped gallium nitride layers.
Optionally, after the source electrode structure and the drain electrode structure are grown, the covering part is removed by sequentially adopting wet etching and dry etching processes.
Optionally, the step of forming the gate sidewall spacer includes: and forming continuous side wall material layers on the structures for forming the source electrode structure and the drain electrode structure, removing the side wall material layers above the source electrode structure, the drain electrode structure and part of the epitaxial structure by adopting an anisotropic etching process, and reserving the side wall material layers at the side parts of the source electrode structure and the drain electrode structure so as to form the grid side wall and limit the grid region through the grid side wall.
Optionally, the method for manufacturing the semiconductor device structure further includes a step of manufacturing a source electrode and a drain electrode, wherein the source electrode is formed on a portion of the surface of the source structure, and the drain electrode is formed on a portion of the surface of the drain structure.
Optionally, the method for manufacturing the semiconductor device structure further includes: and forming a dielectric passivation layer on the surfaces of the source electrode structure, the drain electrode structure and the epitaxial structure around the source electrode structure and the drain electrode structure.
Optionally, the dielectric passivation layer is formed by an atomic layer deposition process, the material of the dielectric passivation layer includes a high-dielectric-constant dielectric layer, and the thickness of the dielectric passivation layer is between 10nm and 50 nm.
The invention also provides a gallium nitride device structure combining a secondary epitaxy and a self-alignment process, wherein the semiconductor device structure is preferably prepared by adopting the preparation method of the semiconductor device structure of the invention, and of course, other modes can be adopted, and the gallium nitride device structure combining the secondary epitaxy and the self-alignment process comprises the following steps:
a semiconductor substrate;
an epitaxial structure formed on the semiconductor substrate, the epitaxial structure including a gallium nitride layer;
the source electrode structure and the drain electrode structure are epitaxially grown on the surface of the gallium nitride layer;
the grid side wall is formed between the source electrode structure and the drain electrode structure and limits a grid region;
and the grid structure is formed on the epitaxial structure corresponding to the grid region so as to form a gallium nitride device.
Optionally, the epitaxial structure sequentially includes, from bottom to top: the buffer layer, the gallium nitride layer and the barrier layer, wherein the source electrode structure and the drain electrode structure penetrate through the barrier layer to be formed on the surface of the gallium nitride layer.
Optionally, the buffer layer comprises an AlxGa1-xN layer, the barrier layer comprises an AlyGa1-yN layer, the thickness of the barrier layer is between 20-100nm, the thickness of the gallium nitride layer is between 0.5um-2um, wherein 0< x <1, 0< y < 1.
Optionally, the source structure comprises a doped gallium nitride layer, and the drain structure comprises a doped gallium nitride layer; the semiconductor device structure further comprises a drain electrode and a source electrode, wherein the source electrode is formed on the surface of the source structure, and the drain electrode is formed on the surface of the drain structure.
Optionally, a dielectric passivation layer is further formed between the gate sidewall and the epitaxial structure, the gate structure is formed on the dielectric passivation layer, and the dielectric passivation layer further extends to the side portions and the upper surfaces of the source structure and the drain structure.
Optionally, the material of the dielectric passivation layer comprises a high dielectric constant dielectric layer, and the thickness of the dielectric passivation layer is between 10nm and 50 nm.
As described above, according to the gallium nitride device structure and the method for manufacturing the same combining the secondary epitaxy and the self-alignment process, the ohmic contact resistance can be effectively reduced by the method for forming the source electrode structure and the drain electrode structure through the secondary epitaxy growth, and meanwhile, before the secondary epitaxy, the etching rate and the material damage caused by etching are balanced through the steps of multi-step ion etching, oxidation and acid solvent digital etching, and the process cost is considered while the material quality is ensured. In addition, by utilizing the self-alignment technology, the error caused by the alignment process in the photoetching process is avoided, and the size of the grid electrode is accurately defined. Meanwhile, the size of the grid is controlled by the thickness of the isolation side wall, so that a step of etching a grid foot is omitted, and the process is simplified. The scheme of the invention can realize the heteroepitaxy of the GaN material on the large-size wafer, and save the epitaxy cost of unit size.
Drawings
FIG. 1 shows a process flow diagram for fabricating a gallium nitride device structure according to the present invention.
Fig. 2 is a schematic structural diagram of a semiconductor substrate provided in the fabrication of a gallium nitride device structure according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram illustrating the formation of an epitaxial structure during fabrication of a gan device structure according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram illustrating an example of an epitaxial structure formed in the fabrication of a gan device structure according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram illustrating the formation of an etching mask layer in the fabrication of a gallium nitride device structure according to an embodiment of the present invention.
Fig. 6 is a schematic view illustrating an epitaxial structure etched during fabrication of a gan device structure according to an embodiment of the present invention.
FIG. 7 is a schematic view of the formation of a source opening and a drain opening in the fabrication of a GaN device structure according to an embodiment of the invention.
FIG. 8 is a schematic diagram illustrating the formation of a source structure and a drain structure during fabrication of a GaN device structure according to an embodiment of the invention.
Fig. 9 is a schematic view of the structure of the gan device structure according to the present invention.
Fig. 10 is a schematic structural diagram illustrating a passivation dielectric material layer and a sidewall material layer formed in the gallium nitride device structure preparation according to an embodiment of the invention.
Fig. 11 is a schematic structural diagram illustrating the formation of gate sidewalls in the fabrication of a gan device structure according to an embodiment of the present invention.
Fig. 12 is a schematic structural diagram illustrating the formation of a gate structure, a source electrode and a drain electrode in the fabrication of a gan device structure according to an embodiment of the present invention.
Description of the element reference numerals
101 semiconductor substrate
102 epitaxial structure
103 buffer layer
104 gallium nitride layer
105 barrier layer
106 etch mask layer
106a covering part
106b first opening
106c second opening
107 source opening
108 drain opening
109 source structure
110 drain structure
111 dielectric passivation layer
112 side wall material layer
113 grid side wall
114 dielectric passivation layer
115 source electrode
116 drain electrode
117 gate structure
S1-S6
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for preparing a gallium nitride device structure by combining a secondary epitaxy and a self-alignment process, wherein the method comprises the following steps:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a gallium nitride layer;
forming an etching mask layer on the epitaxial structure, wherein the etching mask layer is provided with a covering part at least covering a grid electrode area of a grid electrode structure to be formed, and a first opening and a second opening which expose the epitaxial structure;
epitaxially growing a source electrode structure and a drain electrode structure at positions corresponding to the first opening and the second opening based on the etching mask layer, wherein the source electrode structure and the drain electrode structure are both grown on the surface of the gallium nitride layer;
forming a grid side wall between the source electrode structure and the drain electrode structure, wherein the grid side wall defines a grid region;
and forming a gate structure on the epitaxial structure corresponding to the gate region to prepare the gallium nitride device.
The method for manufacturing the semiconductor device structure of the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the manufacturing sequence of the semiconductor device structure of the present invention, and the skilled person can change the sequence according to the actual process steps, and fig. 1 shows only the manufacturing steps of the semiconductor device structure in one example.
As shown in S1 in fig. 1 and fig. 2, the semiconductor substrate 101 is provided. The semiconductor substrate 101 may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, a GOI (Germanium-on-Insulator) substrate, an SiC substrate, a sapphire substrate, and the like, in other embodiments, the semiconductor substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, silicon carbide, and the like, the semiconductor substrate 101 may also be a stacked structure, such as a silicon/Germanium-silicon stacked structure, and the like, in this embodiment, the semiconductor substrate 101 is a Si (111) substrate, and silicon is used as the substrate, so that heteroepitaxy of a GaN material can be realized on a large-sized wafer, and the epitaxy cost per unit size is saved.
As shown in S2 in fig. 1 and fig. 3-4, an epitaxial structure 102 is formed on the semiconductor substrate 101, wherein the epitaxial structure 102 includes a gallium nitride layer to fabricate a gallium nitride device. In this embodiment, referring to fig. 4, the step of forming the epitaxial structure 102 on the semiconductor substrate 101 includes: a buffer layer 103 is epitaxially formed on the semiconductor substrate 101, the gallium nitride layer 104 is epitaxially formed on the buffer layer 103, and a barrier layer 105 is epitaxially formed on the gallium nitride layer 104.
Specifically, in an example, the buffer layer 103 includes an AlxGa1-xN layer, where 0< x <1, for example, may be selected to be 0.1, 0.15, 0.2, etc., and a thickness of the buffer layer 103 is selected to be 2-5 μm, for example, 3 μm, 4 μm, and the buffer layer 103 is configured to release stress caused by lattice mismatch. The barrier layer 105 comprises an AlyGa1-yN layer, where 0< y <1, e.g., may be selected to be 0.1, 0.15, 0.2, 0.3, etc.; the thickness of the barrier layer 105 is between 15nm and 100nm, and may be, for example, 20nm, 30nm, 50nm, 80nm, or the like. The gallium nitride layer 104 is a channel layer having a thickness of 0.5 μm to 2 μm, and may be, for example, 0.8 μm, 1 μm, or 1.2 μm. In this embodiment, the thickness of the gallium nitride layer 104 is selected to be 1 μm, and the barrier layer 105 is selected to be an al0.3ga0.7n layer. The barrier layer 105 is formed on the gallium nitride layer 104 to control a two-dimensional electron gas surface based on where the barrier layer 105 is formed in the gallium nitride layer 104, for example, based on the elemental composition of the barrier layer 105 and the thickness of the barrier layer 105.
In another example, a nucleation layer, which may be, for example, an AlN layer, is formed on the semiconductor substrate 101 before the epitaxial structure 102, that is, the buffer layer 103, is formed, and then, in one example, an AlGaN/GaN/AlGaN thin film is heteroepitaxial in sequence. The thickness of the nucleation layer may be selected to be between 100nm and 400nm, and may be, for example, 150nm, 200nm, 300nm, etc.
As shown in S3 of fig. 1 and fig. 5, an etching mask layer 106 is formed on the epitaxial structure 102, where the etching mask layer 106 has a covering portion 106a at least covering a gate region where a gate structure is to be formed, and a first opening 106b and a second opening 106c exposing the epitaxial structure 102, and positions of the first opening 106b and the second opening 106c correspond to positions where a source structure and a drain structure are to be formed subsequently. In this step, the etching mask layer 106 is formed, on one hand, the subsequent source structure and drain structure may be prepared based on the etching mask layer 106, and on the other hand, the etching mask layer 106 has the covering portion 106a, and the covering portion 106a may cover a region on the epitaxial structure 102 where the gate structure is subsequently formed, for example, a region on the barrier layer 105 corresponding to the gate structure, so as to protect the portion of the material layer from being damaged in the process of forming the source structure and the drain structure, and of course, the covering portion 106a may further cover other regions except the gate region, which is set according to actual requirements. In an example, the material of the etching mask layer 106 includes, but is not limited to, SiO2 or SiN, and in an example, the etching mask material layer may be formed by a chemical vapor deposition process, and then the first opening 106b, the second opening 106c, and the covering portion 106a are formed by a photolithography process.
As shown in S4 of fig. 1 and fig. 6-8, a source structure 109 and a drain structure 110 are epitaxially grown at positions corresponding to the first opening 106b and the second opening 106c based on the etching mask layer 106, that is, the double epitaxy according to the present invention is to epitaxially grow the source structure 109 and the drain structure 110, wherein the source structure 109 and the drain structure 110 are both grown on the surface of the gallium nitride layer 104. In this step, the source structure 109 and the drain structure 110 are epitaxially grown on the gallium nitride layer 104 by an epitaxial growth method, that is, the source structure and the drain structure are formed by a secondary epitaxial method, so that ohmic contact resistance can be effectively reduced, and the problem that the ohmic contact resistance of the existing device structure is not ideal can be solved.
In the present embodiment, as shown in fig. 6-8, the step of epitaxially growing the source structure 109 and the drain structure 110 on the epitaxial structure 102 includes:
first, as shown in fig. 6 to 7, the epitaxial structure 102 is etched based on the etching mask layer 106, a source opening 107 and a drain opening 108 are respectively formed corresponding to the first opening 106b and the second opening 106c, and the gallium nitride layer 104 is exposed from the source opening 107 and the drain opening 108.
In an example, etching the epitaxial structure 102 based on the etching mask layer 106 includes sequentially performing a first etching and a second etching on the epitaxial structure 102, where the first etching includes a step of multi-step ion etching, and the second etching includes a step of oxidizing and etching with an acid solvent. That is, etching the epitaxial structure 102 based on the etching mask layer 106 includes sequentially performing a plurality of steps of ion etching, oxidation, and acid solvent digital etching on the epitaxial structure 102, so as to form the source opening 107 corresponding to the first opening 106b and the drain opening 108 corresponding to the second opening 106 c. In an example, the epitaxial structure sequentially comprises the buffer layer 103, the gallium nitride layer 104 and the barrier layer 105 from bottom to top, wherein the barrier layer 105 is etched by a multi-step ion etching process, such as performing multi-step inductively coupled ion beam etching, in an example, during the multi-step ion etching process, the etching power of each step of ion etching is gradually reduced, wherein the higher the power is, the faster the etching rate is, the larger the damage to the material is, the more charges are accumulated on the etching surface, rapid etching can be performed in an initial stage, as the gallium nitride layer is closer to the etching termination surface, the etching rate is reduced, and the etching damage is reduced, in an example, multi-step ICP plasma etching is performed, and the Cl2/Ar/BCl3 is used as an etching gas source, the power is gradually reduced, and the power is sequentially 50W, 25W, 5W and 1W, and the etching time can be selected according to actual thickness and the like. In addition, the etching mask layer 106 of the present invention has the covering portion 106a covering the gate region of the epitaxial structure where the gate structure is to be formed, so that the gate region can be protected from the damage of plasma etching during the etching in this step.
Further, after the multi-step ion etching, the steps of oxidation and acid solvent etching are performed, in the above example, the epitaxial structure sequentially includes the buffer layer 103, the gallium nitride layer 104, and the barrier layer 105 from bottom to top, after the barrier layer 105 is etched, the surface of the gallium nitride layer 104 is oxidized, for example, GaN surface oxidation is performed by using oxygen plasma, and etching is performed by using an acid solvent, for example, etching and cleaning are performed by using an acid reagent (HF, HCl), the above oxidation and chemical reagent etching method is called a digital etching method, and the etching rate is slow, about 0,1nm to 1 nm/time, so that the etching thickness can be accurately controlled. Multiple oxidation and chemical reagent etching steps can be carried out to reach the required etching thickness. In one example, during the etching process, the etching process is stopped on the two-dimensional electron gas surface of the gallium nitride layer 104, so as to form the source opening 107 and the drain opening 108 exposing the gallium nitride layer 104. The two-dimensional electron gas surface may be selected based on the composition, thickness, and the like of the barrier layer 105 on the gallium nitride layer 104. By the method, before secondary epitaxy, the etching rate and material damage caused by etching are balanced by the ICP etching technology under different power in multiple steps and combining with the oxidation of the interface oxygen plasma and acid cleaning, and the process cost is considered while the material quality is ensured.
Next, as shown in fig. 8, a doped source structure 109 is epitaxially grown on the surface of the gallium nitride layer 104 corresponding to the source opening 107, and a doped drain structure 110 is epitaxially grown on the surface of the gallium nitride layer 104 corresponding to the drain opening 108.
As an example, the step of growing the source structure 109 and the drain structure 110 on the surface of the gallium nitride layer includes:
firstly, placing a structure obtained by etching the epitaxial structure in the previous step into a reaction chamber of epitaxial equipment, for example, placing the sample into MOCVD equipment;
then, raising the temperature in the reaction chamber to 1200-1250 ℃, and introducing impurity-removing gas, for example, the temperature can be raised to 1200 ℃, 1220 ℃ or 1230 ℃, and the introduced impurity-removing gas can be hydrogen to remove impurities on the substrate;
finally, controlling the temperature in the reaction chamber between 1150 ℃ and 1170 ℃, for example, 1160 ℃ or 1180 ℃, and introducing a gas source to grow the doped source structure and the doped drain structure, wherein the source structure and the drain structure both comprise a doped gallium nitride layer, for example, the gas source can be NH3, SiH4, TMGa or TEGa as a gas source, and epitaxially dope the n-type highly doped GaN film doped with Si, in one example, the doping concentration is 10 ℃18～5×1019/cm3. In one example, the material of the source structure 109 and the drain structure 110 is doped gallium nitride, which is consistent with the main material of the gallium nitride layer as a channel layer.
By adopting the method of the present example, the doped source electrode structure and the doped drain electrode structure are grown on the gallium nitride layer 104 by the secondary epitaxy, and in a pair of proportions, the source electrode structure and the drain electrode structure are prepared by the traditional process, wherein the ion implantation is followed by the subsequent high temperature annealing to activate the implanted ions and recover the material lattice damage caused by the ion bombardment, moreover, the high temperature annealing temperature usually exceeds 1200 ℃, and the GaN material starts to decompose at 900 ℃, which damages the material, and the ion activation rate is not high enough, so that the ohmic contact resistance always restricts the GaN device from developing to a higher frequency direction. Even though a capping layer may be deposited or a multi-step rapid annealing may be performed to prevent GaN material from decomposing at a high temperature, the total ion implantation conductance effect is not good, and the solution of this example of the present invention solves the above problem, and meanwhile, in an example, the material of the source structure 109 and the drain structure 110 is doped GaN, which is consistent with the main material of the GaN layer as a channel layer, and may compensate the material of the GaN layer 104 during the epitaxial growth of the source structure and the drain structure.
For example, as shown in fig. 9, after the source structure 109 and the drain structure 110 are grown, the covering portion 106a is removed by sequentially performing wet etching and dry etching. In one example, a wet process is used to remove most of the mask layer 106, and a dry etching process is used to remove the residual impurities, wherein most of the definitions can be designed according to the field and process requirements, and the removal effect can be improved by sequentially performing the wet etching process and the dry etching process on the premise of ensuring the device preparation efficiency. In one example, after the step of performing the dry etching, a step of cleaning the exposed surface of the epitaxial structure, such as the surface of the barrier layer 105, is further included.
As shown in S5 of fig. 1 and fig. 10-11, a gate sidewall 113 is formed between the source structure 109 and the drain structure 110, and the gate sidewall 113 defines a gate region. In this step, a gate sidewall 113 is formed on the sidewalls of the source structure 109 and the drain structure 110 that have already been formed, where the thickness of the gate sidewall 113 may be determined according to the gate length of the subsequently formed gate structure, or may be determined by the size of the gate region that is needed, so as to implement the self-alignment described in the present invention, and in this way, the gate length of the gate structure is equal to the distance between the adjacent source structure 109 and the drain structure 110 minus twice the thickness of the gate sidewall 113, that is, LGrid＝LMask film-2*LSide wallWherein L isMask filmWhich represents the distance between adjacent source structures 109 and drain structures 110, i.e., the width of the cap portion 106 a. By the method, the gate length, the gate-source distance and the gate-drain distance can be determined by the thickness of the deposited side wall material, the process is simple and controllable, the size of the gate is controlled by the thickness of the isolation side wall, the step of gate foot photoetching is omitted, the process is simplified, meanwhile, the error caused by an alignment process is avoided, the size of the gate is accurately defined, and the bottleneck of photoetching alignment is broken through because the thickness can be controlled at a nanometer level. In addition, the source structure 109 and the drain structure 110 grown based on the double epitaxy process of the present invention further haveThe implementation of the self-alignment process is facilitated, and therefore the implementation and simplification of the whole device preparation process are facilitated.
In one example, the method for manufacturing the semiconductor device structure further comprises the steps of: a dielectric passivation layer 114 is formed on the surface of the epitaxial structure 102 around the source structure 109, the drain structure 110, and both. In one example, the dielectric passivation layer 114 covers between adjacent ones of the source structure 109 and the drain structure 110 and extends onto sidewalls of the source structure 109 and the drain structure 110 and portions of upper surfaces thereof, as shown in fig. 12. In this example, the dielectric passivation layer 114 serves as a gate dielectric layer of the device on the one hand and a passivation layer on the surface of the device material on the other hand. In an alternative example, the dielectric passivation layer 114 is formed by an atomic layer deposition process, the material of the dielectric passivation layer 114 includes a high-k dielectric layer, such as Al2O3, and the thickness of the dielectric passivation layer 114 is between 10nm and 50nm, such as 12nm, 15nm, 20nm, 25nm, 30nm, 45nm, and so on. Through the conditions, a compact material layer can be obtained, the thickness of the obtained medium passivation layer is controllable, the functions of the gate medium layer and the passivation layer are favorably exerted, and in addition, high-dielectric-constant medium layers such as Al2O3 and the like are more effective in preventing the current collapse of the device compared with Si3N4 and the like. In addition, when the dielectric passivation layer 114 is formed, the gate length of the gate structure is equal to the distance between the adjacent source structure 109 and drain structure 110 minus two times the thickness of the gate sidewall 113 minus two times the thickness of the dielectric passivation layer 114, i.e., LGrid＝LMask film-2*LSide wall-2*LDielectric passivation layerAnd the effective control of the gate length can be realized, the error caused by the alignment process is avoided, and the bottleneck of photoetching alignment is broken through.
In addition, referring to fig. 10-12, an example of forming the gate sidewall 113 and the dielectric passivation layer 114 is provided, wherein, first, as shown in fig. 10, a continuous dielectric passivation material layer 111 and a sidewall material layer 112 are sequentially formed on the structure where the source structure 109 and the drain structure 110 are formed, the dielectric passivation material layer 111 may be formed by atomic film deposition ALD, and the sidewall material layer 112 may be deposited by plasma enhanced chemical vapor deposition PECVD, which includes but is not limited to Si3N 4.
In an example, the sidewall material layer 111 above the source structure 109, the drain structure 110, and a portion of the epitaxial structure 102 is removed by using an anisotropic etching process, which is beneficial to control the size of the obtained gate sidewall 113, and the sidewall material layer 111 on the side portions of the source structure 109 and the drain structure 110 is retained to form the gate sidewall 113 and define the gate region by the gate sidewall 113. Optionally, by plasma dry etching, the Si3N4 dielectric on the surface of the material is etched away by SF6 anisotropic etching, and only the sidewall material on both sides of the source and drain is left.
As shown in S6 of fig. 1 and fig. 12, a gate structure 117 is formed on the epitaxial structure 102 corresponding to the gate region to fabricate a gan device. In addition, the method for manufacturing the semiconductor device structure further includes a step of manufacturing a source electrode 115 and a drain electrode 116, wherein the source electrode 115 is formed on a portion of the surface of the source structure 109, and the drain electrode 116 is formed on a portion of the surface of the drain structure 110. In an example, the dielectric passivation layer 111 at the corresponding positions of the source electrode 115 and the drain electrode 116 is removed by a photolithography and etching process to obtain the dielectric passivation layer 114, wherein the dielectric passivation layer 111 can be removed by a wet process, for example, Al2O3 is removed by the wet process, and then the source electrode 115 is formed on the exposed source structure 109, wherein Ti/Al/Ni/Au can be deposited on the source structure 109 to form the source electrode 115, and similarly, the drain electrode 116 can be formed based on the same process and material. In an example, the gate structure 117 may be formed after the source electrode 115 and the drain electrode 116 are formed, for example, a mask layer may be formed through a photolithography process, and then the gate structure 117 is formed in the gate region defined by the gate sidewall 113, where the gate structure 117 may be Ni/Au and also serves as an extraction electrode. In addition, in an optional example, the gate structure 117 includes a gate layer formed between the gate sidewalls 113 and a gate cap formed on the gate layer, where an outer edge of the gate cap does not exceed an interface between the gate sidewall 113 and the source structure and the drain structure, which is beneficial to preventing leakage of a device.
As shown in fig. 12 and referring to fig. 1 to 11, the present invention further provides a gallium nitride device structure combining a secondary epitaxy and a self-alignment process, wherein the gallium nitride device structure is preferably prepared by using the gallium nitride device structure preparation method of the present invention, and of course, other methods may also be used, and various features of the gallium nitride device structure and descriptions related thereto may refer to descriptions in the gallium nitride device structure preparation method of this embodiment, and are not described herein again, and the gallium nitride device structure includes:
a semiconductor substrate 101;
an epitaxial structure 102 formed on the semiconductor substrate 101, the epitaxial structure 102 including a gallium nitride layer 104;
a source structure 109 and a drain structure 110, both epitaxially grown on the surface of the gallium nitride layer 104;
a gate sidewall 113 formed between the source structure 109 and the drain structure 110 and defining a gate region;
a gate structure 117 is formed on the epitaxial structure 102 corresponding to the gate region to form a gan device.
As an example, the epitaxial structure 102 includes, in order from bottom to top: a buffer layer 103, the gallium nitride layer 104, and a barrier layer 105, wherein the source structure 109 and the drain structure 110 are formed on the surface of the gallium nitride layer 104 through the barrier layer 105.
As an example, the buffer layer 103 comprises an AlxGa1-xN layer, the barrier layer 105 comprises an AlyGa1-yN layer, the thickness of the barrier layer 105 is between 20-100nm, and the thickness of the gallium nitride layer 104 is between 0.5um-2um, where 0< x <1, 0< y < 1.
As an example, the source structure 109 comprises a doped gallium nitride layer, and the drain structure 110 comprises a doped gallium nitride layer; the semiconductor device structure further includes a drain electrode 115 and a source electrode 116, the drain electrode 116 is formed on the surface of the drain structure 110, and the source electrode 115 is formed on the surface of the source structure 109.
As an example, a dielectric passivation layer 114 is further formed between the gate sidewall 113 and the epitaxial structure 102, the gate structure 117 is formed on the dielectric passivation layer 114, and the dielectric passivation layer 114 further extends to the side portions and a portion of the upper surfaces of the source structure 109 and the drain structure 110.
Illustratively, the material of the dielectric passivation layer 114 includes a high dielectric constant dielectric layer, and the thickness of the dielectric passivation layer 114 is between 10nm and 50 nm.
In summary, the gallium nitride device structure and the preparation method thereof in combination with the secondary epitaxy and the self-alignment process of the invention can effectively reduce the ohmic contact resistance by the method of forming the source electrode structure and the drain electrode structure by the secondary epitaxy growth, and simultaneously balance the etching rate and the material damage caused by etching by the steps of ion etching, oxidation and acid solvent digital etching before the secondary epitaxy, thereby ensuring the material quality and considering the process cost. In addition, by utilizing the self-alignment technology, the error caused by the alignment process in the photoetching process is avoided, and the size of the grid electrode is accurately defined. Meanwhile, the size of the grid is controlled by the thickness of the isolation side wall, so that a step of etching a grid foot is omitted, and the process is simplified. The heteroepitaxy of the GaN material can be realized on the large-size wafer, and the unit-size epitaxy cost is saved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. A preparation method of a gallium nitride device structure combining secondary epitaxy and self-alignment process is characterized by comprising the following steps:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a gallium nitride layer;
forming an etching mask layer on the epitaxial structure, wherein the etching mask layer is provided with a covering part at least covering a grid electrode area of a grid electrode structure to be formed, and a first opening and a second opening which expose the epitaxial structure, the epitaxial structure is etched based on the etching mask layer, the epitaxial structure comprises the steps of sequentially carrying out first etching and second etching on the epitaxial structure, the first etching comprises the step of multi-step ion etching, the second etching comprises the step of carrying out etching by oxidizing and combining acid solvent, and the etching power of the ion etching in each step is gradually reduced in the technological process of the multi-step ion etching; in the technological process of etching by the pickling solvent, stopping the pickling solvent etching process on the two-dimensional electron gas surface of the gallium nitride layer;
epitaxially growing a source electrode structure and a drain electrode structure at positions corresponding to the first opening and the second opening based on the etching mask layer, wherein the source electrode structure and the drain electrode structure are both grown on the surface of the gallium nitride layer;
forming a grid side wall between the source electrode structure and the drain electrode structure, wherein the grid side wall defines a grid region;
forming a gate structure on the epitaxial structure corresponding to the gate region to prepare a gallium nitride device;
and after the source electrode structure and the drain electrode structure are grown, removing the covering part to expose the epitaxial structure, and after the covering part is removed, forming a medium passivation layer by adopting an atomic layer deposition process to be used as a gate dielectric layer of the device and a passivation layer on the surface of a device material, wherein the medium passivation layer covers between the adjacent source electrode structure and the drain electrode structure and extends to the side walls of the source electrode structure and the drain electrode structure and part of the upper surface of the source electrode structure and the drain electrode structure, the medium passivation layer comprises a high dielectric constant dielectric layer, and the thickness of the medium passivation layer is between 10nm and 50 nm.
2. The method of claim 1, wherein the step of forming the epitaxial structure on the semiconductor substrate comprises: and epitaxially forming a buffer layer on the semiconductor substrate, epitaxially forming the gallium nitride layer on the buffer layer, and epitaxially forming a barrier layer on the gallium nitride layer.
3. The method of claim 2, wherein the step of epitaxially growing the source structure and the drain structure on the epitaxial structure comprises:
etching the epitaxial structure based on the etching mask layer, respectively forming a source opening and a drain opening corresponding to the first opening and the second opening, and exposing the gallium nitride layer from the source opening and the drain opening;
and epitaxially growing the doped source electrode structure on the surface of the gallium nitride layer corresponding to the source electrode opening, and epitaxially growing the doped drain electrode structure on the surface of the gallium nitride layer corresponding to the drain electrode opening.
4. The method according to claim 1, wherein the step of growing the source structure and the drain structure on the surface of the GaN layer comprises:
placing the structure obtained after the epitaxial structure is etched in a reaction chamber of epitaxial equipment;
raising the temperature in the reaction chamber to 1200-1250 ℃, and introducing impurity-removing gas;
and controlling the temperature in the reaction chamber to be 1150-1170 ℃, and introducing a gas source to grow the doped source electrode structure and the doped drain electrode structure, wherein the source electrode structure and the drain electrode structure both comprise doped gallium nitride layers.
5. The method according to claim 1, wherein the covering portion is removed by wet etching and dry etching sequentially after the source structure and the drain structure are grown.
6. The method according to claim 1, wherein the step of forming the gate spacer comprises: and forming continuous side wall material layers on the structures for forming the source electrode structure and the drain electrode structure, removing the side wall material layers above the source electrode structure, the drain electrode structure and part of the epitaxial structure by adopting an anisotropic etching process, and reserving the side wall material layers at the side parts of the source electrode structure and the drain electrode structure so as to form the grid side wall and limit the grid region through the grid side wall.
7. The method of claim 1, further comprising a step of forming a source electrode and a drain electrode, wherein the source electrode is formed on a portion of the surface of the source structure, and the drain electrode is formed on a portion of the surface of the drain structure.
8. A gan device structure incorporating double epitaxy and self-aligned processes, the semiconductor device structure comprising:
a semiconductor substrate;
an epitaxial structure formed on the semiconductor substrate, the epitaxial structure including a gallium nitride layer;
the source electrode structure and the drain electrode structure are epitaxially grown on the two-dimensional electron gas surface of the gallium nitride layer;
the grid side wall is formed between the source electrode structure and the drain electrode structure and limits a grid region;
the gate structure is formed on the epitaxial structure corresponding to the gate region so as to form a gallium nitride device;
a dielectric passivation layer is further formed between the gate sidewall and the epitaxial structure, the gate structure is formed on the dielectric passivation layer, the dielectric passivation layer further extends to the side portions and partial upper surfaces of the source electrode structure and the drain electrode structure, the dielectric passivation layer is made of a high dielectric constant dielectric layer, and the thickness of the dielectric passivation layer is between 10nm and 50 nm.
9. The gallium nitride device structure combined with secondary epitaxy and self-aligned process according to claim 8, wherein the epitaxial structure comprises, in order from bottom to top: the buffer layer, the gallium nitride layer and the barrier layer, wherein the source electrode structure and the drain electrode structure penetrate through the barrier layer to be formed on the surface of the gallium nitride layer.
10. The gan device structure of claim 9 combining double epitaxy and self-aligned process wherein the buffer layer comprises a layer of AlxGa1-xN, the barrier layer comprises a layer of AlyGa1-yN, the thickness of the barrier layer is between 15-100nm, and the thickness of the gan layer is between 0.5-2 μm, where 0< x <1, 0< y < 1.
11. The gallium nitride device structure combined with secondary epitaxy and self-aligned process according to claim 8, wherein the source structure comprises a doped gallium nitride layer and the drain structure comprises a doped gallium nitride layer; the semiconductor device structure further comprises a drain electrode and a source electrode, wherein the source electrode is formed on the surface of the source structure, and the drain electrode is formed on the surface of the drain structure.
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