CN111192827B - Preparation method of p-GaN cap layer of enhanced high electron mobility transistor - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 96
- 239000000463 material Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 40
- 238000002347 injection Methods 0.000 claims abstract description 33
- 239000007924 injection Substances 0.000 claims abstract description 33
- 230000000903 blocking effect Effects 0.000 claims abstract description 28
- 238000002513 implantation Methods 0.000 claims description 24
- 238000001312 dry etching Methods 0.000 claims description 20
- 238000001039 wet etching Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000009616 inductively coupled plasma Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 claims description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 2
- 150000002902 organometallic compounds Chemical class 0.000 claims 1
- 229910001425 magnesium ion Inorganic materials 0.000 abstract description 12
- 238000009826 distribution Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 311
- 229910002601 GaN Inorganic materials 0.000 description 156
- 230000008569 process Effects 0.000 description 15
- 239000000758 substrate Substances 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 229910002704 AlGaN Inorganic materials 0.000 description 9
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 239000000203 mixture Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 5
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002156 mixing Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013386 optimize process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a p-GaN cap layer of an enhanced high electron mobility transistor. The invention provides a preparation method of a p-GaN cap layer of an enhanced high electron mobility transistor, which comprises the following steps: providing an epitaxial wafer comprising a channel layer and a barrier layer which are sequentially stacked; sequentially growing an injection barrier layer and an AlN layer on the surface of the barrier layer, which is far away from the channel layer, and etching the partial injection barrier layer and the AlN layer to expose partial area on the surface of the barrier layer to form a p-GaN cap layer area window; and epitaxially growing a p-GaN material layer on the surface of the AlN layer, which is far away from the injection blocking layer, and the window of the p-GaN cap layer area, and etching the p-GaN material layer, the AlN layer and the injection blocking layer in the area outside the window of the p-GaN cap layer area to form the p-GaN cap layer. The method solves the problems of poor epitaxial uniformity and non-uniform Mg ion distribution in the p-GaN cap layer in the existing preparation process of the p-GaN cap layer.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a p-GaN cap layer of an enhanced high electron mobility transistor.
Background
A High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor, and a High mobility two-dimensional electron gas (2DEG) exists in a heterojunction, so that the HEMT device has High frequency, High power, High temperature resistance, strong radiation resistance and other excellent performances. At present, the p-GaN HEMT is the most attractive device type, and due to the intrinsic polarization effect, the device is usually in a depletion type, and the device is turned off by applying negative voltage bias to a grid, so that the difficulty is increased for the design of a negative voltage driving circuit, the static power consumption of the device is increased, and the safety of a system is reduced. The p-GaN enhanced HEMT device can reduce the power consumption and complexity of a system and improve the safety, thereby having wide application prospect in high-temperature and radio-frequency integrated circuits, high-speed switches and microwave monolithic integrated circuits.
Currently, the mainstream technology for realizing a p-GaN enhancement type HEMT device is to introduce a p-GaN cap layer structure between the lower part of a gate electrode and a barrier layer, wherein the p-GaN can partially or completely remove 2DEG below the gate to enable the threshold voltage (Vth) to drift forward. For the preparation of the p-GaN cap layer in the grid region, after a p-GaN cap layer region window is formed in the grid region part of the barrier layer by the traditional method, a p-GaN material layer is epitaxially grown in the p-GaN cap layer region window for the second time, and then the p-GaN cap layer is formed. The secondary epitaxy scheme is an effective means for solving the problem that the etching depth of the p-GaN is difficult to control, but has self disadvantages, such as poor secondary epitaxy uniformity of the p-GaN cap layer, uneven Mg ion distribution in the p-GaN cap layer and the like.
Based on the consideration, the preparation method of the p-GaN cap layer with good uniformity and high stability needs to be developed urgently, and the development of the GaN power device industry in China is promoted.
Disclosure of Invention
The invention mainly aims to provide a preparation method of a p-GaN cap layer of an enhanced high-electron-mobility transistor, aiming at solving the problems of poor epitaxial uniformity and non-uniform Mg ion distribution in the p-GaN cap layer in the existing preparation process of the p-GaN cap layer.
The present invention also provides a method for fabricating an enhancement mode hemt, and further provides an enhancement mode hemt fabricated by the above method.
In order to achieve the purpose, the invention adopts the following technical scheme:
a preparation method of a p-GaN cap layer of an enhanced high electron mobility transistor comprises the following steps:
providing an epitaxial wafer, wherein the epitaxial wafer comprises a channel layer and a barrier layer which are sequentially stacked;
sequentially growing an injection blocking layer and an AlN layer on the surface of the barrier layer, which is far away from the channel layer, and etching partial injection blocking layer and the AlN layer to expose partial area on the surface of the barrier layer to form a p-GaN cap layer area window;
and epitaxially growing a p-GaN material layer on the surface of the AlN layer, which is far away from the injection blocking layer, and the window of the p-GaN cap layer area, and etching the p-GaN material layer, the AlN layer and the injection blocking layer in the area outside the window of the p-GaN cap layer area to form a p-GaN cap layer.
According to the preparation method of the p-GaN cap layer of the enhanced high electron mobility transistor, the AlN layer grows on the injection blocking layer before the p-GaN cap layer area window is formed, on one hand, the p-GaN can grow on the surface of the AlN layer, so that the p-GaN can be ensured to grow uniformly on the surface of the whole epitaxial wafer, the problem of uneven Mg ion distribution caused by the fact that the p-GaN is limited in the narrow p-GaN cap layer area window to grow is effectively avoided, and the uniformity and the stability of the p-GaN cap layer are improved; on the other hand, the AlN layer grows on the injection barrier layer, a high-temperature condition is not needed, the condition is mild, the influence on an epitaxial wafer is small, the process difficulty is reduced, the method is simple, the operation is simple and convenient, and the mass production is easy.
Correspondingly, the preparation method of the enhancement type high electron mobility transistor comprises the following steps:
providing an epitaxial wafer, wherein the epitaxial wafer comprises a channel layer and a barrier layer which are sequentially stacked;
preparing a p-GaN cap layer on the surface of the barrier layer, which is deviated from the channel layer, by using the preparation method;
and arranging a grid electrode on the p-GaN cap layer, and preparing a source electrode and a drain electrode on the barrier layer.
Correspondingly, the enhanced high electron mobility transistor prepared by the preparation method is provided.
The preparation method of the enhanced high electron mobility transistor provided by the invention is simple and convenient, is easy to operate, has good uniformity of the p-GaN cap layer in the enhanced high electron mobility transistor prepared by the preparation method, has high stability, and is suitable for large-scale mass production of the enhanced high electron mobility transistor.
Drawings
Fig. 1 is a schematic view of a thin-layer structure of an epitaxial wafer used in example 1;
FIG. 2 shows the surface growth of SiO on the epitaxial wafer of example 12A schematic of the thin layer structure behind the layer and barrier layer;
FIG. 3 shows the surface growth of SiO on the epitaxial wafer of example 12Layer, barrier layer and photoresistSchematic diagram of the thin layer structure of (1);
FIG. 4 is a schematic diagram of the structure of the thin layer after forming the window of the p-GaN cap layer region by photolithography definition in embodiment 1;
FIG. 5 is a schematic view showing the structure of a thin layer after epitaxially growing a p-GaN material layer on the entire surface of the epitaxial wafer of example 1;
FIG. 6 is a schematic structural diagram of a thin layer of the epitaxial wafer of example 1 after a photoresist is spread on a surface of the p-GaN material layer away from the window of the p-GaN cap layer region;
FIG. 7 is a schematic view of an epitaxial structure with a p-GaN cap layer grown on the surface in example 1;
fig. 8 is a schematic view of a thin layer structure of the p-GaN enhancement type HEMT obtained by the preparation of example 2.
Detailed Description
In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
In order to solve the problems of poor epitaxial uniformity and uneven Mg ion distribution in the p-GaN cap layer in the existing preparation process of the p-GaN cap layer, the embodiment of the invention provides the following specific technical scheme:
a preparation method of a p-GaN cap layer of an enhanced high electron mobility transistor comprises the following steps:
s01, providing an epitaxial wafer, wherein the epitaxial wafer comprises a channel layer and a barrier layer which are sequentially stacked;
s02, sequentially growing an injection barrier layer and an AlN layer on the surface of the barrier layer, which is far away from the channel layer, and etching partial injection barrier layer and the AlN layer to expose partial area on the surface of the barrier layer to form a p-GaN cap layer area window;
s03, epitaxially growing a p-GaN material layer on the surface of the AlN layer, which is far away from the injection blocking layer, and the p-GaN cap layer area window, and etching the p-GaN material layer, the AlN layer and the injection blocking layer outside the p-GaN cap layer area window to form a p-GaN cap layer.
According to the preparation method of the p-GaN cap layer of the enhanced high electron mobility transistor, provided by the embodiment of the invention, the AlN layer grows on the injection blocking layer before the p-GaN cap layer area window is formed, on one hand, the p-GaN can grow on the surface of the AlN layer, the p-GaN can be ensured to grow uniformly on the surface of the whole epitaxial wafer, the problem of uneven Mg ion distribution caused by the fact that the p-GaN is limited in the narrow p-GaN cap layer area window to grow is effectively avoided, and therefore the uniformity and the stability of the p-GaN cap layer are improved; on the other hand, the AlN layer grows on the injection blocking layer, high-temperature conditions are not needed, the conditions are mild, the influence on the epitaxial wafer is small, the process difficulty is reduced, the method is simple, the operation is simple and convenient, and the mass production is easy.
Specifically, in step S01, the epitaxial wafer is used as a substrate for epitaxially growing a p-GaN cap layer, and includes a channel layer and a barrier layer, which are sequentially stacked. In an embodiment of the present invention, the material of the channel layer and/or the material of the barrier layer is preferably a group iii nitride. Wherein the group III nitride includes, but is not limited to, GaN, AlGaN, InN, InAlN, InGaN, BN, BALN, BInN, BGaN, InAlGaN, BALGaN, BInGaN, BInAlN, and the like. As a first embodiment, the epitaxial wafer includes an AlGaN barrier layer and a GaN channel layer; as a second embodiment, a GaN or SiN cap layer is added on the surface of the AlGaN barrier layer in the first embodiment to increase the effective barrier height of the barrier layer; in a third embodiment, the thin ALN layer is inserted into the ALGaN/GaN hetero-interface of the first or second embodiment, so that the effective conduction band level of the barrier layer can be increased. Further, besides the channel layer, the hetero-interface insertion layer, the barrier layer and the barrier layer cap layer, the epitaxial wafer further comprises a substrate and a buffer layer, wherein the buffer layer is arranged on the surface of the substrate, the channel layer is arranged on the surface, away from the substrate, of the buffer layer, and the barrier layer is arranged on the surface, away from the buffer layer, of the channel layer. It is understood that the specific structure of the epitaxial wafer can be added or reduced with some functional layers according to actual product requirements.
In step S02, an implantation barrier layer and an AlN layer are sequentially grown on the surface of the barrier layer away from the channel layerThe injection blocking layer is used for defining a growth window of the p-GaN cap layer, and AlN is in lattice matching with the p-GaN, so that subsequent p-GaN can grow uniformly on the surface of the whole epitaxial wafer, and the p-GaN cap layer has good uniformity and stability. The p-GaN material is a conductive p-GaN material formed by converting a magnesium-doped GaN material, and if the growth of an AlN layer on the injection blocking layer is omitted, due to lattice matching problems, such as SiO, between the p-GaN and the injection blocking layer material2Lattice mismatch, subsequent p-GaN can only grow in a narrow window of the p-GaN cap layer area, Mg ions in the p-GaN are easily captured by the narrow window under the action of airflow of the reaction cavity, and the probability that the Mg ions are captured by the window in the p-GaN epitaxial growth process is different, so that the Mg ions in the p-GaN cap layer are easily distributed unevenly. On the contrary, for the whole Wafer growth, Mg ions spread on the whole surface along with the airflow and participate in the reaction growth, the concentration range is not greatly fluctuated, and as a result, the distribution of the Mg ions in the film is relatively uniform and is easy to control. Furthermore, the semiconductor materials lattice-matched with p-GaN are various, such as gallium nitride materials including GaN, InN and ternary alloys thereof (AlGaN, InGaN), and the like, and compared with the materials, the AlN layer grows on the injection blocking layer without high temperature conditions, the conditions are mild, the influence on the epitaxial wafer is small, and the process difficulty is reduced.
Preferably, in the step of sequentially growing the implantation barrier layer and the AlN layer on the surface of the barrier layer away from the channel layer, the implantation barrier layer is deposited on the surface of the barrier layer away from the channel layer by adopting a plasma enhanced chemical vapor deposition (PEVCD) technology, then the AlN layer is continuously grown on the surface of the implantation barrier layer away from the barrier layer by adopting a magnetron sputtering technology, and SiO is grown by PECVD2The temperature of the epitaxial layer is 300-400 ℃, the LPCVD is 700-800 ℃, and the low growth temperature can avoid the damage of the reaction process to the epitaxial wafer as much as possible. Further, when the AlN layer grows on the surface of the injection blocking layer departing from the barrier layer by adopting a magnetron sputtering technology, the temperature of a growth substrate is controlled to be below 400 ℃. If other methods are used, such as MOCVD, temperatures up to 1000 ℃ or higher may be applied to the epitaxial wafer and the grown SiO2Causing some damage.
In embodiments of the present invention, the implantation barrier layer is preferably SiO2Layer, SiN layer, Si or Al2O3More preferably SiO2Layer of SiO2The growth and etching modes of the epitaxial wafer are simple, the cost is low, BOE solution etching can be adopted, the damage to the epitaxial wafer is low, the operation is simple and controllable, and the advantages are very obvious compared with other barrier layer modes. Further, the implantation barrier layer is preferably 80-100nm thick.
In the present embodiment, the AlN layer thickness is preferably 1-5 nm. When the AlN layer is less than 1nm in thickness, the requirement on the process technology is high, and the process difficulty is increased; when the AlN layer thickness is more than 5nm, the gain effect on the uniformity of Mg ions is not obvious, AlN waste is easily caused, and the etching difficulty is increased.
And etching part of the injection barrier layer and the AlN layer to expose the gate region on the surface of the barrier layer, thereby forming a p-GaN cap layer region window. Preferably, in the step of etching a part of the implantation blocking layer and the AlN layer, the AlN layer in the window of the p-GaN cap layer region is removed by dry etching, and then the implantation blocking layer in the window of the p-GaN cap layer region is removed by wet etching. When the AlN layer is removed by adopting dry etching, the barrier layer is injected to serve as a buffer layer for the dry etching, so that the direct impact of the dry etching on the surface of the barrier layer is avoided; the residual injection barrier layer is etched by a wet method, the etching process can be automatically stopped on the surface of the barrier layer, and the problem of over-etching or insufficient etching caused by only adopting dry etching can be avoided. The embodiment of the invention combines the dry etching and the wet etching in the etching process of the injection barrier layer and the AlN layer, fully utilizes the advantages of simple dry etching process and good platform compatibility, ensures that the low-damage etching is stopped on the surface of the barrier layer, ensures sufficient electron concentration in a channel, has high process repetition rate and good stability, and achieves the effect of optimizing devices.
Furthermore, the dry etching method adopts Inductively Coupled Plasma (ICP), which has the advantages of high etching speed, high selectivity, high anisotropy, small etching damage, good large-area uniformity, high controllability of the etching section profile, smooth and flat etching surface and the like, and is widely applied to etching of materials such as III-V compounds and the like. In some embodiments, dry etching is performed using an inductively coupled plasma formed from a mixture of chlorine and boron trichloride gases, pure chlorine etching is isotropic to achieve an anisotropic process, and boron trichloride is also added to the etch), which has a large molecular weight for physical etching, allowing good control of the sidewall profile. In still other embodiments, the mixing molar ratio of the chlorine gas to the boron trichloride gas is 3:5, and the etching experiment shows that the gas has a proportional etching rate of about 0.8nm/s, and the etching morphology is good, so that the process requirements are met.
Furthermore, the wet etching adopts Buffer Oxide (BOE) to selectively remove silicon oxide, basically does not damage ALGaN, and enables the corrosion to be well controlled. In some embodiments, the buffer oxide is selected to be a mixture of ammonium fluoride (40 wt%) and hydrofluoric acid (49 wt%); in other embodiments, the volume ratio of the ammonium fluoride to the hydrofluoric acid is 6: 1; in still other embodiments, the wet etch has an etch rate of about
As a preferred embodiment, the step of etching a portion of the implantation barrier layer and the AlN layer specifically includes:
s021, paving photoresist on the surface of the AlN layer, which is far away from the injection blocking layer;
s022, patterning the photoresist to enable the AlN layer outside the window area of the p-GaN cap layer area to be masked by the photoresist;
s023, removing the AlN layer in the window of the p-GaN cap layer area by adopting ICP dry etching, specifically, adopting inductively coupled plasma formed by a mixture of chlorine and boron trichloride gas with a molar ratio of 3:5, and etching at a rate of 0.8 nm/S;
s024, removing the implantation barrier layer in the p-GaN cap layer region window by adopting BOE wet etching, specifically, selecting the BOE as a mixture of ammonium fluoride (40 wt%) and hydrofluoric acid (49 wt%) with the volume ratio of 6:1, and performing wet etching to remove the implantation barrier layer in the p-GaN cap layer region window by adopting the BOE wet etching method
Etching at the rate of the second step to expose the gate region on the surface of the barrier layer and form a window of the p-GaN cap layer region.
Specifically, in step S03, a p-GaN material layer is epitaxially grown on the surface of the AlN layer facing away from the implantation barrier layer and the p-GaN cap layer region window, so that p-GaN is uniformly grown on the entire surface of the epitaxial wafer. Preferably, in the step of epitaxially growing the p-GaN material layer on the surface of the AlN layer away from the implantation barrier layer and on the p-GaN cap layer region window, a Metal-organic Chemical Vapor Deposition (MOCVD) technique is used to grow the p-GaN material layer. MOCVD growth rate is moderate, crystal quality is high, equipment is simple, process repeatability is good, the method is very suitable for batch production, the method is a mainstream technology for growth of GaN and heterojunction materials thereof, MBE and HVPE technologies can also be adopted in actual work, MBE growth crystal quality is best, single cost is highest, HEPE growth quality is lowest, and high-temperature H is needed at the same time2The P-GaN passivation device works in the middle, and the P-GaN is easily passivated and loses efficacy.
And etching the p-GaN material layer, the AlN layer and the injection blocking layer in the region outside the window of the p-GaN cap layer region to form a p-GaN cap layer. Preferably, in the step of etching the p-GaN material layer, the AlN layer and the implantation barrier layer in the region outside the window of the p-GaN cap layer region, the p-GaN material layer and the AlN layer in the region outside the window of the p-GaN cap layer region are removed by dry etching, and then the implantation barrier layer in the region outside the window of the p-GaN cap layer region is removed by wet etching. The dry etching and the wet etching are combined, the advantages of simple dry etching process and good platform compatibility are fully utilized, low-damage etching is stopped on the surface of the barrier layer, sufficient electron concentration in a channel is guaranteed, the process repetition rate is high, the stability is good, and the effect of optimizing devices is achieved. Further, referring to step S02, the preferable conditions of the dry etching and the wet etching are not described in detail herein for the sake of brevity.
As a preferred embodiment, the step of etching the p-GaN material layer, the AlN layer, and the implantation barrier layer in the region outside the window of the p-GaN cap layer region specifically includes:
s031, spreading photoresist on the surface of the p-GaN material layer departing from the window of the p-GaN cap layer region, so that the p-GaN material layer within the window region of the p-GaN cap layer region is masked by the photoresist;
s032, removing the p-GaN material layer and the AlN layer outside the window of the p-GaN cap layer region by adopting ICP dry etching, specifically, adopting inductively coupled plasma formed by a mixture of chlorine and boron trichloride gas with a molar ratio of 3:5, and etching at a rate of 0.8 nm/second;
s033, removing the injection blocking layer outside the window of the p-GaN cap layer region by adopting BOE wet etching, specifically, selecting the BOE as a mixture of ammonium fluoride (40 wt%) and hydrofluoric acid (49 wt%) with a volume ratio of 6:1, and mixing
Etching at a rate to form a p-GaN cap layer.
In summary, under the comprehensive action of the optimized process conditions provided by the embodiments of the present invention, the p-GaN cap layer obtained by the preparation method provided by the embodiments of the present invention has the advantages of optimal comprehensive performance, good uniformity and high stability.
Correspondingly, the preparation method of the enhanced high electron mobility transistor comprises the following steps:
A. providing an epitaxial wafer, wherein the epitaxial wafer comprises a channel layer and a barrier layer which are sequentially stacked;
B. preparing a p-GaN cap layer on the surface of the barrier layer, which is far away from the channel layer, by using the preparation method;
C. and arranging a grid electrode on the p-GaN cap layer, and preparing a source electrode and a drain electrode on the barrier layer.
Correspondingly, the enhanced high electron mobility transistor prepared by the preparation method is provided.
The preparation method of the enhanced high electron mobility transistor provided by the invention is simple and convenient, is easy to operate, has good uniformity of the p-GaN cap layer in the enhanced high electron mobility transistor prepared by the preparation method, has high stability, and is suitable for large-scale mass production of the enhanced high electron mobility transistor.
Preferably, the enhancement mode high electron mobility transistor includes:
a substrate;
a buffer layer disposed on a surface of the substrate;
a channel layer disposed on a surface of the buffer layer facing away from the substrate;
a barrier layer disposed on a surface of the channel layer facing away from the buffer layer;
a p-GaN cap layer disposed on a surface of the barrier layer facing away from the channel layer;
the grid electrode is arranged on the p-GaN cap layer;
and a source and a drain disposed on the barrier layer.
Furthermore, the material of the substrate may refer to the conventional technology in the art, and the material of the channel layer and the barrier layer refers to the channel layer and the barrier layer related in the above technical solution, and for brevity, details are not repeated here.
In some embodiments, the substrate is selected as a silicon substrate, the buffer layer is made of GaN, the channel layer is made of GaN, the barrier layer is made of AlGaN, and the p-GaN cap layer is made of a conductive p-GaN material formed by converting a GaN material doped with magnesium.
In order to clearly understand the details and operation of the above-mentioned embodiments of the present invention by those skilled in the art, and to significantly reflect the advanced performance of the method for fabricating the p-GaN cap layer of the enhanced hemt according to embodiments of the present invention, the following embodiments of the present invention are exemplified by the following examples.
Example 1
The embodiment provides a method for preparing a p-GaN cap layer of an enhanced HEMT, which specifically comprises the following steps:
s11, extractingAn epitaxial wafer having the structure shown in FIG. 1, which comprises a silicon substrate, a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer, which are sequentially stacked, and DHF (diluted hydrofluoric acid), SC1 (NH) are sequentially used4OH、H2O2、H2Solution prepared by mixing O according to a certain proportion) and SC2(HCl, H)2O2、H2Solution prepared by mixing O according to a certain proportion) to clean the epitaxial wafer.
S12, depositing a layer of SiO with the thickness of 80nm on the surface of the AlGaN barrier layer away from the channel layer by adopting an LPCVD method2Layer, then proceeding on SiO by magnetron sputtering technique2The surface of the layer facing away from the barrier layer was low temperature grown with a 5nm thick AlN layer to obtain the epitaxial structure shown in fig. 2.
In the AlN layer away from the SiO2Spreading photoresist on the surface of the layer, and defining a gate region part on the surface of the barrier layer by photoetching, as shown in FIG. 3;
patterning the mask layer to enable the AlN layer outside the window area of the p-GaN cap layer area to be shielded by photoresist; then, removing the AlN layer in the window of the p-GaN cap layer area by adopting ICP dry etching; and then, removing the SiO in the window of the p-GaN cap layer area by adopting BOE wet etching2And exposing the gate region part on the surface of the barrier layer to form a p-GaN cap layer region window, wherein the structure is shown in FIG. 4.
S13, separating the AlN layer from the SiO layer by adopting a MOCVD method2And epitaxially growing a p-GaN material layer on the surface of the layer and the window of the p-GaN cap layer region to obtain the structure shown in the figure 5.
Laying photoresist on the surface of the p-GaN material layer, which is away from the window of the p-GaN cap layer region, so that the p-GaN material layer in the window region of the p-GaN cap layer region is masked by the photoresist, and the structure is shown in FIG. 6;
removing the p-GaN material layer and the AlN layer in the region outside the window of the p-GaN cap layer region by adopting ICP dry etching; then, removing the SiO outside the window of the p-GaN cap layer region by adopting BOE wet etching2And forming a p-GaN cap layer, wherein the structure is shown in FIG. 7.
Example 2
The embodiment provides a preparation method of a p-GaN enhancement type HEMT, which comprises the following steps:
providing the epitaxial wafer with the p-GaN cap layer prepared in the embodiment 1, manufacturing a gate on the p-GaN cap layer, and respectively manufacturing a source electrode and a drain electrode in a region where the p-GaN cap layer is not grown on the surface of the barrier layer.
Referring to fig. 8, the p-GaN enhancement HEMT of the present embodiment includes:
a silicon substrate;
a GaN buffer layer disposed on a surface of the silicon substrate;
a GaN channel layer disposed on a surface of the GaN buffer layer facing away from the substrate;
an AlGaN barrier layer disposed on a surface of the GaN channel layer facing away from the GaN buffer layer;
the p-GaN cap layer is arranged on the surface of the AlGaN barrier layer, which is deviated from the channel layer;
the grid electrode is arranged on the p-GaN cap layer;
and a source electrode and a drain electrode disposed on the barrier layer.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A preparation method of a p-GaN cap layer of an enhanced high electron mobility transistor is characterized by comprising the following steps:
providing an epitaxial wafer, wherein the epitaxial wafer comprises a channel layer and a barrier layer which are sequentially stacked;
sequentially growing an injection blocking layer and an AlN layer on the surface of the barrier layer, which is far away from the channel layer, and etching partial injection blocking layer and the AlN layer to expose partial area on the surface of the barrier layer to form a p-GaN cap layer area window;
and epitaxially growing a p-GaN material layer on the surface of the AlN layer, which is far away from the injection blocking layer, and the window of the p-GaN cap layer area, and etching the p-GaN material layer, the AlN layer and the injection blocking layer in the area outside the window of the p-GaN cap layer area to form a p-GaN cap layer.
2. The method according to claim 1, wherein in the step of etching the p-GaN material layer, the AlN layer, and the implantation barrier layer in the region outside the window of the p-GaN cap layer region, the p-GaN material layer and the AlN layer in the region outside the window of the p-GaN cap layer region are removed by dry etching, and then the implantation barrier layer in the region outside the window of the p-GaN cap layer region is removed by wet etching; and/or
And in the step of etching partial injection blocking layer and the AlN layer, removing the AlN layer in the window of the p-GaN cap layer area by adopting dry etching, and then removing the injection blocking layer in the window of the p-GaN cap layer area by adopting wet etching.
3. The manufacturing method according to claim 2, wherein the dry etching employs inductively coupled plasma; and/or
The wet etching adopts a buffer oxide.
4. The method of claim 1, wherein the implantation barrier layer is SiO2Layer, SiN layer, Si layer and Al2O3At least one of the layers.
5. A production method according to any one of claims 1 to 4, characterized in that in the step of epitaxially growing a p-GaN material layer on the surface of the AlN layer facing away from the implantation blocking layer and on the window of the p-GaN cap layer region, the p-GaN material layer is grown by using a metal organic compound chemical vapor deposition technique.
6. The production method according to any one of claims 1 to 4, characterized in that in the step of sequentially growing an implantation barrier layer and an AlN layer on the surface of the barrier layer facing away from the channel layer, the implantation barrier layer is deposited on the surface of the barrier layer facing away from the channel layer by using a plasma enhanced chemical vapor deposition technique, and then the AlN layer is continued on the surface of the implantation barrier layer facing away from the barrier layer by using a magnetron sputtering technique.
7. The method according to any one of claims 1 to 4, wherein the implantation barrier layer is 80-100nm thick; and/or
The AlN layer is 1-5nm thick.
8. The production method according to any one of claims 1 to 4, wherein a material of the channel layer and/or a material of the barrier layer is a group III nitride.
9. A method for preparing an enhanced High Electron Mobility Transistor (HEMT) comprises the following steps:
providing an epitaxial wafer, wherein the epitaxial wafer comprises a channel layer and a barrier layer which are sequentially stacked;
preparing a p-GaN cap layer on a surface of the barrier layer facing away from the channel layer by using the preparation method according to any one of claims 1 to 8;
and arranging a grid electrode on the p-GaN cap layer, and preparing a source electrode and a drain electrode on the barrier layer.
10. An enhancement mode high electron mobility transistor made by the method of claim 9.
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| CN107634009A (en) * | 2017-08-10 | 2018-01-26 | 北京大学深圳研究生院 | A kind of GaN MOS HEMT devices and preparation method thereof |
| CN110034186A (en) * | 2018-01-12 | 2019-07-19 | 中国科学院苏州纳米技术与纳米仿生研究所 | The enhanced HEMT of group III-nitride and preparation method thereof based on composite potential barrier layer structure |
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| CN107634009A (en) * | 2017-08-10 | 2018-01-26 | 北京大学深圳研究生院 | A kind of GaN MOS HEMT devices and preparation method thereof |
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