CN110429127B - Gallium nitride transistor structure and preparation method thereof - Google Patents

Gallium nitride transistor structure and preparation method thereof Download PDF

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CN110429127B
CN110429127B CN201910673099.4A CN201910673099A CN110429127B CN 110429127 B CN110429127 B CN 110429127B CN 201910673099 A CN201910673099 A CN 201910673099A CN 110429127 B CN110429127 B CN 110429127B
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刘煦冉
程海英
王敬
宋东波
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Wuhu Qidi Semiconductor Co ltd
Tsinghua University
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Tsinghua University
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Abstract

The invention discloses a gallium nitride transistor structure and a preparation method thereof. The gallium nitride transistor structure includes a substrate 1; a GaN-based buffer layer 2 on the substrate 1; in on the GaN-based buffer layer 2xAlyGa1‑x‑yAn N/GaN heterojunction epitaxial structure; in is located InxAlyGa1‑x‑yA source electrode 6 at one end of the surface of the N/GaN heterojunction epitaxial structure; in is located InxAlyGa1‑x‑yA drain electrode 5 at the other end of the surface of the N/GaN heterojunction epitaxial structure; in is located InxAlyGa1‑x‑yA p-type oxide film on the surface of the N/GaN heterojunction epitaxial structure and a grid electrode 7. The invention is realized by adding InxAlyGa1‑x‑yA p-type oxide thin film is arranged between a source electrode 6 and a drain electrode 5 on the surface of the N/GaN heterojunction epitaxial structure, the obtained GaN transistor structure with the p-type oxide intercalation can inhibit the current collapse effect, and the virtual gate effect is relieved by utilizing holes in the p-type oxide to neutralize electrons captured by surface traps.

Description

Gallium nitride transistor structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a gallium nitride transistor structure and a preparation method thereof.
Background
The device based on traditional semiconductor materials such as Si, GaAs and the like is limited by the properties of the materials, so that the corresponding indexes of the power semiconductor device are difficult to further improve. In recent years, the third generation wide bandgap semiconductor materials based on group iii nitrides have been developed rapidly. GaN has excellent material properties such as wide forbidden band, high saturated electron drift rate, high breakdown field strength, high thermal conductivity and the like, and has great development potential in the fields of high-frequency, high-temperature, high-power, ultraviolet LEDs and the like. In addition, GaN has excellent electronic characteristics, can form a modulation doped AlGaN/GaN heterostructure with AlGaN, obtains higher two-dimensional electronic air density than a second generation compound semiconductor heterojunction structure, and is praised as an ideal material for developing microwave and power devices. Therefore, the AlGaN/GaN-based heterojunction device has a good application prospect in the fields of high-frequency and high-power wireless communication, radars, power electronic switches, inverters and the like.
Although AlGaN/GaN devices have made great progress in microwave and high power device characteristics, there is still an important limitation, namely, the current collapse effect. During the operation of the GaN high-voltage device, electrons can be trapped by a trap of the GaN, so that the on-resistance is increased and the current density is reduced. The current collapse is divided into drain delay and gate delay, the former is generally considered to be related to traps in a GaN buffer layer and a barrier layer, and the influence of the current collapse is smaller and smaller with the improvement of epitaxy and doping processes; the latter is mainly caused by the surface states of the barrier layers, and is related to the polarization charges and the energy band structure of the heterojunction surface. The surface state trapped electrons between the gate and the drain form a virtual gate, which is the main mechanism causing the current collapse effect. This effect is even more pronounced, especially at high pressures.
In order to solve the current collapse effect, the prior art widely adopts a field plate structure and a passivation technology. The basic structure of the field plate is that a layer of dielectric film is prepared on the periphery of a grid electrode and a source electrode by deposition, photoetching and etching methods, and the grid electrode or the source electrode is properly extended to the upper part of a dielectric, so that a circle of metal-insulating layer-semiconductor structure is formed on the periphery of an electrode. The field plate structure changes the electric field distribution in the depletion layer by changing the bending degree of the boundary of the depletion layer at the edge of the grid electrode, reduces the peak electric field intensity and improves the breakdown voltage of the device. Passivation techniques mitigate the current collapse effect by suppressing surface states, reducing leakage current. However, even if these two technologies are combined, it is still difficult to obtain satisfactory GaN devices under high voltage conditions. In recent years, it has been proposed to suppress the current collapse effect by introducing a p-GaN or p-AlGaN thin layer between the gate and the drain region and neutralizing electrons trapped by traps with holes in the p-GaN or p-AlGaN thin layer. However, the etching selection between the p-AlGaN or p-GaN and the epitaxial AlGaN barrier layer is relatively small, which brings certain difficulty for the device process.
Disclosure of Invention
The invention aims to provide a gallium nitride transistor structure and a preparation method thereof. By InxAlyGa1-x-yA p-type oxide functional layer is arranged on the N-type barrier layer, and the virtual gate effect is relieved by utilizing the holes in the p-type oxide to neutralize electrons captured by the surface traps; meanwhile, the growth process of the p-type oxide is simple, and the p-type oxide is mixed with InxAlyGa1-x-yThe N barrier layers are made of different materials and are easy to selectively etch.
The technical scheme adopted by the invention is as follows:
a gallium nitride transistor structure comprising a substrate; a GaN-based buffer layer located over the substrate; a GaN-based channel layer located above the GaN-based buffer layer; in over GaN-based channel layerxAlyGa1-x-yN barrier layer of which x is not less than 0<1,0≤y<1, and x + y is not equal to 0; in is located InxAlyGa1-x-yA source electrode at one end above the N barrier layer; in is located InxAlyGa1-x-yA drain electrode at the other end above the N barrier layer; a gate electrode between the source electrode and the drain electrode; and a p-type oxide functional layer located between the gate and the drain.
Further, the substrate may be Si, GaN, sapphire, or SiC material.
Further, the p-type oxide functional layer partially or completely covers In between the grid and the drainxAlyGa1-x- yA region above the N-barrier layer.
Further, the p-type oxide functional layer comprises p-NiO, p-ZnO and p-Al2O3Or a composite structure of any two or three of them.
Furthermore, the source electrode and the drain electrode are ohmic contact metal electrodes, and the ohmic contact metal electrodes are formed by single-layer or multi-layer metal and InxAlyGa1-x-yThe N-barrier layer forming an ohmic contactAnd an electrode.
Further, the grid electrode is a Schottky contact metal electrode I, and the Schottky contact metal electrode I is formed by a single layer or multiple layers of metal and InxAlyGa1-x-yThe N-barrier layer forms an electrode of the schottky contact.
Further, the grid electrode is an insulated grid structure electrode which is composed of a grid metal, a grid dielectric layer and InxAlyGa1-x-yAnd a metal-semi-insulator-semiconductor structure is formed among the N barrier layers.
Further, the InxAlyGa1-x-yAnd a p-GaN cap layer is arranged above the surface of the N barrier layer, the grid is a Schottky contact electrode II, and the Schottky contact electrode II is an electrode in Schottky contact formed between single-layer or multi-layer metal and the p-GaN cap layer.
Furthermore, a groove etching structure is arranged below the grid electrode and comprises a part of In etching structurexAlyGa1-x-yN barrier layer, or In is etched entirelyxAlyGa1-x-yN barrier layer, or In is etched entirelyxAlyGa1-x-yAnd etching part of the GaN-based channel layer after the N barrier layer.
Further, the p-type oxide functional layer is interconnected with the drain metal electrode through a Schottky contact electrode III; the Schottky contact electrode III is an electrode which forms Schottky contact between a single-layer or multi-layer metal and a p-type oxide functional layer.
Further, the schottky contact electrode iii and the schottky electrode ii are made of the same material.
Furthermore, the uppermost layer of the gallium nitride transistor structure is covered with a passivation layer; the passivation layer comprises Si3N4、Al2O3、AlN、Y2O3、La2O3、Ta2O5、TiO2、HfO2、ZrO2A single-layer or multi-layer composite structure of (1).
The invention also provides a preparation method of the gallium nitride transistor, which comprises the following steps:
(1) growing a GaN-based buffer layer on a substrate, growing a GaN-based channel layer on the GaN-based buffer layer, and growing In on the GaN-based channel layerxAlyGa1-x-yAn N barrier layer;
(2) inxAlyGa1-x-yForming a p-type oxide film above the N barrier layer, defining a p-type oxide functional layer area by a photoetching method, and etching the p-type oxide film outside the defined range;
(3) inxAlyGa1-x-yAn active region is defined on the N barrier layer;
(4) defining a source electrode area and a drain electrode area on the active area, and depositing an ohmic contact metal electrode to form a source electrode and a drain electrode;
(5) and defining a grid electrode area on the active area, and depositing a Schottky contact metal electrode to form a grid electrode.
Further, the step (1) further comprises the step of adding InxAlyGa1-x-yGrowing a p-GaN cap layer on the N barrier layer; and removing the p-GaN layer outside the gate region.
Further, the step (5) further comprises defining a gate region on the p-GaN cap layer of the active region, and depositing a schottky contact metal electrode ii to form a gate schottky contact electrode.
Further, the step (5) is followed by defining an electrode forming area on the surface of the p-type oxide functional layer by photolithography, depositing a schottky contact electrode iii, and interconnecting the p-type oxide functional layer with the drain metal electrode through the schottky contact electrode iii.
Compared with the prior art, the invention has the following advantages:
(1) the invention is realized by adding InxAlyGa1-x-yA p-type oxide functional layer is arranged between a source electrode and a drain electrode on the N barrier layer, the GaN transistor structure reinforced by the p-type oxide functional layer is obtained, the current collapse effect can be inhibited, and the virtual gate effect is relieved by utilizing holes in the p-type oxide to neutralize electrons captured by surface traps.
(2) The p-type oxide functional layer can partially deplete two-dimensional electron gas in the channel, and when the p-type oxide functional layer is arranged in the edge area of the grid or the drain, electric field concentration under high voltage can be relieved, and breakdown voltage of the device is improved.
(3) The structure can promote the p-type oxide to inject holes into the GaN semiconductor when the drain electrode is connected with positive large voltage, reduce the probability that electrons near the drain electrode are trapped by surface defects under high voltage, and further inhibit the current collapse effect.
(4) Compared with the method for forming a part of p-GaN or p-AlGaN thin layer between the grid electrode and the drain electrode to inhibit the current collapse effect, the method has the advantage that the growth process of the p-type oxide is relatively simple. In addition, because of the low etching selectivity, the etching is InxAlyGa1-x-yThere are difficulties with p-GaN or p-AlGaN processes over N barrier layers. And p-type oxide and InxAlyGa1-x-yThe N barrier layer is made of different materials, so the N barrier layer has higher etching selection ratio, and is beneficial to stably stopping In when the p-type oxide functional layer is etchedxAlyGa1-x-yAnd an N barrier layer.
Drawings
Fig. 1 is a structural view of a gallium nitride transistor in example 1;
FIG. 2 is a structural view of a gallium nitride transistor in example 2;
FIG. 3 is a structural view of a gallium nitride transistor in example 3;
FIG. 4 is a structural view of a gallium nitride transistor in example 4;
the reference numbers in the drawings are respectively as follows: 1-substrate, 2-GaN-based buffer layer, 3-GaN-based channel layer, and 4-InxAlyGa1-x-yThe structure comprises an N barrier layer, a 5-drain electrode, a 6-source electrode, a 7-grid electrode, an 8-p type oxide functional layer, a 9-passivation layer, a 10-grid dielectric layer, an 11-p-GaN cap layer and a 12-contact electrode III.
Detailed Description
The present invention will be described in detail with reference to examples.
Example 1
A gallium nitride transistor structure comprises a substrate 1, wherein the substrate 1 is a Si, SiC, GaN or sapphire substrate;
a GaN-based buffer layer 2 located above the substrate 1; a GaN-based channel layer 3 located above the GaN-based buffer layer 2; in located over the GaN-based channel layer 3xAlyGa1-x-yAn N barrier layer 4, wherein x is not less than 0<1,0≤y<1, and x + y is not equal to 0;
the GaN-based buffer layer 2 is structurally composed of an AlN nucleating layer, a GaN buffer layer and an AlGaN buffer layer from bottom to top;
in is located InxAlyGa1-x-y A source electrode 6 at one end above the N barrier layer 4; the source electrode 6 is an ohmic contact metal electrode which is formed by a single layer or multiple layers of metal and InxAlyGa1-x-yThe N barrier layer 4 forms an electrode of ohmic contact;
in is located InxAlyGa1-x-y A drain electrode 5 at the other end above the N barrier layer 4; the drain electrode 5 is an ohmic contact metal electrode, and the ohmic contact metal is a single-layer or multi-layer metal and InxAlyGa1-x-yThe N barrier layer 4 forms an electrode of ohmic contact;
a gate 7 located between the source 6 and the drain 5; the grid 7 is a Schottky contact metal electrode I which is formed by single-layer or multi-layer metal and InxAlyGa1-x-yAn electrode where the N barrier layer 4 forms a schottky contact;
and a p-type oxide functional layer 8 located between the gate 7 and the drain 5; the p-type oxide functional layer 8 partially or completely covers In between the grid 7 and the drain 5xAlyGa1-x-yThe region above the N barrier layer 4; the p-type oxide functional layer 8 comprises p-NiO, p-ZnO and p-Al2O3Or a composite structure of any two or three of them.
The preparation method of the gallium nitride transistor comprises the following steps:
(1) and (3) heterojunction epitaxial growth: by passingA method of metal organic chemical vapor deposition or molecular beam epitaxy comprises growing a GaN-based buffer layer 2 on a substrate 1 of Si, SiC, GaN or sapphire, growing a GaN-based channel layer 3 on the GaN-based buffer layer 2, and growing In on the GaN-based channel layer 3xAlyGa1-x-y N barrier layer 4 of InxAlyGa1-x-yAn N/GaN heterojunction epitaxial structure;
(2) growing the p-type oxide layer: inxAlyGa1-x-yGrowing a p-type oxide film on the N barrier layer by a metal organic chemical vapor deposition or atomic layer deposition or sputtering method;
(3) p-type oxide etching: defining the region of the p-type oxide functional layer 8 by a photoetching method, and etching the p-type oxide film outside the defined range by adopting an RIE (reactive ion etching), ICP (inductively coupled plasma) or wet etching method; further, when the p-type oxide is p-NiO, wet etching is carried out by adopting sulfuric acid or hydrochloric acid; when the p-type oxide is p-ZnO, RIE or ICP etching is carried out by adopting Cl-based gas or wet etching is carried out by adopting HF and a buffer solution thereof; when the p-type oxide is p-Al2O3When in use, HCl is adopted for wet etching;
(4) device isolation: defining an active region by photoetching process, covering and protecting the active region by photoresist, and enabling In outside the active region by RIE, ICP etching or N ion implantationxAlyGa1-x-yThe N/GaN heterojunction structure fails to realize the isolation among different devices;
(5) and forming ohmic contact of a source electrode and a drain electrode: defining a source electrode 6 and a drain electrode 5 area on an active area by photoetching, depositing four metals of Ti, Al, Ni and Au in sequence by using an evaporation or sputtering method to form an ohmic contact metal film, and then forming an ohmic contact metal electrode by a stripping process; performing RTA rapid annealing process at 600-900 deg.C to combine the metal electrode with InxAlyGa1-x-yOhmic contact is formed between the N barrier layers 4;
(6) gate schottky contact formation: the gate electrode 7 region is defined on the active region by photolithography, a schottky contact metal thin film is formed by sequentially depositing three metals of Ni, Au, and Ti by using an evaporation or sputtering method, and then a schottky contact metal electrode is formed by a lift-off process.
Example 2
A gan transistor structure, which is otherwise the same as embodiment 1, except that a passivation layer 9 is further covered on the uppermost layer of the gan transistor structure; the passivation layer 9 comprises Si3N4、Al2O3、AlN、Y2O3、La2O3、Ta2O5、TiO2、HfO2、ZrO2A single-layer or multi-layer composite structure of (1).
The preparation method of the gallium nitride transistor is otherwise the same as that of the gallium nitride transistor in the embodiment 1, except that the step (6) is followed by a step of depositing the passivation layer 9, and the passivation layer 9 is deposited by using a PECVD, MOCVD, ALD or sputtering method.
Example 3
A gallium nitride transistor structure comprises a substrate 1, wherein the substrate 1 is a Si, SiC, GaN or sapphire substrate;
a GaN-based buffer layer 2 located above the substrate 1; a GaN-based channel layer 3 located above the GaN-based buffer layer 2; in located over the GaN-based channel layer 3xAlyGa1-x-yAn N barrier layer 4, wherein x is not less than 0<1,0≤y<1, and x + y is not equal to 0;
the GaN-based buffer layer 2 is structurally composed of an AlN nucleating layer, a GaN buffer layer and an AlGaN buffer layer from bottom to top;
in is located InxAlyGa1-x-y A source electrode 6 at one end above the N barrier layer 4; the source electrode 6 is an ohmic contact metal electrode which is formed by a single layer or multiple layers of metal and InxAlyGa1-x-yThe N barrier layer 4 forms an electrode of ohmic contact;
in is located InxAlyGa1-x-y A drain electrode 5 at the other end above the N barrier layer 4; the drain electrode 5 is an ohmic contact metal electrode, and the ohmic contact metal is a single-layer or multi-layer metal and InxAlyGa1-x-yThe N barrier layer 4 forms an electrode of ohmic contact;
a gate 7 located between the source 6 and the drain 5;the grid electrode 7 is an insulated grid structure electrode which is composed of grid metal, a grid dielectric layer 10 and InxAlyGa1-x-yA metal-semi-insulator-semiconductor structure formed among the N barrier layer 4; a groove etching structure is arranged below the grid 7 and comprises a part of InxAlyGa1-x-y N barrier layer 4, or In is etched entirelyxAlyGa1-x-y N barrier layer 4, or In is etched entirelyxAlyGa1-x-yEtching part of the GaN-based channel layer 3 after the N barrier layer 4 is formed; the gate dielectric layer 10 is In uncoveredxAlyGa1-x-yDepositing a gate dielectric on the surface of the N barrier layer 4; the gate dielectric comprises Si3N4、SiO2、Al2O3、AlN，HfO2、Ta2O5One or more of;
and a p-type oxide functional layer 8 located between the gate 7 and the drain 5; the p-type oxide functional layer 8 partially or completely covers In between the grid 7 and the drain 5xAlyGa1-x-yThe region above the N barrier layer 4; the p-type oxide functional layer 8 comprises p-NiO, p-ZnO and p-Al2O3Or a composite structure of any two or three of them.
The uppermost layer of the gallium nitride transistor structure is also covered with a passivation layer 9.
The preparation method of the gallium nitride transistor comprises the following steps:
(1) and (3) heterojunction epitaxial growth: growing a GaN-based buffer layer 2 on a substrate 1 of Si, SiC, GaN or sapphire, growing a GaN-based channel layer 3 on the GaN-based buffer layer 2, and growing In on the GaN-based channel layer 3 by a metal organic chemical vapor deposition or molecular beam epitaxy methodxAlyGa1-x-y N barrier layer 4 of InxAlyGa1-x-yAn N/GaN heterojunction epitaxial structure;
(2) growing the p-type oxide layer: inxAlyGa1-x-yBy metal organic chemical vapour deposition or atomic layer deposition or sputtering on the N-barrier layerThe method comprises growing a p-type oxide film;
(3) p-type oxide etching: defining the region of the p-type oxide functional layer 8 by a photoetching method, and etching the p-type oxide film outside the defined range by adopting an RIE (reactive ion etching), ICP (inductively coupled plasma) or wet etching method; further, when the p-type oxide is p-NiO, wet etching is carried out by adopting sulfuric acid or hydrochloric acid; when the p-type oxide is p-ZnO, RIE or ICP etching is carried out by adopting Cl-based gas or wet etching is carried out by adopting HF and a buffer solution thereof; when the p-type oxide is p-Al2O3When in use, HCl is adopted for wet etching;
(4) device isolation: defining an active region by photoetching process, covering and protecting the active region by photoresist, and enabling In outside the active region by RIE, ICP etching or N ion implantationxAlyGa1-x-yThe N/GaN heterojunction structure fails to realize the isolation among different devices;
(5) etching the grid groove: and forming the enhancement type GaN transistor by adopting a grid electrode groove etching method. Defining a grid electrode groove etching area through a photoetching process, using photoresist to cover and protect the area except the groove etching, and adopting Cl2/BCl3Performing RIE or ICP etching on the mixed gas; or with O2Plasma processing, oxidizing the GaN-based material, and removing the oxide layer by using dilute HCl to remove InxAlyGa1-x-yThe N barrier layer 4 is partially or entirely etched, or entirely etched InxAlyGa1-x-yEtching part of the GaN-based channel layer 3 after the N barrier layer 4;
(6) and (3) gate dielectric deposition: gate dielectric deposition using PECVD, ALD, MOCVD or sputtering methods, the gate dielectric material comprising Si3N4、SiO2、Al2O3、AlN，HfO2、Ta2O5One or more of;
(7) and forming ohmic contact of a source electrode and a drain electrode: the source electrode 6, drain electrode 5 regions are defined on the active region by photolithography, four metals of Ti, Al, Ni, Au are sequentially deposited by using an evaporation or sputtering method to form an ohmic contact metal thin film, and then by a lift-off process,forming an ohmic contact metal electrode; performing RTA rapid annealing process at 600-900 deg.C to combine the metal electrode with InxAlyGa1-x-yOhmic contact is formed between the N barrier layers 4;
(8) forming an insulated gate structure electrode: defining a grid electrode 7 area on an active area by photoetching, and sequentially depositing three metals of Ni, Au and Ti by using an evaporation or sputtering method to form a Schottky contact metal film or sputtering a metal electrode by WN and TiN;
(9) deposition of a passivation layer: depositing a passivation layer 9 using a PECVD, MOCVD, ALD or sputtering method, the passivation layer 9 comprising Si3N4、Al2O3、AlN、Y2O3、La2O3、Ta2O5、TiO2、HfO2、ZrO2One or more of (a).
Example 4
A gallium nitride transistor structure comprises a substrate 1, wherein the substrate 1 is a Si, SiC, GaN or sapphire substrate;
a GaN-based buffer layer 2 located above the substrate 1; a GaN-based channel layer 3 located above the GaN-based buffer layer 2; in located over the GaN-based channel layer 3xAlyGa1-x-yAn N barrier layer 4, wherein x is not less than 0<1,0≤y<1, and x + y is not equal to 0;
the GaN-based buffer layer 2 is structurally composed of an AlN nucleating layer, a GaN buffer layer and an AlGaN buffer layer from bottom to top;
in is located InxAlyGa1-x-y A source electrode 6 at one end above the N barrier layer 4; the source electrode 6 is an ohmic contact metal electrode which is formed by a single layer or multiple layers of metal and InxAlyGa1-x-yThe N barrier layer 4 forms an electrode of ohmic contact;
in is located InxAlyGa1-x-y A drain electrode 5 at the other end above the N barrier layer 4; the drain electrode 5 is an ohmic contact metal electrode, and the ohmic contact metal is a single-layer or multi-layer metal and InxAlyGa1-x-yThe N barrier layer 4 forms an electrode of ohmic contact;
at the source electrode 6 and the drain electrode5 between the grid 7; the gate 7 is a Schottky contact electrode II, and the Schottky contact electrode II is an electrode which forms Schottky contact between single-layer or multi-layer metal and the p-GaN cap layer 11; the p-GaN cap layer 11 is provided InxAlyGa1-x-yAbove the surface of the N-barrier layer 4,
and a p-type oxide functional layer 8 located between the gate 7 and the drain 5; the p-type oxide functional layer 8 partially or completely covers In between the grid 7 and the drain 5xAlyGa1-x-yThe region above the N barrier layer 4; the p-type oxide functional layer 8 comprises p-NiO, p-ZnO and p-Al2O3Or a composite structure of any two or three thereof; the p-type oxide functional layer 8 is interconnected with the drain electrode 5 metal electrode through a Schottky contact electrode III 12; the Schottky contact electrode III 12 is an electrode which forms Schottky contact between a single layer or multiple layers of metal and the p-type oxide functional layer 8.
The preparation method of the gallium nitride transistor comprises the following steps:
(1) and (3) heterojunction epitaxial growth: sequentially growing a GaN-based buffer layer 2 on a Si, SiC, GaN or sapphire substrate 1, growing a GaN-based channel layer 3 on the GaN-based buffer layer 2, and growing In on the GaN-based channel layer 3 by a metal organic chemical vapor deposition or molecular beam epitaxy methodxAlyGa1-x-y N barrier layer 4 of InxAlyGa1-x-yAn N/GaN heterojunction epitaxial structure; inxAlyGa1-x-yA p-GaN cap layer 11 structure grows on the N barrier layer 4 to manufacture a depletion type GaN transistor;
(2) etching the p-GaN cap layer: defining a p-GaN etching area by adopting a photoetching process, and removing a p-GaN layer outside a gate electrode area by utilizing an ICP (inductively coupled plasma), RIE (reactive ion etching) or wet etching method;
(3) growing the p-type oxide layer: inxAlyGa1-x-yGrowing a p-type oxide film on the N barrier layer 4 by a sputtering or atomic layer deposition or sputtering method;
(4) p-type oxide etching: defining the p-type oxide functional layer 8 region by photoetching process, and covering and protecting the MOS structure region by using photoresistProtecting, and removing the p-type oxide outside the structural region by adopting a RIE (reactive ion etching), ICP (inductively coupled plasma) or wet etching method; further, when the p-type oxide is p-NiO, wet etching is carried out by adopting sulfuric acid or hydrochloric acid; when the p-type oxide is p-ZnO, RIE or ICP etching is carried out by adopting Cl-based gas or wet etching is carried out by adopting HF and a buffer solution thereof; when the p-type oxide is p-Al2O3When in use, HCl is adopted for wet etching;
(5) device isolation: defining an active region by photoetching process, covering and protecting the active region by photoresist, and enabling In outside the active region by RIE, ICP etching or N ion implantationxAlyGa1-x-yThe N/GaN heterojunction structure fails to realize the isolation among different devices;
(6) and forming ohmic contact of a source electrode and a drain electrode: defining a source electrode 6 and a drain electrode 5 area on an active area by photoetching, depositing four metals of Ti, Al, Ni and Au in sequence by using an evaporation or sputtering method to form an ohmic contact metal film, and then forming an ohmic contact metal electrode by a stripping process; performing RTA rapid annealing process at 600-900 deg.C to combine the metal electrode with InxAlyGa1-x-yOhmic contact is formed between the N barrier layers 4;
(7) gate schottky contact formation: defining a grid 7 forming area through photoetching, forming a Schottky contact metal film by sequentially depositing Ti and Al metals by using an evaporation or sputtering method, and then forming a Schottky contact metal electrode through a stripping process;
(8) forming a surface electrode of the p-type oxide functional layer: an electrode forming area is defined on the surface of the p-type oxide functional layer 8 through photoetching, a surface electrode which forms Schottky contact with the p-type oxide through Ti/Al metal evaporation deposition, namely a Schottky contact electrode III, and the p-type oxide functional layer 8 is interconnected with the drain electrode 5 through a Schottky contact electrode III 12. This structure promotes the injection of holes into the GaN semiconductor by the p-type oxide when the drain 5 is applied with a large positive voltage.
The above detailed description of a gan transistor structure and a method for fabricating the same with reference to the embodiments is illustrative and not restrictive, and several embodiments may be enumerated within the scope of the limitations, so that variations and modifications thereof may be made without departing from the general inventive concept and scope thereof.

Claims (9)

1. A gallium nitride transistor structure comprising a substrate; a GaN-based buffer layer located over the substrate; a GaN-based channel layer located above the GaN-based buffer layer; in over GaN-based channel layerxAlyGa1-x-yN barrier layer of which x is not less than 0<1,0≤y<1, and x + y is not equal to 0; in is located InxAlyGa1-x-yA source electrode at one end above the N barrier layer; in is located InxAlyGa1-x-yA drain electrode at the other end above the N barrier layer; a gate electrode between the source electrode and the drain electrode; and a p-type oxide functional layer located between the gate and the drain;
the p-type oxide functional layer is interconnected with the drain metal electrode through a Schottky contact electrode III; the Schottky contact electrode III is an electrode which forms Schottky contact between a single-layer or multi-layer metal and a p-type oxide functional layer.
2. The GaN transistor structure of claim 1, wherein the p-type oxide functional layer partially or completely covers In between the gate and the drainxAlyGa1-x-yA region above the N-barrier layer.
3. The gallium nitride transistor structure of claim 1, wherein the p-type oxide functional layer comprises p-NiO, p-ZnO, or a composite thereof.
4. The GaN transistor structure of any of claims 1-3, wherein the source and drain are ohmic contact metal electrodes formed by a single layer or multiple layers of metal and InxAlyGa1-x-yThe N-barrier layer forms an electrode of ohmic contact.
5. The GaN transistor structure of any of claims 1-3, wherein the gate is a Schottky contact metal electrode I, and the Schottky contact metal electrode I is formed by a single layer or multiple layers of metal and InxAlyGa1-x-yThe N-barrier layer forms an electrode of the schottky contact.
6. The GaN transistor structure of any of claims 1-3, wherein the gate is an insulated gate structure electrode composed of a gate metal, a gate dielectric layer and InxAlyGa1-x-yAnd a metal-semi-insulator-semiconductor structure is formed among the N barrier layers.
7. Gallium nitride transistor structure according to any of claims 1-3, wherein In isxAlyGa1-x- yAnd a p-GaN cap layer is arranged above the surface of the N barrier layer, the grid is a Schottky contact electrode II, and the Schottky contact electrode II is an electrode in Schottky contact formed between single-layer or multi-layer metal and the p-GaN cap layer.
8. The GaN transistor structure of any of claims 1-3, wherein a trench etch structure is provided under the gate, the trench etch structure comprising In partially etchedxAlyGa1-x-yN barrier layer, or In is etched entirelyxAlyGa1-x-yN barrier layer, or In is etched entirelyxAlyGa1-x-yAnd etching part of the GaN-based channel layer after the N barrier layer.
9. A method for producing a gallium nitride transistor according to any one of claims 1 to 8, comprising the steps of:
(1) growing a GaN-based buffer layer on a substrate, growing a GaN-based channel layer on the GaN-based buffer layer, and growing In on the GaN-based channel layerxAlyGa1-x-yAn N barrier layer;
(2) inxAlyGa1-x-yForming a p-type oxide film above the N barrier layer, defining a p-type oxide functional layer area by a photoetching method, and etching the p-type oxide film outside the defined range;
(3) inxAlyGa1-x-yAn active region is defined on the N barrier layer;
(4) defining a source electrode area and a drain electrode area on the active area, and depositing an ohmic contact metal electrode to form a source electrode and a drain electrode;
(5) defining a grid electrode area on the active area, and depositing a Schottky contact metal electrode to form a grid electrode;
(6) and defining an electrode forming area on the surface of the p-type oxide functional layer by photoetching, forming a Schottky contact electrode III which is a surface electrode in Schottky contact with the p-type oxide by Ti/Al metal evaporation deposition, and interconnecting the p-type oxide functional layer with a drain metal electrode through the Schottky contact electrode III.
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