CN109950323B - Polarized superjunction III-nitride diode device and method of making the same - Google Patents
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Abstract
Description
技术领域technical field
本发明涉及一种二极管器件,具体涉及一种极化超结的Ⅲ族氮化物二极管器件及其制作方法,属于功率半导体技术领域。The invention relates to a diode device, in particular to a polarized superjunction III-nitride diode device and a manufacturing method thereof, belonging to the technical field of power semiconductors.
背景技术Background technique
Ⅲ族氮化物(如GaN)具有大禁带宽度、高电子迁移率、高击穿场强等优点,能够满足下一代电力电子系统对功率器件更大功率、更高频率、更小体积和更高温度的工作的要求,因此Ⅲ族氮化物制成的二极管器件成为新一代功率器件研究的热点。传统的采用肖特基金属接触的Ⅲ族氮化物二极管还面临许多问题,如开启电压大、击穿电压低和反向漏电大等。Group III nitrides (such as GaN) have the advantages of large band gap, high electron mobility, high breakdown field strength, etc., which can meet the requirements of next-generation power electronic systems for power devices with higher power, higher frequency, smaller size and more space. Due to the requirements of high temperature operation, diode devices made of group III nitrides have become a hot spot in the research of new generation power devices. Conventional III-nitride diodes using Schottky metal contacts also face many problems, such as large turn-on voltage, low breakdown voltage and large reverse leakage.
Jae-Gil Lee等采用刻蚀AlGaN势垒层的方式制备的AlGaN/GaN二极管器件,开启电压0.37V,远小于常规肖特基结构的二极管开启电压,但是反向漏电流较大(IEEEElectron Device Letters,vol.34,no.2,Feb2013)。The AlGaN/GaN diode device prepared by Jae-Gil Lee et al by etching the AlGaN barrier layer has a turn-on voltage of 0.37V, which is much lower than the turn-on voltage of a diode with a conventional Schottky structure, but the reverse leakage current is relatively large (IEEE Electron Device Letters , vol.34, no.2, Feb2013).
Silvia Lenci等采用结终端技术制备的肖特基二极管器件,反向电流得到了有效的降低,但是正向导通电流密度依然很低(IEEE ElectronDevice Letters,vol.34,no.8,Aug2013)。The Schottky diode device prepared by Silvia Lenci et al. using junction termination technology has effectively reduced the reverse current, but the forward current density is still very low (IEEE ElectronDevice Letters, vol.34, no.8, Aug2013).
周琦等提出了一种采用欧姆接触作为阳极和阴极,采用AlGaN/GaN异质结的二维电子气作为导电沟道,将靠近阳极AlGaN势垒层刻蚀一定深度,制备金属-绝缘层-半导体接触,该金属与阳极相连,从而实现正向电压开启和反向电压关断功能(CN103872145A)。该器件可以实现较低的阈值电压和导通电流密度。但是由于刻蚀AlGaN势垒层技术难度较大,刻蚀损伤较高,该器件的制备存在一定的难度。Zhou Qi et al. proposed a method using ohmic contact as anode and cathode, using two-dimensional electron gas of AlGaN/GaN heterojunction as conductive channel, and etching the AlGaN barrier layer near the anode to a certain depth to prepare a metal-insulating layer- The semiconductor contacts, the metal is connected to the anode, thereby realizing the forward voltage turn-on and reverse voltage turn-off functions (CN103872145A). The device can achieve lower threshold voltage and on-current density. However, due to the technical difficulty of etching the AlGaN barrier layer and the high etching damage, the preparation of the device has certain difficulties.
总之,现有Ⅲ族氮化物二极管还存在诸多缺陷,如开启电压大、击穿电压低和饱和电流低等,这也是本领域一直渴望解决的难题。In a word, the existing III-nitride diodes still have many defects, such as large turn-on voltage, low breakdown voltage and low saturation current, etc., which are also difficult problems that the art has been eager to solve.
发明内容SUMMARY OF THE INVENTION
本发明的主要目的在于提供一种极化超结的Ⅲ族氮化物二极管器件及制作方法,以克服现有技术的不足。The main purpose of the present invention is to provide a polarized superjunction III-nitride diode device and a fabrication method to overcome the deficiencies of the prior art.
为实现前述发明目的,本发明采用的技术方案包括:In order to realize the foregoing invention purpose, the technical scheme adopted in the present invention includes:
本发明实施例提供了一种极化超结的Ⅲ族氮化物二极管器件,其包括:An embodiment of the present invention provides a polarized superjunction III-nitride diode device, which includes:
第一异质结,其包括第一半导体和形成于第一半导体上的第二半导体,所述第二半导体具有宽于第一半导体的带隙,且所述第一异质结构中形成有二维电子气;A first heterojunction includes a first semiconductor and a second semiconductor formed on the first semiconductor, the second semiconductor has a wider band gap than the first semiconductor, and two semiconductors are formed in the first heterostructure. dimensional electronic gas;
第二异质结,其包括所述第二半导体和形成于所述第二半导体上的第三半导体,所述第三半导体具有窄于所述第二半导体的带隙,所述第二异质结中形成有二维空穴气;A second heterojunction including the second semiconductor and a third semiconductor formed on the second semiconductor, the third semiconductor having a narrower band gap than the second semiconductor, the second heterojunction A two-dimensional hole gas is formed in the junction;
第四半导体,其形成于所述第二半导体上并与第三半导体紧密连接,且能够将第一异质结中的二维电子气耗尽;a fourth semiconductor formed on the second semiconductor and in close connection with the third semiconductor and capable of depleting the two-dimensional electron gas in the first heterojunction;
阳极和阴极,其中所述阳极包括相互电连接的第一阳极和第二阳极,所述第一阳极和阴极与所述第一异质结中的二维电子气电连接,所述第二阳极与第四半导体电连接。an anode and a cathode, wherein the anode includes a first anode and a second anode electrically connected to each other, the first anode and cathode being electrically connected to two-dimensional electrons in the first heterojunction, the second anode is electrically connected to the fourth semiconductor.
优选的,所述第四半导体与第三半导体在与所述Ⅲ族氮化物二极管器件的轴线垂直的方向上紧密结合。Preferably, the fourth semiconductor and the third semiconductor are closely combined in a direction perpendicular to the axis of the group III nitride diode device.
进一步地,所述第四半导体为p型半导体。Further, the fourth semiconductor is a p-type semiconductor.
优选的,所述第二阳极与第四半导体之间形成欧姆接触或肖特基接触。Preferably, an ohmic contact or a Schottky contact is formed between the second anode and the fourth semiconductor.
优选的,所述第一阳极和阴极与第二半导体形成欧姆接触。Preferably, the first anode and the cathode form ohmic contact with the second semiconductor.
进一步地,对于本发明的Ⅲ族氮化物二极管器件,当在所述第二阳极上施加的电压大于一开启电压时,所述二极管器件处于开启状态,所述开启电压至少足以使位于第二阳极与第四半导体接触处正下方的第一异质结的局部区域内形成二维电子气并将第一阳极与阴极电连接;而当在所述第二阳极上施加的电压小于所述开启电压时,所述二极管器件处于关闭状态。Further, for the group III nitride diode device of the present invention, when the voltage applied on the second anode is greater than a turn-on voltage, the diode device is in an on state, and the turn-on voltage is at least sufficient to make the second anode A two-dimensional electron gas is formed in the local area of the first heterojunction directly below the contact with the fourth semiconductor and the first anode and the cathode are electrically connected; and when the voltage applied on the second anode is less than the turn-on voltage , the diode device is turned off.
优选的,所述阴极接地。Preferably, the cathode is grounded.
本发明实施例还提供了一种制作所述极化超结的Ⅲ族氮化物二极管器件的制作方法,其包括:在衬底上依次设置第一半导体、第二半导体和第四半导体,An embodiment of the present invention also provides a method for fabricating the group III nitride diode device of the polarized superjunction, which includes: sequentially disposing a first semiconductor, a second semiconductor and a fourth semiconductor on a substrate,
制作阳极和阴极,所述阳极包括相互电连接的第一阳极和第二阳极,并使第一阳极及阴极与所述第一异质结中的二维电子气电连接,且使第二阳极与第四半导体形成欧姆接触或肖特基接触;以及An anode and a cathode are fabricated, the anode includes a first anode and a second anode electrically connected to each other, the first anode and the cathode are electrically connected to the two-dimensional electrons in the first heterojunction, and the second anode is electrically connected forming an ohmic or Schottky contact with the fourth semiconductor; and
对分布于阳极和阴极之间的第四半导体进行掺杂处理形成第三半导体。A third semiconductor is formed by doping the fourth semiconductor distributed between the anode and the cathode.
在前述的制作方法中,至少可以通过离子注入、高温扩散和等离子体处理中的任一种方式对第四半导体进行掺杂处理,从而形成第三半导体。In the aforementioned fabrication method, the fourth semiconductor can be doped by at least any one of ion implantation, high temperature diffusion and plasma treatment, thereby forming the third semiconductor.
优选的,其中采用的掺杂元素包括F、N、Ar或H,但不限于此。Preferably, the doping element used therein includes F, N, Ar or H, but is not limited thereto.
本发明实施例还提供了一种制作所述极化超结的Ⅲ族氮化物二极管器件的制作方法,其包括:在衬底上依次设置第一半导体、第二半导体、第三半导体;An embodiment of the present invention also provides a method for manufacturing the group III nitride diode device of the polarized superjunction, which includes: sequentially arranging a first semiconductor, a second semiconductor, and a third semiconductor on a substrate;
制作第一阳极和阴极,并使第一阳极及阴极与所述第一异质结中的二维电子气电连接;fabricating a first anode and a cathode, and electrically connecting the first anode and the cathode with the two-dimensional electrons in the first heterojunction;
对靠近第一阳极一侧的第三半导体进行掺杂处理,形成第四半导体;以及Doping the third semiconductor on the side close to the first anode to form a fourth semiconductor; and
制作第二阳极,且使第二阳极与第四半导体形成欧姆接触或肖特基接触。A second anode is fabricated, and the second anode is made to form an ohmic contact or a Schottky contact with the fourth semiconductor.
在前述的制作方法中,至少可以通过离子注入及高温退火激活方式或低能电子辐射激活方式对第三半导体进行掺杂处理,从而形成第四半导体。In the aforementioned fabrication method, at least the third semiconductor can be doped by ion implantation and high temperature annealing activation mode or low energy electron radiation activation mode to form the fourth semiconductor.
优选的,其中采用的掺杂元素包括镁或锌,但不限于此。Preferably, the doping element used therein includes magnesium or zinc, but is not limited thereto.
在本发明前述的制作方法中,至少可以以金属有机化学气相沉积、分子束外延、原子层沉积、物理气相沉积和磁控溅射中的任一种方式生长形成第一半导体、第二半导体和第三半导体或第四半导体。In the aforementioned manufacturing method of the present invention, the first semiconductor, the second semiconductor and the The third semiconductor or the fourth semiconductor.
优选的,所述衬底包括氮化镓、碳化硅、硅或蓝宝石衬底,但不限于此。Preferably, the substrate includes a gallium nitride, silicon carbide, silicon or sapphire substrate, but is not limited thereto.
与现有技术相比,本发明提供的极化超结的Ⅲ族氮化物二极管器件结构简单,同时具有p型耗尽区和高阻盖帽,可以更加便捷的调整器件的开启电压,提高器件耐压和频率特性;同时第三、第四半导体可以通过工艺方式实现p型和高阻的互相转化,工艺简单,可以避免过多的刻蚀损伤,工艺窗口大,对器件的损伤小,而且工艺重复性高,成本低廉,易于进行大规模生产。Compared with the prior art, the polarized superjunction III-nitride diode device provided by the present invention has a simple structure, has a p-type depletion region and a high-resistance cap at the same time, can more conveniently adjust the turn-on voltage of the device, and improve the device resistance. voltage and frequency characteristics; at the same time, the third and fourth semiconductors can realize the mutual conversion of p-type and high resistance through the process, the process is simple, can avoid excessive etching damage, the process window is large, the damage to the device is small, and the process High reproducibility, low cost, and easy mass production.
附图说明Description of drawings
图1是本发明一典型实施例中极化超结的Ⅲ族氮化物二极管的局部结构示意图;1 is a schematic diagram of a partial structure of a group III nitride diode with a polarized superjunction in a typical embodiment of the present invention;
图2是本发明一具体实施例中一种极化超结的Ⅲ族氮化物二极管的制作工艺流程图;FIG. 2 is a flow chart of a manufacturing process of a polarized superjunction III-nitride diode according to a specific embodiment of the present invention;
图3是本发明一具体实施例中另一种极化超结的Ⅲ族氮化物二极管的制作工艺流程图;3 is a process flow diagram of another polarized superjunction III-nitride diode according to an embodiment of the present invention;
附图标记说明:衬底1、第一半导体2、第二半导体3、第四半导体4、第一阳极5、阴极6、第二阳极7、二维电子气8、第三半导体9、二维空穴气10、源极11、漏极12、栅极13。DESCRIPTION OF REFERENCE NUMERALS:
具体实施方式Detailed ways
鉴于现有技术中的不足,本案发明人经长期研究和大量实践,得以提出本发明的技术方案。如下将对该技术方案、其实施过程及原理等作进一步的解释说明。In view of the deficiencies in the prior art, the inventor of the present application was able to propose the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.
下文将对本发明的技术方案作更为详尽的解释说明。但是,应当理解,在本发明范围内,本发明的上述各技术特征和在下文(如实施例)中具体描述的各技术特征之间都可以互相组合,从而构成新的或优选的技术方案。限于篇幅,在此不再一一累述。The technical solutions of the present invention will be explained in more detail below. However, it should be understood that within the scope of the present invention, the above-mentioned technical features of the present invention and the technical features specifically described in the following (eg, the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, it is not repeated here.
本发明实施例一方面提供的一种极化超结的Ⅲ族氮化物二极管器件包括:An aspect of a polarized superjunction III-nitride diode device provided in an embodiment of the present invention includes:
第一异质结,其包括第一半导体和形成于第一半导体上的第二半导体,所述第二半导体具有宽于第一半导体的带隙,且所述第一异质结构中形成有二维电子气;A first heterojunction includes a first semiconductor and a second semiconductor formed on the first semiconductor, the second semiconductor has a wider band gap than the first semiconductor, and two semiconductors are formed in the first heterostructure. dimensional electronic gas;
第二异质结,其包括所述第二半导体和形成于所述第二半导体上的第三半导体,所述第三半导体具有窄于所述第二半导体的带隙,所述第二异质结中形成有二维空穴气;A second heterojunction comprising the second semiconductor and a third semiconductor formed on the second semiconductor, the third semiconductor having a narrower bandgap than the second semiconductor, the second heterojunction A two-dimensional hole gas is formed in the junction;
第四半导体,其形成于所述第二半导体上并与第三半导体紧密连接,且能够将第一异质结中的二维电子气耗尽;a fourth semiconductor formed on the second semiconductor and in close connection with the third semiconductor and capable of depleting the two-dimensional electron gas in the first heterojunction;
阳极和阴极,其中所述阳极包括相互电连接的第一阳极和第二阳极,所述第一阳极和阴极与所述第一异质结中的二维电子气电连接,所述第二阳极与第四半导体电连接。an anode and a cathode, wherein the anode includes a first anode and a second anode electrically connected to each other, the first anode and cathode being electrically connected to two-dimensional electrons in the first heterojunction, the second anode is electrically connected to the fourth semiconductor.
进一步地,第三半导体和第四半导体可以是一体结构的。其中第三半导体可以由第四半导体中的局部区域转变形成,或者第四半导体可以由第三半导体中的局部区域转变形成。Further, the third semiconductor and the fourth semiconductor may be of an integral structure. Wherein the third semiconductor may be formed by the transformation of a local area in the fourth semiconductor, or the fourth semiconductor may be formed by the transformation of a local area in the third semiconductor.
例如,可以将第四半导体的局部区域经过一定的处理转变为高阻的第三半导体。For example, a local area of the fourth semiconductor can be transformed into a high-resistance third semiconductor through a certain process.
进一步地,所述第一半导体、第二半导体和第三半导体的材质可以选自Ⅲ族氮化物。Further, the materials of the first semiconductor, the second semiconductor and the third semiconductor may be selected from group III nitrides.
优选的,所述第一半导体的材质包括GaN,但不限于此。Preferably, the material of the first semiconductor includes GaN, but is not limited thereto.
优选的,所述第二半导体的材质包括AlxGa(1-x)N、AlInGaN或InxAl(1-x)N,0<x≤1,但不限于此。Preferably, the material of the second semiconductor includes AlxGa (1-x) N , AlInGaN or InxAl (1-x) N, 0<x≤1, but not limited thereto.
优选的,所述第三半导体的材质包括高阻或本征GaN、高阻或本征InGaN、高阻或本征InN,或者GaO,更优选的包括高阻GaN、高阻InGaN或高阻InN,例如,所述第三半导体的材质包括掺C或掺Fe的高阻GaN、InGaN或InN,但不限于此。Preferably, the material of the third semiconductor includes high-resistance or intrinsic GaN, high-resistance or intrinsic InGaN, high-resistance or intrinsic InN, or GaO, and more preferably includes high-resistance GaN, high-resistance InGaN or high-resistance InN For example, the material of the third semiconductor includes C-doped or Fe-doped high-resistance GaN, InGaN or InN, but not limited thereto.
进一步地,所述第一半导体与第二半导体之间还可以分布有插入层。Further, an insertion layer may be distributed between the first semiconductor and the second semiconductor.
优选的,所述插入层的材质包括AlN,但不限于此。Preferably, the material of the insertion layer includes AlN, but is not limited thereto.
进一步地,所述第四半导体为p型半导体。Further, the fourth semiconductor is a p-type semiconductor.
优选的,所述第四半导体的材质包括p型的宽禁带半导体。Preferably, the material of the fourth semiconductor includes a p-type wide bandgap semiconductor.
更优选的,所述p型的宽禁带半导体包括p型的Ⅲ族氮化物,例如p-GaN或p-InGaN,但不限于此。More preferably, the p-type wide bandgap semiconductor includes p-type group III nitrides, such as p-GaN or p-InGaN, but not limited thereto.
更优选的,所述宽禁带半导体包括p-NiO,但不限于此。More preferably, the wide bandgap semiconductor includes p-NiO, but is not limited thereto.
进一步地,所述第四半导体的p型掺杂浓度和厚度足以耗尽所述第一异质结中的二维电子气。在一些实施方案中,所述第三半导体可以由第四半导体经过离子注入、高温扩散和等离子体处理中的任一种方式形成。优选的,所述离子注入、扩散或等离子体处理的元素包括氢、氟等,但不限于此。Further, the p-type doping concentration and thickness of the fourth semiconductor are sufficient to deplete the two-dimensional electron gas in the first heterojunction. In some embodiments, the third semiconductor may be formed from the fourth semiconductor by any one of ion implantation, high temperature diffusion, and plasma treatment. Preferably, the elements for ion implantation, diffusion or plasma treatment include hydrogen, fluorine, etc., but are not limited thereto.
在一些实施方案中,所述第四半导体可以由第三半导体经过离子注入和高温退火激活形成或低能电子辐射激活处理形成。优选的,注入元素可以为镁、锌等,但不限于此。In some embodiments, the fourth semiconductor may be formed from the third semiconductor by ion implantation and high temperature annealing activation or low energy electron radiation activation. Preferably, the implanted element may be magnesium, zinc, etc., but is not limited thereto.
优选的,所述所述阳极和阴极之间第三半导体至少经离子注入、等离子体处理和热扩散工艺中的任一种方式处理形成。Preferably, the third semiconductor between the anode and the cathode is formed by at least any one of ion implantation, plasma treatment and thermal diffusion process.
在一些实施方案中,所述第一阳极与第二阳极一体设置。In some embodiments, the first anode is integral with the second anode.
在一些实施方案中,所述第四半导体被第二阳极掩盖。In some embodiments, the fourth semiconductor is masked by the second anode.
更进一步地讲,所述第四半导体能够将所述第一异质结内位于第四半导体下方区域的二维电子气耗尽,使所述第一异质结内的二维电子气导电沟道断开,无法形成电流通路。Furthermore, the fourth semiconductor can deplete the two-dimensional electron gas in the region below the fourth semiconductor in the first heterojunction, so that the two-dimensional electron gas in the first heterojunction can conduct conduction channels. The channel is disconnected and no current path can be formed.
在一些实施方案中,所述第二阳极与第四半导体之间形成欧姆接触或肖特基接触。In some embodiments, an Ohmic or Schottky contact is formed between the second anode and the fourth semiconductor.
在一些实施方案中,所述第一阳极和阴极与第二半导体形成欧姆接触。In some embodiments, the first anode and cathode form ohmic contact with the second semiconductor.
进一步地,对于本发明的极化超结的Ⅲ族氮化物二极管器件,当在所述第二阳极上施加的电压大于一开启电压时,所述二极管器件处于开启状态,所述开启电压至少足以使位于第二阳极与第四半导体接触处正下方的第一异质结的局部区域内形成二维电子气并将第一阳极与阴极电连接;而当在所述第二阳极上施加的电压小于所述开启电压时,所述二极管器件处于关闭状态。优选的,所述阴极接地。Further, for the polarized superjunction III-nitride diode device of the present invention, when the voltage applied to the second anode is greater than a turn-on voltage, the diode device is in an on state, and the turn-on voltage is at least sufficient A two-dimensional electron gas is formed in the local area of the first heterojunction directly below the contact between the second anode and the fourth semiconductor and the first anode and the cathode are electrically connected; and when the voltage applied on the second anode When less than the turn-on voltage, the diode device is in an off state. Preferably, the cathode is grounded.
优选的,所述开启电压为正电压。Preferably, the turn-on voltage is a positive voltage.
在一些较为具体的实施方案中,当在所述阳极上未施加电压或施加的电压低于零电压时,所述二极管器件处于关闭状态,而当在所述阳极上施加的电压大于零电压且高于开启电压时,所述二极管器件处于开启状态。In some more specific embodiments, the diode device is in an off state when no voltage is applied on the anode or the applied voltage is below zero voltage, and when the applied voltage on the anode is greater than zero voltage and Above the turn-on voltage, the diode device is turned on.
在一些较为具体的实施方案中,当在所述阳极上施加零偏压或者没有施加偏压时,位于所述阳极正下方的第一异质结的局部区域内无二维电子气的积累,而当在所述阳极上施加的电压大于开启电压时,能够在位于所述阳极正下方的第一异质结的局部区域内形成二维电子气。In some more specific embodiments, when zero bias voltage or no bias voltage is applied on the anode, there is no accumulation of two-dimensional electron gas in the local area of the first heterojunction directly below the anode, And when the voltage applied on the anode is greater than the turn-on voltage, a two-dimensional electron gas can be formed in the local area of the first heterojunction directly under the anode.
在一些较为具体的实施方案中,当所述二极管器件开启时,所述二维电子气、二维空穴气同时存在于第一异质结、第二异质结中;当所述二极管器件处于关态时,所述二维电子气泄放到阴极并在所述第一异质结内的界面处留下正电荷,所述二维空穴气通过第四半导体泄放到阳极并在所述第二异质结内的界面处留下负电荷,所述正电荷与负电荷使所述二极管中于阳极和阴极之间形成均匀电场分布。In some specific embodiments, when the diode device is turned on, the two-dimensional electron gas and the two-dimensional hole gas simultaneously exist in the first heterojunction and the second heterojunction; when the diode device is turned on In the off state, the two-dimensional electron gas leaks to the cathode and leaves a positive charge at the interface within the first heterojunction, and the two-dimensional hole gas leaks to the anode through the fourth semiconductor and leaves a positive charge at the interface within the first heterojunction. Negative charges are left at the interface within the second heterojunction, and the positive and negative charges create a uniform electric field distribution in the diode between the anode and the cathode.
本发明提供的一种极化超结的Ⅲ族氮化物二极管器件结构简单,同时具有p型耗尽区和高阻盖帽,器件的开启电压可以被更为便捷的调整,器件耐压和频率特性亦得到了显著改善。The polarized superjunction III-nitride diode device provided by the present invention is simple in structure, has a p-type depletion region and a high resistance cap, the turn-on voltage of the device can be adjusted more conveniently, and the withstand voltage and frequency characteristics of the device can be adjusted more conveniently. also significantly improved.
本发明实施例的另一个方面提供的一种制作所述极化超结的Ⅲ族氮化物二极管器件的制作方法包括:Another aspect of the embodiments of the present invention provides a method for fabricating the polarized superjunction group III nitride diode device, comprising:
在衬底上依次设置第一半导体、第二半导体和第四半导体,A first semiconductor, a second semiconductor and a fourth semiconductor are sequentially arranged on the substrate,
制作阳极和阴极,所述阳极包括相互电连接的第一阳极和第二阳极,并使第一阳极及阴极与所述第一异质结中的二维电子气电连接,且使第二阳极与第四半导体形成欧姆接触或肖特基接触;以及An anode and a cathode are fabricated, the anode includes a first anode and a second anode electrically connected to each other, the first anode and the cathode are electrically connected to the two-dimensional electrons in the first heterojunction, and the second anode is electrically connected forming an ohmic or Schottky contact with the fourth semiconductor; and
对分布于阳极和阴极之间的第四半导体进行掺杂处理,从而形成第三半导体。Doping treatment is performed on the fourth semiconductor distributed between the anode and the cathode, thereby forming the third semiconductor.
在前述的制作方法中,至少可以通过离子注入、高温扩散和等离子体处理中的任一种方式对第四半导体的局部区域进行掺杂处理,从而形成第三半导体。In the aforementioned fabrication method, a local area of the fourth semiconductor may be doped by at least any one of ion implantation, high temperature diffusion and plasma treatment, thereby forming the third semiconductor.
优选的,其中采用的掺杂元素包括F、N、Ar或H,但不限于此。Preferably, the doping element used therein includes F, N, Ar or H, but is not limited thereto.
或者,在前述的制作方法中,也可通过高温热氧化对第四半导体进行氧化处理,从而形成第三半导体(如GaO等)。Alternatively, in the aforementioned fabrication method, the fourth semiconductor may also be oxidized by high-temperature thermal oxidation, thereby forming the third semiconductor (eg, GaO, etc.).
例如,在一些较为具体的实施方案中,可以经过离子注入、等离子体轰击和热扩散等工艺,将位于阳极和阴极之间的p型第四半导体转变成高阻第三半导体。其中采用的掺杂元素可以包括F、N、Ar、H等。For example, in some specific embodiments, the p-type fourth semiconductor located between the anode and the cathode can be transformed into a high-resistance third semiconductor through processes such as ion implantation, plasma bombardment, and thermal diffusion. The doping elements used therein may include F, N, Ar, H, and the like.
本发明实施例的另一个方面提供的一种制作所述极化超结的Ⅲ族氮化物二极管器件的制作方法包括:Another aspect of the embodiments of the present invention provides a method for fabricating the polarized superjunction group III nitride diode device, comprising:
在衬底上依次设置第一半导体、第二半导体、第三半导体;Disposing a first semiconductor, a second semiconductor, and a third semiconductor in sequence on the substrate;
制作第一阳极和阴极,并使第一阳极及阴极与所述第一异质结中的二维电子气电连接;fabricating a first anode and a cathode, and electrically connecting the first anode and the cathode with the two-dimensional electrons in the first heterojunction;
对靠近第一阳极一侧的第三半导体进行掺杂处理,形成第四半导体;Doping the third semiconductor on the side close to the first anode to form a fourth semiconductor;
制作第二阳极,且使第二阳极与第四半导体形成欧姆接触或肖特基接触。A second anode is fabricated, and the second anode is made to form an ohmic contact or a Schottky contact with the fourth semiconductor.
在前述的制作方法中,至少可以通过离子注入及高温退火激活方式或低能电子辐射激活方式对第三半导体进行掺杂处理,从而形成第四半导体。In the aforementioned fabrication method, at least the third semiconductor can be doped by ion implantation and high temperature annealing activation mode or low energy electron radiation activation mode to form the fourth semiconductor.
优选的,其中采用的掺杂元素包括镁或锌,但不限于此。Preferably, the doping element used therein includes magnesium or zinc, but is not limited thereto.
例如,在一些较为具体的实施方案中,可以将靠近阳极部分的高阻的第三半导体经过低能电子辐射激活和高温退火处理等的工艺将Mg掺杂激活,使第三半导体转变成p型半导体,即第四半导体。For example, in some specific embodiments, the high-resistance third semiconductor near the anode portion can be subjected to low-energy electron radiation activation and high-temperature annealing to activate Mg doping, so that the third semiconductor can be converted into a p-type semiconductor. , namely the fourth semiconductor.
在本发明前述的制作方法中,至少可以以金属有机化学气相沉积、分子束外延、原子层沉积、物理气相沉积和磁控溅射中的任一种方式生长形成第一半导体、第二半导体和第三半导体或第四半导体。In the aforementioned manufacturing method of the present invention, the first semiconductor, the second semiconductor and the The third semiconductor or the fourth semiconductor.
优选的,所述衬底包括氮化镓、碳化硅、硅或蓝宝石衬底,但不限于此。Preferably, the substrate includes a gallium nitride, silicon carbide, silicon or sapphire substrate, but is not limited thereto.
在本发明前述的制作方法中,可以通过干法刻蚀或湿法刻蚀工艺除去所述第三半导体或第四半导体的阳极(第一阳极)区域和阴极区域。In the aforementioned fabrication method of the present invention, the anode (first anode) region and the cathode region of the third semiconductor or the fourth semiconductor may be removed by dry etching or wet etching.
在一些更为具体的实施方案中,制作所述极化超结的Ⅲ族氮化物二极管器件的制作方法可以包括:In some more specific embodiments, the fabrication method of the polarized superjunction III-nitride diode device may include:
(1)材料生长:生长HR GaN/AlGaN/GaN/衬底的结构,在此结构中二维电子气(2DEG)和二维空穴气(2DHG)同时存在两个异质结的界面处;高阻(HR)GaN的获得方式主要通过生长GaN时掺入受主杂质Mg、Zn等(此处掺入受主杂质的GaN为未被激活的GaN)。(1) Material growth: grow the structure of HR GaN/AlGaN/GaN/substrate, in which two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) exist at the interface of two heterojunctions at the same time; High-resistance (HR) GaN is obtained mainly by doping acceptor impurities Mg, Zn, etc. when growing GaN (here, GaN doped with acceptor impurities is unactivated GaN).
(2)阳极、阴极制备:先进行图形化,再使用刻蚀设备(ICP、RIE、ECR等)刻蚀掉阳极和阴极区域的HR GaN,再通过镀膜设备(如电子书蒸发、磁控溅射、热蒸发等)在AlGaN上沉积欧姆金属,最后通过快速退火(RTA)进行合金化,实现欧姆接触电极的制备。(2) Anode and cathode preparation: first pattern, then use etching equipment (ICP, RIE, ECR, etc.) to etch away HR GaN in anode and cathode regions, and then use coating equipment (such as e-book evaporation, magnetron sputtering, etc.) ohmic metal was deposited on AlGaN, and finally alloyed by rapid annealing (RTA) to realize the preparation of ohmic contact electrodes.
(3)局部激活:制备掩模(掩模材质可为光刻胶、SiO2、氮化硅等),对阳极区域进行图形化(光刻胶为显影、其他掩模通过湿法或干法腐蚀),再以低能电子束辐射(LEEBI)方式对开窗口区域(亦可理解为没有掩模保护的区域)的HRGaN进行局部激活,使得HR GaN转变为p-GaN,低能电子束辐射的设备包括SEM(扫描电子显微镜)、电子束光刻机等可以形成低能电子束的设备。(3) Local activation: prepare a mask (the mask material can be photoresist, SiO 2 , silicon nitride, etc.), and pattern the anode region (the photoresist is developed, and other masks are wet or dry) Corrosion), and then locally activate HRGaN in the windowed area (also understood as an area without mask protection) by low-energy electron beam radiation (LEEBI), so that HR GaN is transformed into p-GaN, a device for low-energy electron beam radiation. Including SEM (scanning electron microscope), electron beam lithography machine and other equipment that can form low-energy electron beams.
(4)阳极制备:先图形化,使用镀膜设备沉积一层与p-GaN可形成欧姆接触的金属(Ni/Au、Pd/Pt/Au等),再通过剥离、退火等工艺获得欧姆接触。或使用镀膜设备沉积一层与p-GaN可形成肖特基接触的金属(Ti/Au、TiN等)再通过剥离、退火等工艺获得肖特基接触。(4) Anode preparation: first pattern, use coating equipment to deposit a layer of metal (Ni/Au, Pd/Pt/Au, etc.) that can form ohmic contact with p-GaN, and then obtain ohmic contact through peeling, annealing and other processes. Or use coating equipment to deposit a layer of metal (Ti/Au, TiN, etc.) that can form Schottky contact with p-GaN, and then obtain Schottky contact through processes such as lift-off and annealing.
在一些更为具体的实施方案中,制作所述极化超结的Ⅲ族氮化物二极管器件的制作方法也可以包括:In some more specific embodiments, the fabrication method of the polarized superjunction III-nitride diode device may also include:
(1)材料生长:生长p-GaN/AlGaN/GaN/衬底的结构,在此结构中,当p-GaN中的空穴浓度太高时,2DEG和2DHG都不存在于两个异质结的界面处。p-GaN的获得方式主要通过生长GaN时掺入受主杂质Mg、Zn等,之后再通过在生长设备(如MOCVD、MBE、PLD等)中进行退火激活获得。(1) Material growth: grow the structure of p-GaN/AlGaN/GaN/substrate, in this structure, when the hole concentration in p-GaN is too high, neither 2DEG nor 2DHG exists in the two heterojunctions at the interface. The main method of obtaining p-GaN is by doping acceptor impurities such as Mg and Zn during the growth of GaN, and then by annealing and activation in the growth equipment (such as MOCVD, MBE, PLD, etc.).
(2)阳极、阴极制备:先进行图形化,再使用刻蚀设备(ICP感应耦合等离子体、RIE反应离子刻蚀、ECR电子回旋共振等)刻蚀掉阳极和阴极区域的HR GaN,再通过镀膜设备(如电子书蒸发、磁控溅射、热蒸发等)在AlGaN上沉积欧姆金属,最后通过快速退火(RTA)进行合金化,实现欧姆电极的制备。(2) Preparation of anode and cathode: patterning is performed first, and then etching equipment (ICP inductively coupled plasma, RIE reactive ion etching, ECR electron cyclotron resonance, etc.) is used to etch away the HR GaN in the anode and cathode regions, and then pass through Coating equipment (such as e-book evaporation, magnetron sputtering, thermal evaporation, etc.) deposits ohmic metal on AlGaN, and finally performs alloying by rapid annealing (RTA) to realize the preparation of ohmic electrodes.
(3)阳极制备:先图形化,使用镀膜设备沉积一层与p-GaN可形成欧姆接触的金属(例如Ni/Au、Pd/Pt/Au等),再通过剥离、退火等工艺获得欧姆接触。或使用镀膜设备沉积一层与p-GaN可形成肖特基接触的金属(Ti/Au、TiN等)再通过剥离、退火等工艺获得肖特基接触。(3) Anode preparation: first pattern, use coating equipment to deposit a layer of metal (such as Ni/Au, Pd/Pt/Au, etc.) that can form ohmic contact with p-GaN, and then obtain ohmic contact through peeling, annealing and other processes . Or use coating equipment to deposit a layer of metal (Ti/Au, TiN, etc.) that can form Schottky contact with p-GaN, and then obtain Schottky contact through processes such as lift-off and annealing.
(4)局部钝化:利用电极或者其他绝缘层做掩模,对非电极区的p-GaN进行处理,使之转变为高阻GaN;处理的方式包括离子注入、等离子体表面钝化或者高温钝化等;其中离子注入的元素包括F、N、Ar、H等,优选的,可以在H2或NH3气氛下进行所述等离子体表面钝化或于300~800℃进行高温钝化。(4) Local passivation: Using electrodes or other insulating layers as masks, the p-GaN in the non-electrode area is processed to convert it into high-resistance GaN; the processing methods include ion implantation, plasma surface passivation or high temperature Passivation, etc.; wherein the ion implanted elements include F, N, Ar, H, etc., preferably, the plasma surface passivation can be carried out in an atmosphere of H 2 or NH 3 or high temperature passivation can be carried out at 300-800 °C.
前述衬底的材质可以是硅、蓝宝石、碳化硅、氮化镓中任意一种或多种的组合,但不限于此。本发明提供的极化超结的Ⅲ族氮化物二极管器件制备工艺简单,可以避免过多的刻蚀损伤,工艺窗口大,对器件的损伤小,重复性高,成本低廉,易于进行大规模生产。The material of the foregoing substrate may be any one or a combination of silicon, sapphire, silicon carbide, and gallium nitride, but is not limited thereto. The polarization superjunction group III nitride diode device provided by the invention has a simple preparation process, can avoid excessive etching damage, has a large process window, small damage to the device, high repeatability, low cost, and is easy to carry out large-scale production. .
以下结合附图及实施例对本发明的技术方案作进一步的解释说明。The technical solutions of the present invention will be further explained below with reference to the accompanying drawings and embodiments.
请参阅图1所示是本发明一典型实施方案中采用高阻盖帽层和p型栅技术实现的极化超结增强型二极管器件的结构示意图(以AlGaN/GaN器件为例)。这种器件可以通过在AlGaN/GaN异质结(包括作为作为第一半导体2的GaN层与作为第二半导体3的AlGaN层)上生长作为第四半导体层4的p-GaN层,再以钝化或者离子注入方式将阳极区域以外的p-GaN层4变为作为第三半导体层9的高阻GaN,第四半导体与第三半导体在水平方向上紧密连接。因此,在阳极7和阴极6之间的高阻GaN层9会与下方的AlGaN层3产生负的极化作用,在该异质结界面处会形成高浓度的二维空穴气。当器件处于关态时,阳极7和阴极6之间的电场会均匀分布,而阳极7以下区域仍然是p-GaN层4,利用p型材料可有效抬高阳极7以下的能带,使得整个器件获得增强型的性能。Please refer to FIG. 1 , which is a schematic structural diagram of a polarized superjunction enhancement diode device realized by a high-resistance cap layer and p-type gate technology in a typical embodiment of the present invention (taking an AlGaN/GaN device as an example). This device can be achieved by growing a p-GaN layer as the
类似的,材料外延时,也可以在AlGaN/GaN异质结上外延一层掺Mg的高阻的GaN层9,再以低能电子束辐射方式对阳极7以下区域进行局部激活获得p-GaN层4。在这种器件结构中,增强型的p型栅结构和极化超结的结构是一体的,既能通过p-GaN层4实现增强型,关态时也可以利用p-GaN层4对二维空穴气进行泄放,获得均匀的电场分布。同时,这种器件的工艺避免了复杂且难控制的刻蚀工艺,大大地降低了工艺难度。Similarly, for material epitaxy, a layer of Mg-doped high-
需要说明的是,HR GaN与p-GaN并不一定要通过上述的互相转化的方式形成,也可通过二次外延p-GaN、或者生长其他p型的材质,如ALD(原子层沉积)生长的p-NiO也可以代替p-GaN,在此情况下,HR GaN与p-GaN厚度也可不一样。It should be noted that HR GaN and p-GaN do not necessarily have to be formed by the above-mentioned mutual conversion, but can also be grown by secondary epitaxy of p-GaN, or growth of other p-type materials, such as ALD (atomic layer deposition) growth The p-NiO can also replace p-GaN, in this case, the thickness of HR GaN and p-GaN can also be different.
请参阅图1以及图2,本实施例涉及的一典型实施方案中采用高阻盖帽层和p型栅技术实现的极化超结的Ⅲ族氮化物二极管的一种制作方法可以包括如下步骤:Referring to FIG. 1 and FIG. 2 , a method for fabricating a polarized superjunction III-nitride diode realized by a high-resistance cap layer and a p-type gate technology in a typical implementation involved in this embodiment may include the following steps:
(1)在衬底上外延生长AlGaN/GaN外延层及p-GaN,其中GaN的厚度为1μm-8μm,AlGaN的厚度为14nm-30nm,其中Al元素的摩尔含量为15%-30%,p-GaN的厚度为50-110nm,Mg掺杂浓度为1019量级;(1) Epitaxial growth of AlGaN/GaN epitaxial layer and p-GaN on the substrate, wherein the thickness of GaN is 1 μm-8 μm, the thickness of AlGaN is 14 nm-30 nm, and the molar content of Al element is 15%-30%, p -The thickness of GaN is 50-110nm, and the Mg doping concentration is in the order of 10 19 ;
(2)采用光刻胶或者介质膜作为掩模,进行台面隔离,可以采用离子注入或等离子体刻蚀;(2) Using photoresist or dielectric film as a mask to isolate the mesa, ion implantation or plasma etching can be used;
(3)采用光刻胶作为掩模,对阳极和阴极区域进行刻蚀,刻掉p型掺杂层,之后放入电子束沉积台沉积欧姆接触金属Ti/Al/Ni/Au(20nm/130/nm/50nm/150nm)并进行剥离清洗,之后对样品进行890℃30s退火形成欧姆接触,分别为阳极和阴极;(3) Using photoresist as a mask, the anode and cathode regions are etched, the p-type doping layer is etched away, and then placed in an electron beam deposition platform to deposit ohmic contact metal Ti/Al/Ni/Au (20nm/130 /nm/50nm/150nm) and stripping and cleaning, and then annealing the samples at 890°C for 30s to form ohmic contacts, which are anode and cathode respectively;
(4)采用光刻胶作为掩模,同样利用电子束沉积Ni/Au(50/150nm)进行剥离,在氮气气氛下400℃10min退火与p型第四半导体形成欧姆接触或肖特基接触,完成阳极的制作。(4) Using photoresist as a mask, also using electron beam deposition Ni/Au (50/150nm) for stripping, annealing at 400°C for 10min under nitrogen atmosphere to form ohmic contact or Schottky contact with the p-type fourth semiconductor, Finish the production of the anode.
(5)利用阳极和阴极作为离子注入的掩模,使用离子注入机,进行离子注入(优选的,注入元素可为F、H、N等,其中离子注入能量应较低,以不进入到二维电子气沟道区为宜),使离子注入区域变为高阻区,离子注入完成后,进行400℃10min退火修复损伤,完成器件的制作。(5) Use the anode and the cathode as masks for ion implantation, and use an ion implanter to perform ion implantation (preferably, the implanted elements can be F, H, N, etc., and the ion implantation energy should be low, so as not to enter the two Dimensional electron gas channel region is suitable), so that the ion implantation area becomes a high resistance area. After the ion implantation is completed, annealing at 400° C. for 10 minutes is performed to repair the damage, and the fabrication of the device is completed.
请再次参阅图1和图3,本实施例涉及的一典型实施方案中采用高阻盖帽层和p型栅技术实现的极化超结的Ⅲ族氮化物二极管的另一种制作方法可以包括如下步骤:Referring again to FIG. 1 and FIG. 3 , another method for fabricating a group III nitride diode with a polarized superjunction realized by a high-resistance cap layer and a p-type gate technology in a typical implementation involved in this embodiment may include the following: step:
(1)在衬底上外延生长AlGaN/GaN外延层及掺Mg的未激活的高阻GaN,其中GaN的厚度为1μm-8μm,AlGaN的厚度为14nm-30nm,其中Al元素的摩尔含量为15%-30%,高阻GaN的厚度为50-110nm,Mg掺杂浓度为1019量级;(1) Epitaxial growth of AlGaN/GaN epitaxial layer and Mg-doped inactivated high-resistance GaN on the substrate, wherein the thickness of GaN is 1 μm-8 μm, the thickness of AlGaN is 14 nm-30 nm, and the molar content of Al element is 15 %-30%, the thickness of high-resistance GaN is 50-110nm, and the Mg doping concentration is in the order of 10 19 ;
(2)采用光刻胶或者介质膜作为掩模,进行台面隔离,可以采用离子注入或等离子体刻蚀;(2) Using photoresist or dielectric film as a mask to isolate the mesa, ion implantation or plasma etching can be used;
(3)采用光刻胶作为掩模,对阳极和阴极区域进行刻蚀,刻掉p型掺杂层,之后放入电子束沉积台沉积欧姆接触金属Ti/Al/Ni/Au(20nm/130/nm/50nm/150nm)并进行剥离清洗,之后对样品进行890℃30s退火形成欧姆接触,分别为阳极和阴极;(3) Using photoresist as a mask, the anode and cathode regions are etched, the p-type doping layer is etched away, and then placed in an electron beam deposition platform to deposit ohmic contact metal Ti/Al/Ni/Au (20nm/130 /nm/50nm/150nm) and stripping and cleaning, and then annealing the samples at 890°C for 30s to form ohmic contacts, which are anode and cathode respectively;
(4)光刻形成阳极区7,以低能电子束辐射的方式对阳极区域的高阻GaN进行局部的激活,使得阳极区域的高阻GaN变为p-GaN,再利用电子束沉积Ni/Au(50/150nm)进行剥离,在氮气气氛下400℃10min退火与p-GaN形成欧姆接触或肖特基接触,完成器件的制作。(4) The
前述极化超结二极管的工作原理如下:开启电压Vth为正值,当阳极电压Va<Vth时,阳极与p-GaN下的二维电子气耗尽,所以器件处于关闭状态。同时,双异质结界面处的二维电子气和二维空穴气受到反偏电压的作用分别排泄到阴极6和阳极7,留在两个异质结界面的正负电荷使得阴极6和阳极7的电场均匀分布。当阳极7加偏压达到Vg>Vth时,阳极与p-GaN下的二维电子气感生,同时双异质结界面的二维电子气和二维空穴气重新出现,使阳极5和阴极6导通,器件处于开启状态。The working principle of the aforementioned polarized superjunction diode is as follows: the turn-on voltage Vth is a positive value, and when the anode voltage Va<Vth, the two-dimensional electron gas under the anode and p-GaN is depleted, so the device is turned off. At the same time, the two-dimensional electron gas and two-dimensional hole gas at the interface of the double heterojunction are discharged to the
由于高阻GaN盖帽层和2DHG的存在,能够有效地屏蔽表面态在高频开关过程中对2DEG的捕获作用,降低电流崩塌,改善器件的动态特性。Due to the existence of the high-resistance GaN capping layer and 2DHG, the trapping effect of surface states on 2DEG during high-frequency switching can be effectively shielded, the current collapse can be reduced, and the dynamic characteristics of the device can be improved.
本发明的二极管器件结构简单,利用p-GaN阳极,可以通过电导调制效应提高电流密度,减小导通电阻,其中第三、第四半导体可以通过注入、等离子体轰击和热扩散等工艺方式而实现p型和高阻的互相转化,工艺简单,可以避免过多刻蚀损伤,成本低廉,易于进行大规模生产。需要说明的是,本发明中提及的“阳极区域,阴极区域”是指阳极和阴极正下方的区域;“非电极区域”是指“阳极和阴极以外的区域”。The diode device of the invention has a simple structure, and the p-GaN anode can be used to improve the current density and reduce the on-resistance through the conductance modulation effect. The mutual conversion between p-type and high resistance is realized, the process is simple, excessive etching damage can be avoided, the cost is low, and mass production is easy. It should be noted that the "anode region and cathode region" mentioned in the present invention refers to the region directly under the anode and the cathode; the "non-electrode region" refers to the "region other than the anode and the cathode".
应当理解,上述实施例仅为说明本发明的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施,并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰,都应涵盖在本发明的保护范围之内。It should be understood that the above-mentioned embodiments are only intended to illustrate the technical concept and characteristics of the present invention, and the purpose thereof is to enable those who are familiar with the art to understand the content of the present invention and implement it accordingly, and cannot limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be included within the protection scope of the present invention.
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