CN106206309A - Secondary epitaxy p-type nitride realizes method and enhancement mode HEMT of enhancement mode HEMT - Google Patents
Secondary epitaxy p-type nitride realizes method and enhancement mode HEMT of enhancement mode HEMT Download PDFInfo
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Abstract
The invention discloses a kind of secondary epitaxy p-type nitride and realize method and enhancement mode HEMT of enhancement mode HEMT.The method includes: provides heterojunction structure, and makes source, drain electrode on described heterojunction structure, makes source, drain electrode form Ohmic contact with heterojunction structure surface and also all be connected with the two-dimensional electron gas in heterojunction structure；The subregion that heterojunction structure is positioned at the barrier layer immediately below gate electrode (such as AlGaN layer) and n type semiconductor layer (such as i GaN layer) performs etching, and is formed and penetrates the groove in n type semiconductor layer；By this groove growing P-type quasiconductor in n type semiconductor layer, this P-type semiconductor can be formed with n type semiconductor layer when gate electrode connecting to neutral biases PN junction and when gate electrode connects forward voltage transoid and make source, drain electrode conducting；And, between source, drain electrode, make gate electrode.The present invention effectively achieves enhancement mode HEMT, and technique is simple, and repeatability is high, with low cost, it is easy to carry out large-scale production.
Description
Technical field
The present invention relates to a kind of enhancement mode HEMT (HEMT) device, particularly to one by outside secondary
Prolong p-type nitride-based semiconductor and realize the method for enhancement mode HEMT and corresponding enhancement mode HEMT, belong to microelectronic technique
Field.
Background technology
HEMT device be make full use of quasiconductor heterojunction structure formed two-dimensional electron gas and make.With III-VI race (as
AlGaAs/GaAs HEMT) to compare, III group-III nitride semiconductor is due to piezoelectric polarization and spontaneous polarization effect, at heterojunction structure
Upper (Heterostructure, such as AlGaN/GaN) can form the two-dimensional electron gas of high concentration.So using III group-III nitride
In the HEMT device made, barrier layer is typically made without doping.III group-III nitride has big energy gap, higher
The features such as saturated electron drift velocity, high critical breakdown electric field and extremely strong capability of resistance to radiation, it is possible to full power electronics of future generation
The system requirement to the work of power device greater power, higher frequency, smaller volume and higher temperature.
When existing III group-III nitride semiconductor HEMT device uses as high-frequency element or high voltage switch device, special
When not being as device for power switching, enhancement mode HEMT device is favorably improved system compared with depletion type HEMT device
Safety, the loss reducing device and simplification design circuit.Realize at present the main method of enhancement mode HEMT have thin barrier layer,
The technology such as recessed grid structure, p-type cap and F process.But all there is the deficiency of self in these technology.Such as, first in the world
Propping up enhancement mode HEMT device is to use relatively thin barrier layer to realize, and this method does not use etching technics, so bring
Damage little, but due to relatively thin barrier layer, the saturation current of device is less.F plasma treatment also can realize enhancement mode HEMT
Device, and need not etching, but the plasma of F also can etch barrier layer during injecting, and causes device performance
Reduction.P-type cap technology does not produce the ion etching impact on channel electrons, so having higher saturation current, but
It is that the typically P-type semiconductor (such as P-AlGaN, P-GaN, P-InGaN etc.) of employing etc. are using the process of dry etching
In (such as Cl2Plasma etching), barrier layer AlGaN and P-type semiconductor have the least etching selection ratio, so being difficult to control
Being etched completely by P-type semiconductor, etching stops at barrier layer AlGaN surface simultaneously.
Summary of the invention
One free-revving engine of the present invention is to propose a kind of method that secondary epitaxy p-type nitride realizes enhancement mode HEMT, from
And overcome deficiency of the prior art.
Another free-revving engine of the present invention is to provide one to have structure improved enhancement mode HEMT.
For achieving the above object, present invention employs following technical scheme:
A kind of enhancement mode HEMT, including the heterojunction structure being mainly made up of n type semiconductor layer and barrier layer and source, leakage, grid electricity
Pole, described source, drain electrode form Ohmic contact with heterojunction structure surface, with the two-dimensional electron gas in heterojunction structure even simultaneously
Connecing, described gate electrode is located between source, drain electrode, wherein, in the office of the n type semiconductor layer being positioned at immediately below described gate electrode
P-type semiconductor is distributed in region, portion, and described P-type semiconductor is completely covered by gate electrode, and when gate electrode connecting to neutral biases,
Described P-type semiconductor forms PN junction with n type semiconductor layer, and when gate electrode connects forward voltage, described P-type semiconductor is anti-
Type makes source, drain electrode conducting.
Among one more specific embodiment, described heterojunction structure is mainly by intrinsic GaN layer (i-GaN layer) and AlxGa(1-x)N
Layer composition, 0 < x≤1, and p-type GaN is distributed at the regional area of the intrinsic GaN layer being positioned at below described gate electrode,
Described p-type GaN forms PN junction with intrinsic GaN layer.
Among one more preferred embodiment, between described gate electrode and barrier layer and P-type semiconductor, it is distributed with gate medium
Layer.
Among an embodiment, described gate electrode is close source electrode side between source electrode and drain electrode.
Among an embodiment, described source electrode and drain electrode are connected with electronegative potential and the high potential of power supply respectively.
Among an embodiment, between described n type semiconductor layer and barrier layer, space layer is distributed.
In the present invention, described P-type semiconductor is completely covered by gate electrode, refers to that P-type semiconductor is all distributed in gate electrode
In orthographic projection.
A kind of method that secondary epitaxy p-type nitride realizes enhancement mode HEMT, comprising:
The heterojunction structure being mainly made up of n type semiconductor layer and barrier layer is provided, and on described heterojunction structure, makes source, electric leakage
Pole, makes source, drain electrode form Ohmic contact with heterojunction structure surface, and make source, drain electrode all electric with the two dimension in heterojunction structure
Edema of the legs during pregnancy connects；
The subregion that described heterojunction structure is positioned at the barrier layer immediately below gate electrode and n type semiconductor layer performs etching, shape
Become and penetrate the groove in n type semiconductor layer from barrier layer surface；
By described groove secondary epitaxy growing P-type quasiconductor in n type semiconductor layer, described P-type semiconductor can be at grid electricity
Form PN junction during pole connecting to neutral bias with n type semiconductor layer, and can when gate electrode connects forward voltage transoid and make source, electric leakage
Pole turns on；
And, between source, drain electrode, make gate electrode.
Among one more specific embodiment, described heterojunction structure is mainly by intrinsic GaN layer and AlxGa(1-x)N shell forms,
0 < x≤1, and p-type GaN, described p-type are distributed at the regional area of the intrinsic GaN layer being positioned at below described gate electrode
GaN forms PN junction with intrinsic GaN layer.
Among one more specific embodiment, the method that described secondary epitaxy p-type nitride realizes enhancement mode HEMT includes:
Make mask on described heterojunction structure surface, and mask is patterned process；
Use dry etch process grid lower barrierlayer and part intrinsic GaN layer are performed etching, etching depth at more than 30nm,
And, in the intrinsic GaN layer region being etched, secondary epitaxy growth thickness is p-type GaN of 30nm-70nm, institute
The doping content stating p-type GaN is 10E18cm-3To 10E19cm-3, dopant ion includes Mg2+, but it is not limited to this.
Further, need when carrying out p-type gallium nitride secondary epitaxy to make mask, can be by the mask used in etching
Realize autoregistration, and can select to use SiN or SiO2As mask, due to when epitaxial growth GaN, gallium nitride
Cannot be at SiN or SiO2Thin film is formed, it is possible to Simplified flowsheet, it is to avoid the stripping technology after secondary epitaxy on quasiconductor.
Among one more preferred embodiment, the method that described secondary epitaxy p-type nitride realizes enhancement mode HEMT is also wrapped
Include: on described barrier layer surface, groove cell wall and P-type semiconductor superficial growth gate dielectric layer, then make on described gate dielectric layer
Make gate electrode.
In the present invention, the dry etch process of employing is optional but be not limited to use plasma etch process etc..
In the present invention, for P-type semiconductor, its doping content depends on the actual application needs of device.
In the present invention, the secondary epitaxy of P-type semiconductor can select but be not limited to use MBE (molecular beam epitaxy) or
The semiconductor epitaxial equipment such as MOCVD (metal organic chemical vapor deposition).
In the present invention, the material of aforementioned gate dielectric layer can select but be not limited to SiN, SiO2And Al2O3Etc. conventional quasiconductor.
Compared with prior art, the invention have the advantages that by secondary epitaxy P-type semiconductor, utilize P-type semiconductor (example
Such as p-type gallium nitride) form the PN junction of opposition with n type semiconductor layer (such as intrinsic gallium nitride), it is achieved under zero-bias,
Device is off, and P-type semiconductor transoid can be made to realize the conducting of source, drain electrode by gate electrode, thus
Depletion type HEMT device is converted into enhancement mode HEMT device, effectively realizes enhancement mode HEMT (such as GaN HEMT),
Simultaneously the processing technology of device also have simple, reproducible, controllability is good, with low cost, it is easy to carry out large-scale production etc.
Feature.
Accompanying drawing explanation
Fig. 1 is the partial structurtes schematic diagram of common depletion type HEMT device；
Fig. 2 is the enhancement mode HEMT-structure schematic diagram using P-type semiconductor to realize in the present invention one typical embodiments；
Fig. 3 a-Fig. 3 b is energy band diagram and the ultimate principle figure realizing enhancement mode HEMT in the present invention one typical embodiments；
Description of reference numerals: substrate 1, gallium nitride layer 2, aln layer 3, barrier layer 4, p type semiconductor layer 5, gate dielectric layer
6, gate electrode 7, two-dimensional electron gas 8, source electrode 9, drain electrode 10, intrinsic gallium nitride energy band portion 11, p-type gallium nitride energy
Band portion 12, fermi level 13, PN junction 14.
Detailed description of the invention
Refering to Fig. 1, for common HEMT device (as a example by AlGaN/GaN device, be the most all called for short " device "), typically
For, when applying zero-bias at gate electrode 7 or there is no biasing, drain electrode 9 and source electrode 10 all with two-dimensional electron gas 8
Being connected, so the drain electrode 9 of device and source electrode 10 are conductings, device is in opening, and the most this device is
Depletion type HEMT device, it is also possible to be referred to as open type HEMT device.In device turn off process, gate electrode must apply
Certain back bias voltage, and institute biasing V < Vth, exhaust Two-dimensional electron under grid, in actual application process, there is merit
Problem in terms of consumption height and safety.
Refering to Fig. 2, for common enhancement mode HEMT device, when applying zero-bias at gate electrode 7 or there is no biasing
Time, owing to gate electrode 7 P-type semiconductor 5 below and intrinsic semiconductor 2 form the PN junction of an opposition, so source electrode 9
Being off with drain electrode 10, the most this device is enhancement mode HEMT device, it is also possible to be referred to as normally-off HEMT
Device.In order to make device be in opening, it is necessary to make the lower end accumulation electronics of gate electrode, it is achieved source electrode 9 and drain electrode 10
Between connection, when gate electrode 11 biasing reaches Vg > Vth time, Vth is the threshold voltage of device, for enhancement mode HEMT
The general Vth of device be on the occasion of, when the electronics that P-type semiconductor under grid is assembled makes P-type semiconductor 5 transoid, so that grid
Lower accumulation electronics, so that device is in opening.This device in side circuit application process due to only at grid 7
When applying 0 bias, device is off, and compared with depletion device, reduces the power consumption of device, and the safety of system
Higher.
The present invention passes through secondary epitaxy p-type gallium nitride, forms the PN junction structure of opposition, applies zero-bias at gate electrode or does not has
When being biased, source, drain electrode are off, when gate electrode 11 biasing reaches Vg > Vth time, Vth is device
Threshold voltage, when the electronics that P-type semiconductor under grid is assembled makes P-type semiconductor 5 transoid, so that accumulation electricity under grid
Son, so that device is in opening, it is achieved the purpose of enhancement mode HEMT device.
Refering to Fig. 2, in the present invention one typical embodiments, for realizing enhancement mode HEMT device, first make source electrode 9
With drain electrode 10, source, drain electrode form good Ohmic contact with heterojunction structure surface, and are connected with two-dimensional electron gas 8.
Then the mask needed at sample surfaces deposition-etch, optional but be not limited to SiN, SiO2Deng, then by semiconductor technology (as
Laser direct-writing, photoetching etc.) sample is patterned process, will etch is partially exposed at outside, then by etching work
AlGaN potential barrier 4 and partial nitridation gallium 2 are etched by skill, then by the method growing P-type nitride-based semiconductor of secondary epitaxy
5, the method for growth can select but be not limited to use MBE or MOCVD to grow.Then one layer is grown at sample surfaces
Gate medium 6, gate medium can select but be not limited to SiO2, SiN or Al2O3Deng semiconductive thin film.Finally deposition grid metal, shape
Become enhancement mode MISHEMT device.
It is energy band diagram and the ultimate principle figure realizing enhancement mode HEMT in the present invention one exemplary embodiments refering to Fig. 3 a-Fig. 3 b；
P-type gallium nitride 5 and the intrinsic gallium nitride 2 of secondary epitaxy form PN junction structure 14, when source-drain electrode applies voltage, always deposit
It is in reverse-biased at a PN junction, so device is in cut-off, when applying forward bias at gate electrode, carrying of device
12 part potential barriers begin to decline, break-over of device.
Embodiment refer to Fig. 2, the most on substrate 1 extension HEMT-structure, makes source electrode 9 and drain electrode 10, electricity
Pole and quasiconductor AlGaN form good Ohmic contact, are typically chosen titanium deposition/aluminum/ni au (Ti/Al/Ni/Au
The multiple layer metal such as 20nm/130nm/50nm/150nm), after metal deposit, the metal-stripping outside source-drain electrode is clean, then enter
Row short annealing (890 degrees Celsius 30 seconds), after annealing, source electrode 9 is connected with two-dimensional electron gas 8 with drain electrode 10.Then
At the mask that sample surfaces deposition-etch needs, optional but be not limited to SiN, SiO2Deng, the equipment of use can be PECVD,
ICPCVD etc., the thickness of deposition is 100nm (thickness can adjust according to reality), then by semiconductor technology (such as laser
Direct write, photoetching etc.) sample is patterned process, will etch is partially exposed at outside, then will by etching technics
AlGaN potential barrier 4 and partial nitridation gallium 2 etch, and can select ICP-RIE etching apparatus, for AlGaN in etching process
The etching of quasiconductor can select the plasma of chloro, and such as chlorine or boron chloride etc., etching depth can be 50nm, so
Afterwards by the method growing P-type nitride-based semiconductor 5 of secondary epitaxy, the method for growth can select but be not limited to use MBE or
MOCVD grows.Its thickness is about 30nm-70nm, and doping content is at 10E18cm-3To 10E19cm-3Between, tool
The doping content of body depends on that the specific design needs of device, P-type semiconductor form PN junction structure with intrinsic gallium nitride quasiconductor,
Realize device when the duty of zero gate bias, the disconnection of source-drain electrode.Then one layer of gate medium 6 is grown at sample surfaces,
Gate medium can select but be not limited to SiO2, SiN or Al2O3Deng semiconductive thin film.Finally deposition grid metal (Ni/Au
50nm/150nm), enhancement mode MISHEMT device is formed, in order to improve the performance of device, in addition it is also necessary to take some passivation sides
Formula, these modes are known to industry, so place no longer lists.
The operation principle of this HEMT is as follows: refering to Fig. 3 a-3b, in enhancement mode HEMT device, and threshold voltage vt h is just
Value, when gate voltage Vg is < during Vth, owing to the P-type semiconductor under grid and intrinsic semiconductor form PN junction structure, so source electrode
9 and drain electrode 10 be in disconnection, so device is off.As gate voltage Vg > Vth, this is that under grid, region can be amassed
Tired electronics, accumulation electronically form new communication channel, make source electrode 9 and drain electrode 10 turn on, device is in opening.
Above-described embodiment is only technology design and the feature of the explanation present invention, its object is to allow the person skilled in the art can
Understand present disclosure and implement according to this, can not limit the scope of the invention with this.All according to spirit of the invention
The equivalence change made or modification, all should contain within protection scope of the present invention.
Claims (10)
1. an enhancement mode HEMT, including the heterojunction structure being mainly made up of n type semiconductor layer and barrier layer and source, leakage, grid
Electrode, described source, drain electrode and heterojunction structure surface form Ohmic contact, simultaneously the most all with the two-dimensional electron gas in heterojunction structure
Connecting, described gate electrode is located between source, drain electrode, it is characterised in that partly lead being positioned at the N-type immediately below described gate electrode
P-type semiconductor is distributed in the regional area of body layer, and described P-type semiconductor is completely covered by gate electrode, and when gate electrode connecting to neutral
During bias, described P-type semiconductor forms PN junction with n type semiconductor layer, and when gate electrode connects forward voltage, described p-type
Quasiconductor transoid makes source, drain electrode conducting.
Enhancement mode HEMT the most according to claim 1, it is characterised in that described heterojunction structure is mainly by intrinsic GaN layer
And AlxGa(1-x)N shell forms, and 0 < x≤1, and in the regional area distribution of the intrinsic GaN layer being positioned at below described gate electrode
P-type GaN, described p-type GaN is had to form PN junction with intrinsic GaN layer.
Enhancement mode HEMT the most according to claim 1 and 2, it is characterised in that described gate electrode and barrier layer and p-type half
Gate dielectric layer it is distributed with between conductor.
Enhancement mode HEMT the most according to claim 1, it is characterised in that described gate electrode be positioned at source electrode and drain electrode it
Between near source electrode side.
Enhancement mode HEMT the most according to claim 1, it is characterised in that described source electrode and drain electrode respectively with power supply
Electronegative potential and high potential connect.
Enhancement mode HEMT the most according to claim 1, it is characterised in that divide between described n type semiconductor layer and barrier layer
It is furnished with space layer.
7. the method that a secondary epitaxy p-type nitride realizes enhancement mode HEMT, it is characterised in that including:
The heterojunction structure being mainly made up of n type semiconductor layer and barrier layer is provided, and on described heterojunction structure, makes source, electric leakage
Pole, makes source, drain electrode form Ohmic contact with heterojunction structure surface, and make source, drain electrode all electric with the two dimension in heterojunction structure
Edema of the legs during pregnancy connects；
The subregion that described heterojunction structure is positioned at the barrier layer immediately below gate electrode and n type semiconductor layer performs etching, shape
Become and penetrate the groove in n type semiconductor layer from barrier layer surface；
By described groove secondary epitaxy growing P-type quasiconductor in n type semiconductor layer, described P-type semiconductor can be at grid electricity
Form PN junction during pole connecting to neutral bias with n type semiconductor layer, and can when gate electrode connects forward voltage transoid and make source, electric leakage
Pole turns on；
And, between source, drain electrode, make gate electrode.
The method that the most according to claim 7, secondary epitaxy p-type nitride realizes enhancement mode HEMT, it is characterised in that described
Heterojunction structure is mainly by intrinsic GaN layer and AlxGa(1-x)N shell forms, and 0 < x≤1, and it is being positioned at the basis below described gate electrode
P-type GaN is distributed in levying the regional area of GaN layer, and described p-type GaN forms PN junction with intrinsic GaN layer.
The method that the most according to claim 8, secondary epitaxy p-type nitride realizes enhancement mode HEMT, it is characterised in that including:
Make mask on described heterojunction structure surface, and mask is patterned process；
Use dry etch process grid lower barrierlayer and part intrinsic GaN layer are performed etching, etching depth at more than 30nm,
And, in the intrinsic GaN layer region being etched, secondary epitaxy growth thickness is p-type GaN of 30nm-70nm, institute
The doping content stating p-type GaN is 10E18cm-3To 10E19cm-3, dopant ion includes Mg2+。
10. the method realizing enhancement mode HEMT according to secondary epitaxy p-type nitride according to any one of claim 7-9, its
It is characterised by also including: on described barrier layer surface, groove cell wall and P-type semiconductor superficial growth gate dielectric layer, then described
Gate electrode is made on gate dielectric layer.
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| CN108417493A (en) * | 2018-03-08 | 2018-08-17 | 中国科学院苏州纳米技术与纳米仿生研究所 | P-type grid enhancement transistor and preparation method thereof based on oxidation self-stopping technology technology |
| CN110875382A (en) * | 2018-08-29 | 2020-03-10 | 苏州捷芯威半导体有限公司 | Semiconductor device and method for manufacturing the same |
| CN111653618A (en) * | 2020-05-07 | 2020-09-11 | 深港产学研基地（北京大学香港科技大学深圳研修院） | Built-in PN junction silicon-based high-voltage enhanced gallium nitride transistor and manufacturing method thereof |
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