KR20140112272A - High Electron Mobility Transistor and method of manufacturing the same - Google Patents

High Electron Mobility Transistor and method of manufacturing the same Download PDF

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KR20140112272A
KR20140112272A KR1020130026804A KR20130026804A KR20140112272A KR 20140112272 A KR20140112272 A KR 20140112272A KR 1020130026804 A KR1020130026804 A KR 1020130026804A KR 20130026804 A KR20130026804 A KR 20130026804A KR 20140112272 A KR20140112272 A KR 20140112272A
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region
layer
depletion
semiconductor material
channel
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KR1020130026804A
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Korean (ko)
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박영환
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

Disclosed are a high electron mobility transistor and a method of manufacturing the same. The disclosed high electron mobility transistor includes a depletion formation region which consists of a first region which is prepared on a channel supply layer and forms a depletion region in a 2-dimensional electron gas, and a second region which is extended from the first region and is prepared between the first region and a source/drain electrode. The hole concentration of the second region is lower than that of the first region.

Description

TECHNICAL FIELD [0001] The present invention relates to a high electron mobility transistor and a method of manufacturing the same.

To a high electron mobility transistor and a manufacturing method thereof.

Various power conversion systems require a device, i.e., a power device, that controls the flow of current through on / off switching. In a power conversion system, the efficiency of a power device can influence the efficiency of the overall system.

Most of the power devices currently commercialized are silicon-based power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors). However, due to the limited physical properties of silicon and the limitations of the manufacturing process, it is becoming increasingly difficult to increase the efficiency of silicon-based power devices. In order to overcome these limitations, studies and developments are underway to increase conversion efficiency by applying III-V group compound semiconductors such as GaN to power devices. In this connection, a high electron mobility transistor (HEMT) using a heterojunction structure of a compound semiconductor has attracted attention. A high electron mobility transistor includes semiconductor layers having different polarization characteristics. In a high electron mobility transistor, a semiconductor layer having a relatively high polarization ratio can induce a two-dimensional electron gas (2DEG) to another semiconductor layer bonded to the semiconductor layer, Can have very high electron mobility.

On the other hand, when the gate voltage of the high electron mobility transistor is 0 V, current and power consumption may occur when a normally-on state in which a current flows due to a low resistance between the drain electrode and the source electrode , There is a problem that a negative voltage is applied to the gate electrode in order to turn off the current between the drain electrode and the source electrode. In order to solve these problems, a depletion layer is provided to realize a normally-off characteristic in which the current between the drain electrode and the source electrode is off when the gate voltage is 0V High electron mobility transistors are being studied.

A high electron mobility transistor and a method of manufacturing the same are provided.

In one aspect,

A channel layer comprising a first semiconductor material;

A channel supply layer including a second semiconductor material and inducing a two-dimensional electron gas (2DEG) in the channel layer;

Source and drain electrodes provided on both sides of the channel supply layer;

A first region formed on the channel supply layer and defining a depletion region in the two-dimensional electron gas; a second region extending from the first region and between the first region and the source and drain electrodes; A depletion-forming layer including a second region provided on the first region; And

And a gate electrode provided on the first region of the depletion-inducing layer,

The depletion layer includes a p-type semiconductor material, and the second region has a hole concentration lower than that of the first region.

Here, the second region may have a higher hydrogen density than the first region. The p-type semiconductor material may include Mg.

A depletion-reducing layer may be further provided on the second region to reduce or eliminate the depletion effect. The depletion-reducing layer may comprise an insulating material. The depletion-reducing layer may be formed by metal organic chemical vapor deposition (MOCVD) using a reaction gas containing hydrogen. Meanwhile, the second region may have a hole concentration lower than that of the first region by hydrogen plasma treatment.

The second region may have the same thickness as the first region or a thickness thinner than the first region. The first semiconductor material may include, for example, a GaN-based material, and the second semiconductor material may include at least one selected from among nitrides including at least one of Al, Ga, In, and B can do. The depletion-forming layer may comprise, for example, a III-V series nitride semiconductor material.

In another aspect,

Sequentially forming a channel layer and a channel supply layer on a substrate;

Forming a layer of a depletion material comprising a p-type semiconductor material on the channel supply layer;

Forming a gate electrode on the depletion material layer; And

Wherein the depletion material layer comprises a first region provided below the gate electrode and forming a depletion region in the two-dimensional electron gas, and a second region extending to the first region and having a hole concentration lower than that of the first region Forming a depletion-forming layer including a first region and a second region.

The depletion-forming layer may be formed by depositing a depletion-reducing layer that reduces or eliminates a depletion effect on the depletion layer exposed by the gate electrode. Here, the depletion-reducing layer may be formed by metal organic chemical vapor deposition (MOCVD) using a reaction gas containing hydrogen. On the other hand, the depletion-forming layer may be formed by subjecting the depletion-material layer exposed by the gate electrode to a hydrogen plasma treatment.

Etching the depletion material layer exposed by the gate electrode to a predetermined depth before forming the depletion-forming layer.

According to the embodiment, the second region of the depletion-imparting layer provided between the gate electrode and the source and drain electrodes is made to have a smaller hole concentration than the first region of the depletion-forming layer provided below the gate electrode, The effect of the seismic effect can be reduced or eliminated. Accordingly, a depletion region of the two-dimensional electron gas (2DEG) can be formed only in the channel layer portion corresponding to the first region of the depletion-forming layer below the gate electrode.

1 is a diagram illustrating a high electron mobility transistor according to an exemplary embodiment.
2 is a diagram illustrating a high electron mobility transistor according to another exemplary embodiment.
3 is a diagram illustrating a high electron mobility transistor according to another exemplary embodiment.
4 is a diagram illustrating a high electron mobility transistor according to another exemplary embodiment.
5 and 6 are views for explaining a method of manufacturing the high electron mobility transistor shown in FIG.
FIGS. 7 and 8 are views for explaining a method of manufacturing the high electron mobility transistor shown in FIG.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements, and the size and thickness of each element may be exaggerated for clarity of explanation. In addition, when it is described that a certain material layer is present on a substrate or another layer, the material layer may be present in direct contact with the substrate or another layer, and there may be another third layer in between. In addition, the materials constituting each layer in the following embodiments are illustrative, and other materials may be used.

1 is a diagram illustrating a high electron mobility transistor 100 in accordance with an exemplary embodiment.

Referring to FIG. 1, a channel layer 120 is provided on a substrate 110. The substrate 110 may include, for example, sapphire, Si, SiC or GaN. However, this is merely exemplary, and the substrate 110 may include various other materials. The channel layer 120 may comprise a first semiconductor material. Here, the first semiconductor material may be a III-V compound semiconductor material, but is not limited thereto. For example, the channel layer 120 may be a GaN-based material layer, specifically, a GaN layer. In this case, the channel layer 120 may be an undoped GaN layer, and in some cases, it may be a doped GaN layer.

Although not shown in FIG. 1, a predetermined buffer layer may be further provided between the substrate 110 and the channel layer 120. The buffer layer is provided to reduce the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the channel layer 120 to prevent the crystallinity of the channel layer 120 from deteriorating. The buffer layer includes at least one material selected from among nitrides including at least one of Al, Ga, In, and B, and may have a single layer or a multi-layer structure. The buffer layer may include at least one of materials consisting of, for example, AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN. Meanwhile, a seed layer (not shown) may be further provided between the substrate 110 and the buffer layer for growing the buffer layer.

A channel layer 130 may be formed on the channel layer 120. The channel layer 130 may induce a two-dimensional electron gas (2DEG) in the channel layer 120. Here, the two-dimensional electron gas (2DEG) may be formed in the channel layer 120 under the interface between the channel layer 112 and the channel supply layer 114. The channel layer 130 may include a second semiconductor material different from the first semiconductor material forming the channel layer 120. The second semiconductor material may have at least one of a polarization property, an energy bandgap, and a lattice constant different from that of the first semiconductor material. In particular, the second semiconductor material may have at least one of a polarization ratio and an energy band gap greater than that of the first semiconductor material. The channel supply layer 130 may include at least one selected from among nitrides including at least one of Al, Ga, In, and B, and may have a single layer or a multi-layer structure. As a specific example, the channel supply layer 130 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. However, the present invention is not limited thereto. The channel supply layer 130 may be an undoped layer, but may be a layer doped with a certain impurity.

A source electrode 161 and a drain electrode 162 may be formed on the channel layer 120 on both sides of the channel supply layer 130. Here, the source electrode 161 and the drain electrode 162 may be electrically connected to the two-dimensional electron gas (2DEG). The source electrode 161 and the drain electrode 162 may be provided on the channel supply layer 130 or may be inserted into the channel supply layer 130 or the channel layer 120 . In addition, the configurations of the source electrode 161 and the drain electrode 162 may be variously changed.

A depletion forming layer 140 may be formed on the channel supply layer between the source electrode 161 and the drain electrode 162. The depletion-forming layer 140 may include a p-type semiconductor material. That is, the depletion-forming layer 140 may be a p-type semiconductor layer or a semiconductor layer doped with a p-type impurity. In addition, the depletion-forming layer 140 may include a III-V group nitride semiconductor. For example, the depletion-forming layer 140 may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN, and may be doped with a p-type impurity such as Mg. As a specific example, the depletion-forming layer 140 may be a p-GaN layer or a p-AlGaN layer.

The depletion forming layer 140 includes a first region 141 that forms a depletion region 120a of a two-dimensional electron gas (2DEG), and a second region 141 that extends from both sides of the first region 141 And a second region 142 formed to form a two-dimensional electron gas (2DEG). The second region 142 may be provided between the first region 141 and the source electrode 161 and between the first region 141 and the drain electrode 162.

The first region 141 of the depletion forming layer 140 can increase the energy band gap of the channel supply layer 130 located below the first region 141, A depletion region 120a of a two-dimensional electron gas (2DEG) may be formed in a portion of the channel layer 120 corresponding to the first region 141. [ Therefore, the portion of the two-dimensional electron gas (2DEG) corresponding to the first region 141 of the depletion-forming layer 140 may be broken or may have a characteristic different from that of the remaining portion (for example, have. The region where the two-dimensional electron gas (2DEG) is broken may be referred to as a 'disconnect region', and the high electron mobility transistor 100 may have a normally-off characteristic.

The second region 142 of the depletion-inducing layer 140 may extend from both sides of the first region 141 and be provided between the first region 141 and the source and drain electrodes 161 and 162. The second region 142 may be thinner than the first region 141. In this embodiment, the second region 142 may have a lower hole concentration than the first region 141. The second region 142 may include a p-type impurity (for example, Mg) in the process of depositing a depletion-reducing layer 170, which will be described later, by metal organic chemical vapor deposition (MOCVD) May be formed by bonding hydrogen contained in the reaction gas. Accordingly, the second region 142 may have a higher hydrogen density and a lower hole concentration than the first region 141. In this way, when the second region 142 has a hole concentration lower than that of the first region 141, the depletion effect can be reduced or eliminated. Therefore, a two-dimensional electron gas (2DEG) having no disconnection region may be formed in the channel layer 120 corresponding to the second region 142 of the depletion-forming layer 140. A gate electrode 150 may be formed on the first region 141 of the depletion-inducing layer 140. The first gate electrode 150 may include various metal materials or metal compounds.

A depletion-reducing layer 170 may be provided on the second region 142. The depletion-reducing layer 170 may be provided between the gate electrode 150 and the source and drain electrodes 161 and 162. The depletion-reducing layer 170 may be provided to reduce or eliminate the depletion effect of the second region 142 of the depletion-forming layer 140. That is, in the process of depositing the depletion-reducing layer 170 on the second region 142 by metal-organic chemical vapor deposition (MOCVD) using a reactive gas containing hydrogen, the p-type impurity For example, Mg) and the hydrogen contained in the reaction gas. As a result, the second region 142 has higher hydrogen density and lower hole concentration than the first region 141. Therefore, a depletion region 120a of the two-dimensional electron gas (2DEG) can be formed in the channel layer 120 corresponding to the first region 141, but a depletion region 120a corresponding to the second region 142 A two-dimensional electron gas (2DEG) free from a disconnected region may be formed in the channel layer 120. This depletion-reducing layer 170 may comprise an insulating material. For example, the depletion-reducing layer 170 may comprise silicon nitride, but this is merely exemplary and may include various other insulating materials.

Conventionally, a method of forming a depletion layer only at the bottom of a gate electrode by etching to form a depletion region of a two-dimensional electron gas (2DEG) was used, but it was difficult to accurately etch only a desired portion, The carrier density in the channel layer formed at the lower portion of the etched portion is reduced. However, as in the present embodiment, the depletion-reducing layer 170 is formed between the gate electrode 150 and the source and drain electrodes 161 and 162 to form the depletion-reduction layer 170 in the second region 142 of the depletion- The depletion effect can be reduced or eliminated. The depletion region 120a of the two-dimensional electron gas (2DEG) is formed only in the portion of the channel layer 120 corresponding to the first region 141 under the gate electrode 150 in the depletion forming layer 140. [ May be formed.

FIG. 2 is a diagram illustrating a high electron mobility transistor 100 'in accordance with another exemplary embodiment. The high electron mobility transistor 200 shown in FIG. 2 is similar to that of FIG. 1 except that the second region 142 'of the depletion layer 140' has the same thickness as the first region 141 ' The configuration of the high electron mobility transistor 100 shown in FIG. Hereinafter, differences from the above embodiment will be mainly described.

2, a channel layer 120 and a channel supply layer 130 are sequentially formed on a substrate 110. A source electrode 161 is formed on the channel layer 120 on both sides of the channel supply layer 130, And a drain electrode 162 may be provided. A depletion layer 140 'may be provided on the channel supply layer 130 between the source electrode 151 and the drain electrode 152. The depletion forming layer 140 'includes a first region 141' forming a depletion region 120a of a two-dimensional electron gas (2DEG), and a first region 141 'extending from both sides of the first region 141' And a second region 142 'that is provided to form a two-dimensional electron gas (2DEG). The second region 142 'may be provided between the first region 141' and the source electrode 161 and between the first region 141 'and the drain electrode 162. Here, the first region 141 'and the second region 142' may have the same thickness.

The second region 142 'may have a higher hydrogen density and a lower hole concentration than the first region 141'. Thus, if the second region 142 'has a hole concentration lower than that of the first region 141', the depletion effect can be reduced or eliminated. Therefore, a two-dimensional electron gas (2DEG) free from a disconnected region may be formed in the channel layer 120 corresponding to the second region 142 'of the depletion-forming layer 140'. A gate electrode 150 may be provided on the first region 141 'of the depletion-inducing layer 140'. A depletion-reducing layer 170 may be provided on the second region 142 '. Accordingly, a depletion region 120a of the two-dimensional electron gas (2DEG) can be formed in the channel layer 120 corresponding to the first region 141 ', but the second region 142' A two-dimensional electron gas (2DEG) free from a disconnected region can be formed in the channel layer 120 corresponding to the channel region 120. [

3 is a diagram illustrating a high electron mobility transistor 200 according to another exemplary embodiment. Hereinafter, differences from the above embodiment will be mainly described.

Referring to FIG. 3, a channel layer 220 is provided on a substrate 210. The channel layer 220 may comprise a first semiconductor material. Here, the first semiconductor material may be a III-V compound semiconductor material, but is not limited thereto. For example, the channel layer 220 may be a GaN-based material layer, specifically, a GaN layer. In this case, the channel layer 220 may be an undoped GaN layer, and in some cases, it may be a doped GaN layer. Although not shown in FIG. 1, a predetermined buffer layer may be further provided between the substrate 210 and the channel layer 220, and a predetermined seed layer for growing a buffer layer may be interposed between the substrate 210 and the buffer layer. a seed layer (not shown) may be further provided.

A channel supply layer 230 may be provided on the channel layer 220. The channel supply layer 230 may induce a two-dimensional electron gas (2DEG) in the channel layer 220. The channel layer 230 may include a second semiconductor material different from the first semiconductor material forming the channel layer 220. The second semiconductor material may have at least one of a polarization property, an energy bandgap, and a lattice constant different from that of the first semiconductor material. The channel supply layer 230 may include at least one selected from among nitrides including at least one of Al, Ga, In and B, for example. As a specific example, the channel supply layer 230 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. However, the present invention is not limited thereto. The channel supply layer 230 may be an undoped layer, but may be a layer doped with a predetermined impurity.

A source electrode 261 and a drain electrode 262 may be formed on the channel layer 220 on both sides of the channel supply layer 230. A depletion layer 240 may be provided on the channel supply layer 230 between the source electrode 261 and the drain electrode 262. The depletion-forming layer 240 may include a p-type semiconductor material. That is, the depletion-forming layer 240 may be a p-type semiconductor layer or a semiconductor layer doped with a p-type impurity. In addition, the depletion-forming layer 240 may include a III-V group nitride semiconductor. For example, the depletion-forming layer 240 may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN, and may be doped with a p-type impurity such as Mg. As a specific example, the depletion-forming layer 240 may be a p-GaN layer or a p-AlGaN layer.

The depletion-forming layer 240 includes a first region 241 that forms a depletion region 220a of a two-dimensional electron gas (2DEG), and a second region 242 that is provided to extend from both sides of the first region 241, And a second region 242 that forms an electron gas (2DEG). The second region 242 may be provided between the first region 241 and the source electrode 261 and between the first region 241 and the drain electrode 262. The first region 241 of the depletion forming layer 240 can increase the energy band gap of the channel supply layer 230 located below the first region 241, 230, a depletion region 220a of a two-dimensional electron gas (2DEG) may be formed. Therefore, the portion corresponding to the first region 241 of the two-dimensional electron gas (2DEG) may be cut off or have a characteristic different from that of the remaining portion (for example, an electron concentration or the like). The region where the two-dimensional electron gas (2DEG) is broken may be referred to as a 'disconnecting region', and the high electron mobility transistor 200 may have a normally-off characteristic.

A second region 242 of the depletion layer 240 may extend from both sides of the first region 241 and be provided between the first region 241 and the source and drain electrodes 261 and 262 . The second region 242 may be thinner than the first region 241. In this embodiment, the second region 242 may have a lower hole concentration than the first region 241. The second region 242 can be formed by combining hydrogen and a p-type impurity (for example, Mg) through hydrogen plasma treatment, which will be described later. Accordingly, the second region 242 may have a higher hydrogen density and a lower hole concentration than the first region 241. As such, if the second region 242 has a hole concentration lower than that of the first region 241, the depletion effect can be reduced or eliminated. Therefore, a two-dimensional electron gas (2DEG) having no disconnection region may be formed in the channel layer 220 corresponding to the second region 242 of the depletion-forming layer 240. A gate electrode 250 may be provided on the first region 241 of the depletion-forming layer 240.

The second region 242 of the depletion-forming layer 240 formed between the gate electrode 250 and the source and drain electrodes 261 and 262 has a hole concentration lower than that of the first region 241 The depletion effect of the second region 242 can be reduced or eliminated. The depletion region 220a of the two-dimensional electron gas (2DEG) is formed only in the portion of the channel layer 220 corresponding to the first region 241 under the gate electrode 250 in the depletion- May be formed.

FIG. 4 is a diagram illustrating a high electron mobility transistor 200 'according to another exemplary embodiment. The high electron mobility transistor 200 'shown in FIG. 4 is similar to the high electron mobility transistor 200' except that the second region 242 'of the depletion layer 240' has the same thickness as the first region 241 ' 3 are the same as those of the high electron mobility transistor 200 shown in FIG. Hereinafter, differences from the above embodiment will be mainly described.

4, a channel layer 220 and a channel supply layer 230 are sequentially formed on a substrate 210. A source electrode 261 is formed on the channel layer 220 on both sides of the channel supply layer 230, And a drain electrode 262 may be provided. A depletion layer 240 'may be formed on the channel supply layer 230 between the source electrode 261 and the drain electrode 262. The depletion layer 240 'includes a first region 241' for forming a depletion region 220a of a two-dimensional electron gas (2DEG), and a second region 241 'extending from both sides of the first region 241' And a second region 242 'provided to form a two-dimensional electron gas (2DEG). The second region 242 'may be provided between the first region 241' and the source electrode 261 and between the first region 241 'and the drain electrode 262. Here, the first region 241 'and the second region 242' may have the same thickness.

The second region 242 'may have a higher hydrogen density and a lower hole concentration than the first region 241' by hydrogen plasma treatment. Thus, if the second region 242 'has a lower hole concentration than the first region 241', the depletion effect of the second region 242 'can be reduced or eliminated. Therefore, a two-dimensional electron gas (2DEG) free from a disconnected region can be formed in the channel layer 220 corresponding to the second region 242 'of the depletion-forming layer 240'. A gate electrode 250 may be provided on the first region 241 'of the depletion-inducing layer 240'. Therefore, although a depletion region of the two-dimensional electron gas (2DEG) can be formed in the channel layer 220 corresponding to the first region 241 ', the channel region 220 corresponding to the second region 242' In the layer 220, a two-dimensional electron gas (2DEG) having no disconnection region may be formed.

FIGS. 5 and 6 are views for explaining a method of manufacturing the high electron mobility transistor 100 shown in FIG.

Referring to FIG. 5, a channel layer 120 and a channel supply layer 130 are sequentially deposited on a substrate 110. The channel layer 120 and the channel supply layer 30 may be formed by, for example, metalorganic chemical vapor deposition (MOCVD), but are not limited thereto. The substrate 110 may include, for example, sapphire, Si, SiC or GaN, but is not limited thereto. The channel layer 120 may comprise a first semiconductor material. Here, the first semiconductor material may be a III-V compound semiconductor material, but is not limited thereto. For example, the channel layer 120 may be a GaN-based material layer, specifically, a GaN layer. In this case, the channel layer 120 may be an undoped GaN layer, and in some cases, it may be a doped GaN layer. A buffer layer (not shown) may be further formed between the substrate 110 and the channel layer 120. A seed layer may be formed between the substrate 110 and the buffer layer to grow the buffer layer. (Not shown) may be further formed.

The channel layer 130 may include a second semiconductor material for inducing a two-dimensional electron gas (2DEG) in the channel layer 120 and different from the first semiconductor material constituting the channel layer 120 . The second semiconductor material may have at least one of a polarization property, an energy band gap, and a lattice constant different from the first semiconductor material. The channel supply layer 130 may include at least one selected from among nitrides including at least one of Al, Ga, In and B, for example. As a specific example, the channel supply layer 130 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. However, the present invention is not limited thereto.

A source electrode 161 and a drain electrode 162 are formed on the channel layer 120 on both sides of the channel supply layer 130. The source electrode 161 and the drain electrode 162 may be formed in various shapes, and the forming sequence may be variously modified. A depletion material layer 140a is then deposited on the channel supply layer 130 between the source electrode 161 and the drain electrode 162 and is then deposited on the depletion material layer 140a, Electrode 150 is formed. The depletion material layer 140a may comprise a p-type semiconductor material. The depletion material layer 140a may include a III-V group nitride semiconductor. For example, the depletion material layer 140a may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN, and may be doped with a p-type impurity such as Mg. As a specific example, the depletion material layer 140a may be a p-GaN layer or a p-AlGaN layer.

Next, the depletion material layer 140a exposed by the gate electrode 150 is etched to a predetermined depth. The depletion material layer 140a is formed between the gate electrode 150 and the source and drain electrodes 161 and 162. The first region 141a is formed under the gate electrode 150, And a second region 142a. Here, the second region 142a may be formed to be thinner than the first region 141a. The channel layer 120 corresponding to the depletion material layer 140a may include a two-dimensional electron source layer 140a, since the depletion material layer 140a may increase the energy band gap of the channel supply layer 130 located below the depletion material layer 140a. Gas (2DEG) is not formed.

Referring to FIG. 6, a depletion-reducing layer 170 is deposited on a second region 142a of the depletion layer 140a. The depletion-reducing layer 170 is for reducing or eliminating the depletion effect of the second region 142a of the depletion material layer 140a provided below the depletion-material layer 140a. The depletion layer 140a is formed by depositing the depletion layer 170 on the first region 141 forming the depletion region 120a and the first region 141 forming the depletion region 120a from both sides of the first region 141. [ Can be converted into a depletion-forming layer 140 that includes an extended second region 142 that forms a two-dimensional electron gas (2DEG). The second region 142 is provided between the gate electrode 150 and the source and drain electrodes 161 and 162 so that a portion of the channel layer 120 corresponding to the second region 142 An electron gas (2DEG) can be formed. The first region 141 is provided under the gate electrode 150 and the channel region 120 corresponding to the first region 141 is doped with a two- Region 120a may be formed.

The depletion-reducing layer 170 may be deposited by metal organic chemical vapor deposition (MOCVD) using a reactive gas containing hydrogen. Here, the depletion-reducing layer 170 may include an insulating material such as silicon nitride, but is not limited thereto. In this metalorganic chemical vapor deposition (MOCVD) process, the hydrogen contained in the reaction gas and the p-type impurity (for example, Mg) contained in the second region 142a of the depletion material layer 140a are bonded A depletion forming layer 140 may be formed. Here, the second region 142 of the depletion-inducing layer 140 has a higher hydrogen density and a lower hole concentration than the first region 141, so that the depletion effect of the second region 142 is reduced or eliminated . A two-dimensional electron gas (2DEG) may be formed on the channel layer 120 corresponding to the second region 142 of the depletion-forming layer 140, A depletion region 120a of a two-dimensional electron gas (2DEG) may be formed in a portion of the channel layer 120 corresponding to the region 141. [ In the present embodiment, the second region 142 of the depletion forming layer 140 is thinner than the first region 141 by etching. However, as shown in FIG. 2, The second region 142 'of the seesion forming layer 140' may be formed to have the same thickness as that of the first region 141 '.

FIGS. 7 and 8 are views illustrating a method of manufacturing the high electron mobility transistor 200 shown in FIG. Hereinafter, differences from the above-described embodiments will be mainly described.

Referring to FIG. 7, a channel layer 220 and a channel supply layer 230 are sequentially deposited on a substrate 210. The channel layer 220 may comprise a first semiconductor material. Here, the first semiconductor material may be a III-V compound semiconductor material, but is not limited thereto. A buffer layer (not shown) may be further formed between the substrate 210 and the channel layer 220. A predetermined seed layer (not shown) may be formed between the substrate 210 and the buffer layer to grow the buffer layer. . The channel layer 230 may include a second semiconductor material for inducing a two-dimensional electron gas (2DEG) in the channel layer 220 and different from the first semiconductor material constituting the channel layer 220 .

A source electrode 261 and a drain electrode 262 are formed on the channel layer 220 on both sides of the channel supply layer 230. The source electrode 261 and the drain electrode 262 may be formed in various shapes, and the forming sequence may be variously modified. A depletion material layer 240a is then deposited on the channel supply layer 230 between the source electrode 261 and the drain electrode 262 and then a gate electrode 260 is formed on the depletion material layer 240a. Electrode 250 is formed. The depletion material layer 240a may comprise a p-type semiconductor material. The depletion material layer 240a may include a III-V group nitride semiconductor. For example, the depletion material layer 240a may include at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN, and may be doped with a p-type impurity such as Mg. As a specific example, the depletion material layer 240a may be a p-GaN layer or a p-AlGaN layer.

Next, the depletion layer 240a exposed by the gate electrode 250 is etched to a predetermined depth. Accordingly, the depletion material layer 240a is formed between the gate electrode 250 and the source and drain electrodes 261 and 262. The first region 241a is formed under the gate electrode 250, And a second area 242a. Here, the second region 242a may be formed to be thinner than the first region 241a. The channel layer 220 corresponding to the depletion material layer 240a may have a two-dimensional electron emission layer 240a, since the energy band gap of the channel layer 230 located below the depletion material layer 240a may be high. Gas (2DEG) is not formed.

 Referring to FIG. 8, the second region 242a of the depletion material layer 240a exposed by the gate electrode 250 is subjected to hydrogen plasma treatment. In this hydrogen plasma treatment process, the p-type impurity (for example, Mg) contained in the second region 242a of the hydrogen and the depletion material layer 240a is bonded. Accordingly, the depletion material layer 240a may include a first region 241 forming a depletion region 220a and a second region 242 extending from both sides of the first region 241 to form a two-dimensional electron gas (2DEG) To a depletion-forming layer 240 that includes a second region 242 that forms the second region 242. The second region 242 of the depletion layer 240 has a higher hydrogen density and a lower hole concentration than the first region 241 to reduce or eliminate the depletion effect of the second region 242. [ . Therefore, a two-dimensional electron gas (2DEG) may be formed in a portion of the channel layer 220 corresponding to the second region 242 of the depletion-forming layer 240. [ A depletion region 220a of a two-dimensional electron gas (2DEG) may be formed in a portion of the channel layer 220 corresponding to the first region 241 of the depletion-forming layer 240. The second region 242 of the depletion forming layer 240 is formed to be thinner than the first region 241 by etching. However, as shown in FIG. 2, The second region 242 'of the first region 240' may be formed to have the same thickness as that of the first region 241 '.

While the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

110, 210 ... substrate 120, 220 ... channel layer
130, 230 ... channel supply layer 140, 240 ... depletion layer
141, 241 .. First area 142, 242 ... Second area
150, 250 ... gate electrode 161, 261 ... source electrode
162,

Claims (21)

A channel layer comprising a first semiconductor material;
A channel supply layer including a second semiconductor material and inducing a two-dimensional electron gas (2DEG) in the channel layer;
Source and drain electrodes provided on both sides of the channel supply layer;
A first region formed on the channel supply layer and defining a depletion region in the two-dimensional electron gas; a first region extending from the first region and between the first region and the source and drain electrodes; A depletion-forming layer including a second region provided on the first region; And
And a gate electrode provided on the first region of the depletion-inducing layer,
Wherein the depletion layer comprises a p-type semiconductor material, and the second region has a hole concentration lower than the first region. The method according to claim 1,
Wherein the second region has a higher hydrogen density than the first region. 3. The method of claim 2,
Wherein the p-type semiconductor material comprises Mg. The method according to claim 1,
And a depletion-reducing layer is further provided on the second region for reducing or eliminating a depletion effect. 5. The method of claim 4,
Wherein the depletion-reducing layer comprises an insulating material. 5. The method of claim 4,
Wherein the depletion-reducing layer is formed by Metal-Organic Chemical Vapor Deposition (MOCVD) using a reaction gas containing hydrogen. The method according to claim 1,
Wherein the second region has a lower hole concentration than the first region by hydrogen plasma treatment. The method according to claim 1,
Wherein the second region has the same thickness as the first region or a thickness thinner than the first region. The method according to claim 1,
Wherein the first semiconductor material comprises a GaN-based material. The method according to claim 1,
Wherein the second semiconductor material comprises at least one selected from among nitrides including at least one of Al, Ga, In, The method according to claim 1,
Wherein the depletion layer comprises a Group III-V nitride semiconductor material. Sequentially forming a channel layer and a channel supply layer on a substrate;
Forming a layer of a depletion material comprising a p-type semiconductor material on the channel supply layer;
Forming a gate electrode on the depletion material layer; And
Wherein the depletion material layer comprises a first region provided below the gate electrode and forming a depletion region in the two-dimensional electron gas, and a second region extending to the first region and having a hole concentration lower than that of the first region Forming a depletion layer including a first region and a second region. 13. The method of claim 12,
Wherein the second region is formed to have a higher hydrogen density than the first region. 13. The method of claim 12,
Wherein the p-type semiconductor material comprises Mg. 13. The method of claim 12,
Wherein the depletion layer is formed by depositing a depletion-reducing layer that reduces or eliminates a depletion effect on the depletion material layer exposed by the gate electrode. 16. The method of claim 15,
Wherein the depletion-reducing layer is formed by metal organic chemical vapor deposition (MOCVD) using a reaction gas containing hydrogen. 13. The method of claim 12,
Wherein the depletion layer is formed by hydrogen plasma treatment of the depletion material layer exposed by the gate electrode. 13. The method of claim 12,
Further comprising etching the depletion material layer exposed by the gate electrode to a predetermined depth before forming the depletion-forming layer. 13. The method of claim 12,
Wherein the first semiconductor material comprises a GaN-based material. 13. The method of claim 12,
Wherein the second semiconductor material comprises at least one selected from among nitrides including at least one of Al, Ga, In, and B. < Desc / Clms Page number 20 > 13. The method of claim 12,
Wherein the depletion layer comprises a Group III-V nitride semiconductor material.
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CN108305834A (en) * 2018-01-11 2018-07-20 北京华碳科技有限责任公司 A kind of preparation method of enhancement type gallium nitride fieldtron
CN108365008A (en) * 2018-01-11 2018-08-03 北京华碳科技有限责任公司 Has the preparation method of p-type two-dimensional material grid enhancement type gallium nitride fieldtron
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108305834A (en) * 2018-01-11 2018-07-20 北京华碳科技有限责任公司 A kind of preparation method of enhancement type gallium nitride fieldtron
CN108365008A (en) * 2018-01-11 2018-08-03 北京华碳科技有限责任公司 Has the preparation method of p-type two-dimensional material grid enhancement type gallium nitride fieldtron
CN108365008B (en) * 2018-01-11 2020-12-04 北京华碳科技有限责任公司 Preparation method of enhanced gallium nitride field effect device with P-type two-dimensional material grid
CN108305834B (en) * 2018-01-11 2021-02-19 北京华碳科技有限责任公司 Preparation method of enhanced gallium nitride field effect device
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