KR20150065005A - Normally off high electron mobility transistor - Google Patents

Abstract

Disclosed is a normally off high electron mobility transistor. The disclosed normally off high electron transistor includes a channel layer which is composed of a first nitride semiconductor, a channel supply layer which is composed of a second nitride semiconductor on the channel layer and induces a 2D electron gas on the channel layer, a source electrode and a drain electrode which are formed on both sides of the channel supply layer, a depletion forming layer which forms a depletion region on the at least partial region of the 2D electron gas on the channel supply layer, and a gate electrode which is in contact with the depletion forming layer and has a plurality of opening parts on the depletion layer.

Description

[0001] Normally off high electron mobility transistors [0003]

To a normally off, high electron mobility transistor, and more particularly to a normally off high electron mobility transistor including a gate electrode having a plurality of openings formed on a depletion forming layer.

Various power conversion systems require a device, i.e., a power device, that controls the flow of current through on / off switching. In a power conversion system, the efficiency of a power device can influence the efficiency of the overall system.

Most of the power devices currently commercialized are silicon-based power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors). However, due to the limited physical properties of silicon and the limitations of the manufacturing process, it is becoming increasingly difficult to increase the efficiency of silicon-based power devices. In order to overcome these limitations, studies and developments are underway to increase conversion efficiency by applying III-V group compound semiconductors to power devices. In this connection, a high electron mobility transistor (HEMT) using a heterojunction structure of a compound semiconductor has attracted attention.

A high electron mobility transistor includes semiconductor layers having different polarization characteristics. In a high electron mobility transistor, a semiconductor layer having a relatively high polarization ratio can induce a two-dimensional electron gas (2DEG) to another semiconductor layer bonded to the semiconductor layer, Can have very high electron mobility.

In a high electron mobility transistor, when the gate voltage is 0V, a power consumption may occur when the current becomes a normally-on state due to a low resistance between the drain electrode and the source electrode. A depletion-forming layer is provided in order to turn off the current between the drain electrode and the source electrode so that the current between the drain electrode and the source electrode when the gate voltage is 0 V is normally off- Off) characteristics of a high electron mobility transistor.

However, a normally off high electron mobility transistor using a depletion layer can increase gate leakage current upon turn-on.

An embodiment of the present invention provides a normally-off high electron mobility transistor with a reduced gate leakage current by disposing a gate electrode with a reduced contact area between the depletion-mode-forming layer and the gate electrode.

A normally-off high electron mobility transistor having a patterned gate electrode according to one embodiment comprises:

A channel layer made of a first nitride semiconductor;

A channel supply layer made of a second nitride semiconductor on the channel layer and inducing two-dimensional electron gas in the channel layer;

Source and drain electrodes on both sides of the channel supply layer;

A depletion forming layer forming a depletion region in at least a part of the two-dimensional electron gas on the channel supply layer; And

And a gate electrode in contact with the depletion-forming layer on the depletion-forming layer and having a plurality of openings.

The opening ratio of the plurality of openings may be 20% to 80%.

The plurality of openings may be formed to be evenly dispersed in the gate electrode.

The gate electrode may be formed at substantially the same position as the depletion-forming layer in plan view.

The plurality of openings may be a plurality of slits formed in parallel to the direction of the drain electrode from the source electrode.

According to one aspect, the deformation-forming layer includes a first portion having a first thickness and a second portion having a second thickness on either side of the first portion,

The gate electrode may be formed on the first portion.

The first thickness may be thicker than the second thickness.

The second portion may be spaced apart from the source electrode and the drain electrode.

The depletion region may be formed under the first portion and the lower portion of the second portion may be a region having a lower electron concentration of the two-dimensional electron gas than a region without the depletion-forming layer.

The first nitride semiconductor may be made of a GaN-based material.

The second nitride semiconductor may be at least one selected from among nitrides including at least one of Al, Ga, In, and B.

The depletion-forming layer may be formed of a p-type nitride semiconductor.

The depletion-forming layer may be made of a III-V group nitride semiconductor material.

In the normally off high electron mobility transistor according to the embodiment of the present invention, the gate electrode region contacting the depletion-forming layer is reduced, so that the gate leakage current is reduced upon turning on.

1 is a cross-sectional view schematically illustrating the structure of a normally off high electron mobility transistor according to an embodiment of the present invention.
FIG. 2 is a view showing an example of the plan view of FIG. 1. FIG.
3 is a graph showing the leakage current of the gate electrode according to the aperture ratio of the gate electrode of the normally off high electron mobility transistor according to an embodiment.
Fig. 4 is a view showing another example of the plan view of Fig. 1. Fig.
5 is a cross-sectional view schematically showing the structure of a normally-off high electron mobility transistor according to another embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of the layers or regions shown in the figures are exaggerated for clarity of the description. The same reference numerals are used for substantially the same components throughout the specification and the detailed description is omitted.

1 is a cross-sectional view schematically illustrating the structure of a normally off high electron mobility transistor 100 according to an embodiment of the present invention.

Referring to FIG. 1, a channel layer 120 is formed on a substrate 110. The substrate 110 may be made of, for example, sapphire, Si, SiC or GaN. However, this is merely exemplary, and the substrate 110 may be made of various other materials as well.

The channel layer 120 may comprise a first nitride semiconductor material. The first nitride semiconductor material may be a III-V system compound semiconductor material. For example, the channel layer 120 may be a GaN-based material layer. As a specific example, the channel layer 110 may be a GaN layer. In this case, the channel layer 110 may be an undoped GaN layer, and in some cases, a predetermined impurity may be a doped GaN layer.

Although not shown in the figure, a buffer layer may be further provided between the substrate 110 and the channel layer 120. The buffer layer is intended to mitigate the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the channel layer 120 to prevent deterioration of the crystallinity of the channel layer 120. The buffer layer includes a nitride including at least one of Al, Ga, In, and B, and may have a single layer or a multi-layer structure. The buffer layer may be made of, for example, AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN. A seed layer (not shown) for growing a buffer layer may be further provided between the substrate 110 and the buffer layer.

 A channel supply layer 130 may be formed on the channel layer 120. The channel supply layer 130 may induce a two-dimensional electron gas (2DEG) in the channel layer 120. A two-dimensional electron gas (2DEG) may be formed in the channel layer 120 below the interface between the channel layer 120 and the channel supply layer 130.

The channel supply layer 130 may be formed of a second nitride semiconductor material different from the first nitride semiconductor material constituting the channel layer 120. The second semiconductor material may differ from the first nitride semiconductor material by at least one of a polarization property, an energy bandgap, and a lattice constant. In particular, the second nitride semiconductor material may have at least one of a polarization factor and an energy band gap greater than the first nitride semiconductor material than the first nitride semiconductor material.

 The channel supply layer 130 may be made of a nitride including at least one of Al, Ga, In, and B, and may have a single layer or a multi-layer structure. As a specific example, the channel supply layer 130 may be made of AlGaN, AlInN, InGaN, AlN and AlInGaN. The channel feed layer 130 may be an undoped layer, but may also be a layer doped with certain impurities. The thickness of the channel supply layer 130 may be, for example, several tens nm or less. For example, the thickness of the channel supply layer 130 may be about 50 nm or less, but is not limited thereto.

 A source electrode 141 and a drain electrode 142 may be formed on the channel layer 120 on both sides of the channel supply layer 130. The source electrode 141 and the drain electrode 142 may be electrically connected to the two-dimensional electron gas (2DEG). The source electrode 141 and the drain electrode 142 may be formed on the channel supply layer 130. [ As shown in FIG. 1, the source electrode 141 and the drain electrode 142 may be formed to be inserted into the channel layer 120. The configuration of the source electrode 141 and the drain electrode 142 may be variously changed.

 A depletion forming layer 150 may be provided on the channel supply layer 130. The depletion-forming layer 150 may be formed so as to be spaced apart from the source electrode 141 and the drain electrode 142. The depletion-forming layer 150 may be formed closer to the source electrode 141 than the drain electrode 142 to which a high voltage is applied.

The depletion-forming layer 150 may serve to form a depletion region in the two-dimensional electron gas (2DEG). The energy bandgap of the portion of the channel supply layer 130 located below the depletion forming layer 150 can be increased and as a result the channel layer 120 corresponding to the depletion forming layer 150 ) Portion of the two-dimensional electron gas (2DEG) can be formed. Therefore, a portion corresponding to the depletion-forming layer 150 in the two-dimensional electron gas (2DEG) can be broken.

The region where the two-dimensional electron gas (2DEG) is broken can be referred to as a 'disconnecting region D'. By the disconnecting region D, the high electron mobility transistor 100 has a normally- Lt; / RTI >

The depletion-forming layer 150 may comprise a p-type semiconductor material. That is, the depletion-forming layer 150 may be a p-type semiconductor layer or a semiconductor layer doped with a p-type impurity. Further, the depletion-forming layer 150 may be formed of a III-V group nitride semiconductor. For example, the depletion-forming layer 150 may be made of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN, and may be doped with a p-type impurity such as Mg. As a specific example, the depletion-forming layer 150 may be a p-GaN layer or a p-AlGaN layer. The depletion layer 150 of the two-dimensional electron gas (2DEG) can be formed while the energy band gap of the channel supply layer 130 below the depletion layer 150 is increased.

A gate electrode 160 may be formed on the depletion-forming layer 150. The gate electrode 160 may be formed at substantially the same position as the depletion-forming layer 150 in plan view. A plurality of openings 162 are formed in the gate electrode 160. The plurality of openings 162 may be formed so as to be evenly distributed in the gate electrode 160. The opening 162 reduces the contact area between the depletion-forming layer 150 and the gate electrode 160. Accordingly, the amount of leakage of the voltage applied to the gate electrode 160 through the depletion layer 150 and the channel supply layer 130 can be reduced. The opening ratio in the gate electrode 160 may be approximately 20 to 80%.

The gate electrode 160 may be formed of a common metal. The gate electrode 160 may be a Schottky contact material with the depletion-forming layer 150. The gate electrode 160 may be formed of Al, Nd, Cr, Cu, Ta, Ti, Mo, W, or the like. The gate electrode 160 may be formed to a thickness of approximately several tens to several hundreds nm.

When a voltage equal to or higher than the threshold voltage is applied to the gate electrode 160, a two-dimensional electron gas (2DEG) is generated in the disconnecting region (D), and the high mobility transistor (100) is turned on. Current flows through the two-dimensional electron gas (2DEG) formed in the channel layer 120 as the channel formed below the gate electrode 160 is turned on. The threshold voltage may vary depending on the thickness of the first portion 151 of the depletion-forming layer 150 and the doping concentration of the first portion 151.

FIG. 2 is a view showing an example of the plan view of FIG. 1. FIG. The same reference numerals are used for components substantially the same as those of FIG. 1, and a detailed description thereof will be omitted.

Referring to FIG. 2, the depletion-forming layer 150 is formed so as to be spaced apart from the source electrode 141 and the drain electrode 142. The gate electrode is formed only on the depletion-forming layer 150, and a plurality of openings 162 are formed in a constant pattern. The gate electrode 160 may be disposed at substantially the same position and the same area as the depletion-imparting layer in a plan view. The plurality of openings 162 have a slit shape. A plurality of openings 162 may be formed in the gate electrode 160 evenly dispersed. The plurality of openings 162 are formed in parallel to the direction of the drain electrode 142 from the source electrode 141 so that the 2DEG between the source electrode 141 and the drain electrode 142 does not interfere with the flow of electrons have. The present embodiment is not limited to this. For example, the opening 162 may have various shapes such as a circular shape.

3 is a graph showing the leakage current of the gate electrode according to the aperture ratio of the gate electrode of the normally-off high electron mobility transistor 100 according to an embodiment.

Referring to FIG. 3, when the aperture ratio is 20%, the leakage current of the gate electrode is reduced to 50% or less, and the leakage current of the gate electrode is decreased as the aperture ratio is increased. When the aperture ratio is 80%, the leakage current is reduced by about 90%. The current is concentrated on the edge of the opening portion 162 when the gate voltage of the gate electrode 160 is applied even when the opening portion 162 is formed in the gate electrode 160. As a result, As a result, the current flows in the 2DEG.

On the other hand, if the aperture ratio is less than 20%, the decrease in the leakage current may be small. If the opening ratio is larger than 80%, electrons may not be sufficiently collected in the depletion region of the 2DEG corresponding to the region where the opening 160 is formed, thereby decreasing the controllability of the gate electrode, The gate voltage may increase.

Fig. 4 is a view showing another example of the plan view of Fig. 1. Fig.

Referring to FIG. 4, a plurality of openings 162 'are formed in a predetermined pattern. The plurality of openings 162 'may have a shape with one side opened. The plurality of openings 162 'have a slit shape. The plurality of openings 162 'are formed in parallel to the direction of the drain electrode 142 from the source electrode 141 so as not to interfere with the flow of electrons in the 2DEG between the source electrode 141 and the drain electrode 142 . The present embodiment is not limited to this. For example, the opening 162 'may have various shapes such as a circular shape.

5 is a cross-sectional view schematically illustrating the structure of a normally off high electron mobility transistor 200 according to another embodiment.

Referring to FIG. 5, a channel layer 220 is formed on a substrate 210. The substrate 210 may be made of, for example, sapphire, Si, SiC or GaN. However, this is merely exemplary, and the substrate 210 may be made of various other materials as well.

The channel layer 220 may comprise a first nitride semiconductor material. The first nitride semiconductor material may be a III-V system compound semiconductor material. For example, the channel layer 220 may be a GaN-based material layer. As a specific example, the channel layer 210 may be a GaN layer. In this case, the channel layer 210 may be an undoped GaN layer and, in some cases, a doped GaN layer.

Although not shown in the figure, a buffer layer may be further provided between the substrate 210 and the channel layer 220. The buffer layer is intended to mitigate the difference in lattice constant and thermal expansion coefficient between the substrate 210 and the channel layer 220 to prevent deterioration of the crystallinity of the channel layer 220. The buffer layer includes a nitride including at least one of Al, Ga, In, and B, and may have a single layer or a multi-layer structure. The buffer layer may be made of, for example, AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN. A seed layer (not shown) may be further provided between the substrate 210 and the buffer layer for growing the buffer layer.

 A channel supply layer 230 may be formed on the channel layer 220. The channel supply layer 230 may induce a two-dimensional electron gas (2DEG) in the channel layer 220. A two-dimensional electron gas (2DEG) may be formed in the channel layer 220 below the interface between the channel layer 220 and the channel supply layer 230.

The channel supply layer 230 may be formed of a second nitride semiconductor material different from the first nitride semiconductor material constituting the channel layer 220. The second semiconductor material may differ from the first nitride semiconductor material by at least one of a polarization property, an energy bandgap, and a lattice constant. In particular, the second nitride semiconductor material may have at least one of a polarization factor and an energy band gap greater than the first nitride semiconductor material than the first nitride semiconductor material.

 The channel supply layer 230 may be composed of, for example, a nitride including at least one of Al, Ga, In, and B, and may have a single layer or a multi-layer structure. As a specific example, the channel supply layer 230 may be made of AlGaN, AlInN, InGaN, AlN and AlInGaN. The channel feed layer 230 may be an undoped layer, but may also be a layer doped with certain impurities. The thickness of the channel supply layer 230 may be, for example, several tens nm or less. For example, the thickness of the channel supply layer 230 may be about 50 nm or less, but is not limited thereto.

 A source electrode 241 and a drain electrode 242 may be formed on the channel layer 220 on both sides of the channel supply layer 230. The source electrode 241 and the drain electrode 242 may be electrically connected to the two-dimensional electron gas (2DEG). The source electrode 241 and the drain electrode 242 may be formed on the channel supply layer 230. As shown in FIG. 1, the source electrode 241 and the drain electrode 242 may be formed to be inserted into the channel layer 220. The configuration of the source electrode 241 and the drain electrode 242 may be variously changed.

 A depletion forming layer 250 may be provided on the channel supply layer 230. The depletion layer 250 includes a first portion 251 having a first thickness T1 and a second portion 252 having a second thickness T2. The depletion-forming layer 250 may be formed to be spaced apart from the source electrode 241 and the drain electrode 242. The depletion-forming layer 250 may be formed closer to the source electrode 241 than the drain electrode 242 to which a high voltage is applied.

The depletion-forming layer 150 may serve to form a depletion region in the two-dimensional electron gas (2DEG). The energy bandgap of the portion of the channel supply layer 130 located below the depletion forming layer 150 can be increased and as a result the channel layer 120 corresponding to the depletion forming layer 150 ) Portion of the two-dimensional electron gas (2DEG) can be formed. Therefore, a portion of the two-dimensional electron gas (2DEG) corresponding to the first portion 151 of the depletion forming layer 150 can be broken, and a portion corresponding to the second portion 142 can be reduced . The electron concentration of the two-dimensional electron gas (2DEG) in the regions corresponding to the depletion forming layer 150 and the source electrode 161 and the depletion forming layer 150 and the drain electrode 162 is lower than the electron concentration Of the two-dimensional electron gas (2DEG).

In FIG. 5, a region of a two-dimensional electron gas (2DEG) having a relatively high electron density and a region of a two-dimensional electron gas (2DEG) having a relatively low electron density are shown divided by the thickness of a dot. The larger the thickness of the dot, the higher the electron density. The region where the two-dimensional electron gas (2DEG) is broken can be referred to as a 'disconnecting region D'. By the disconnecting region D, the high electron mobility transistor 100 has a normally- Lt; / RTI >

The depletion-forming layer 150 may comprise a p-type semiconductor material. That is, the depletion-forming layer 150 may be a p-type semiconductor layer or a semiconductor layer doped with a p-type impurity. Further, the depletion-forming layer 150 may be formed of a III-V group nitride semiconductor. For example, the depletion-forming layer 150 may be made of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN, and may be doped with a p-type impurity such as Mg. As a specific example, the depletion-forming layer 150 may be a p-GaN layer or a p-AlGaN layer. As the energy band gap of the portion of the channel supply layer 130 below the depletion layer 150 is increased by the depletion generation layer 150, the disconnection region D of the two-dimensional electron gas (2DEG) or the region having a relatively low electron density .

A gate electrode 260 may be formed on the depletion-forming layer 250. The gate electrode 260 may be formed on the first portion 251 of the depletion-forming layer 250. A plurality of openings 262 are formed in the gate electrode 260. The plurality of openings 262 may be formed so as to be evenly distributed in the gate electrode 260. The opening 262 reduces the contact area between the depletion-forming layer 250 and the gate electrode 260. Accordingly, the amount of leakage of the voltage applied to the gate electrode 260 through the depletion layer 250 and the channel supply layer 230 can be reduced. The aperture ratio at the gate electrode 260 may be approximately 20 to 80%. Since the shape of the opening 262 is well known in the above-described embodiment, detailed description is omitted.

The gate electrode 260 may be formed of a common metal. The gate electrode 260 may be a Schottky contact material with the depletion-forming layer 250. The gate electrode 260 may be formed to a thickness of approximately several tens to several hundreds nm.

When a voltage equal to or higher than a threshold voltage is applied to the gate electrode 260, a two-dimensional electron gas (2DEG) is generated in the cutoff region D, and the high electron mobility transistor 200 is turned on. Current flows through the two-dimensional electron gas (2DEG) formed in the channel layer 220 as the channel formed below the gate electrode 260 is turned on. The threshold voltage may vary depending on the thickness of the first portion 251 of the depletion-forming layer 250 and the doping concentration of the first portion 251.

When a voltage higher than the hole injection voltage of the second portion 252 of the depletion-forming layer 250 is applied to the gate electrode 260 from the second portion 252 to the channel supply layer 230, And the electron concentration of the two-dimensional electron gas (2DEG) in the region below the depletion-forming layer 250 increases corresponding to the holes injected into the two-dimensional electron gas (2DEG). Therefore, the on-resistance decreases.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined by the appended claims.

100: Electron mobility transistor with no-
110: substrate 120: channel layer
130: channel supply layer 141: source electrode
142: drain electrode 150: depletion layer
160: gate electrode 162: opening

Claims (13)

A channel layer made of a first nitride semiconductor;
A channel supply layer made of a second nitride semiconductor on the channel layer and inducing two-dimensional electron gas in the channel layer;
Source and drain electrodes on both sides of the channel supply layer;
A depletion forming layer forming a depletion region in at least a part of the two-dimensional electron gas on the channel supply layer; And
And a gate electrode in contact with the depletion-forming layer and having a plurality of openings formed on the depletion-forming layer. The method according to claim 1,
And an aperture ratio of the plurality of openings is 20% to 80%. The method according to claim 1,
And the plurality of openings are uniformly dispersed in the gate electrode. The method according to claim 1,
Wherein the gate electrode is formed at substantially the same position as the depletion-imparting layer in a plan view. The method according to claim 1,
Wherein the plurality of openings are a plurality of slits formed in parallel to the direction of the drain electrode from the source electrode. The method according to claim 1,
Wherein the depletion layer comprises a first portion having a first thickness and a second portion having a second thickness on either side of the first portion,
And the gate electrode is formed on the first portion. The method according to claim 6,
Wherein the first thickness is thicker than the second thickness. The method according to claim 6,
And the second portion is spaced apart from the source electrode and the drain electrode. The method according to claim 6,
Wherein the depletion region is formed below the first portion and the lower portion of the second portion is a region where the electron concentration of the two-dimensional electron gas is relatively lower than a region without the depletion-forming layer. The method according to claim 1,
Wherein the first nitride semiconductor is a GaN-based material. The method according to claim 1,
Wherein the second nitride semiconductor is at least one selected from among nitrides including at least one of Al, Ga, In, and B. 2. The high electron mobility transistor of claim 1, The method according to claim 1,
Wherein the depletion-forming layer is made of a p-type nitride semiconductor. The method according to claim 1,
Wherein the depletion-forming layer comprises a Group III-V nitride semiconductor material.

Images