CN102856374B - GaN enhanced MIS-HFET device and preparation method of same - Google Patents
GaN enhanced MIS-HFET device and preparation method of same Download PDFInfo
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- CN102856374B CN102856374B CN201210381515.1A CN201210381515A CN102856374B CN 102856374 B CN102856374 B CN 102856374B CN 201210381515 A CN201210381515 A CN 201210381515A CN 102856374 B CN102856374 B CN 102856374B
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Abstract
The invention relates to the technical field of semiconductor devices, and in particular relates to a GaN enhanced MIS-HFET (Metal Insulator Semiconductor Heterojunction Field Effect Transistor) device and a preparation method of the same. The device provided by the invention comprises a grid electrode, a source electrode, a drain electrode, an insulating dielectric layer and a substrate, wherein the substrate is orderly provided with a stress buffer layer, a first GaN layer and a selective growing layer from top to bottom, and the selective growing layer comprises a second GaN layer and a heterogeneous layer thereon; the middle part of the selective growing layer comprises a through groove channel, the bottom surface of the groove channel is covered by a p type Gan layer, and the thickness of the p type GaN layer is not more than that of the second GaN layer; two sides of the upper surface of the heterogeneous layer are coved by ohmic contact metals to respectively form the source electrode and the drain electrode, the insulating dielectric layer covers the upper surface of the device except for the positions of the source electrode and the drain electrode, and the grid electrode covers the groove channel on the insulating dielectric layer. The GaN enhanced MIS-HFET device is simple in manufacturing technology and high in device stability, and simultaneously, by the preparation method, the threshold voltage of the device is improved.
Description
Technical field
The present invention relates to semiconductor device and preparation method thereof, particularly relate to a kind of for GaN enhancement mode MIS-HFET device in high temperature high power switching device and preparation method thereof.
Background technology
GaN base wide bandgap semiconductor is because possess the characteristics such as high breakdown electric field, high electronics saturation drift velocity and high heat conductance, adopt heterostructure can form the two-dimensional electron gas of high concentration, these advantages make GaN have very wide application prospect in high-power electronic device field simultaneously.
In actual applications, enhanced power device can meet " fail safe " requirement.But due to the polarity effect of GaN, the interface of AlGaN/GaN heterostructure forms the two-dimensional electron gas of high concentration, the device directly adopting AlGaN/GaN heterostructure to prepare is made to be depletion device, namely when device under the condition of grid in zero-bias is in conducting state, " fail safe " requirement is not met.In addition, in order to avoid the factors such as noise cause the misoperation of device, also require that enhancement device has higher threshold voltage.Therefore, how adopting AlGaN/GaN heterostructure to prepare the enhanced power device with higher forward threshold voltage, is the focus of research at present.
The technology path realizing enhancement mode GaN FET device traditionally mainly contains Schottky gate field-effect transistor and metal dielectric layer semiconductor field effect transistor (MISFET).
For Schottky gate field-effect transistor, the main method realizing enhancement mode adopts recessed grid structure, namely by utilizing inductively coupled plasma (ICP) etched recesses to area of grid, reduce two-dimensional electron gas (2DEG) concentration of raceway groove, device is made to reach normal effect of closing, simultaneously at grid place evaporation Ni/Au electrode, form Schottky contacts with AlGaN, realize the control of device being opened, turning off.In addition, ion implantation is also a kind of conventional technology, and by carrying out plasma treatment to the AlGaN of area of grid, the two-dimensional electron gas of anion to raceway groove injected as fluorine ion etc. exhausts, and makes device reach normal effect of closing.Adopt power device prepared by said method, its advantage has less conducting resistance (R
oN), and normal pass can be realized; Its shortcoming is that grid leakage current is excessive, and threshold voltage is only between 0 to 1V, simultaneously because area of grid causes lattice damage after plasma treatment, has an impact to the stability of device and reliability.
For GaN base metal dielectric layer semiconductor field effect transistor (MISFET), similar to INVENTIONConventional metal-oxide semiconductor field effect transistor (MOSFET), in order to realize often closing characteristic, p-type doping is carried out to GaN and obtains p-type substrate, it is heavily doped that source and drain two end regions then carries out N-shaped, and electrode evaporation forms ohmic contact, electrode evaporation after area of grid depositing insulating layer, forms MIS structure.When grid adds larger forward bias, GaN forms inversion layer as conducting channel near interfacial dielectric layer place, device is in conducting state.Although this GaN base MISFET can realize often closing characteristic, due to shortcomings such as conducting resistance are larger, in fact and be not suitable for and directly prepare high power device.
At present, in order to overcome the above-mentioned shortcoming of traditional enhancement mode GaN FET device, the main technological route realizing now GaN enhanced power device is the mixed structure adopting metal dielectric layer semiconductor (MIS) and HFET (HFET), i.e. MIS-HFET.Grid place adopts MIS structure, can reduce the grid leakage current of device, improves the threshold voltage of device; The high concentration two-dimensional electron gas utilizing AlGaN/GaN heterostructure to be formed, as conductive channel, can reduce the conducting resistance of device, improves the power output of device.
It seems from current achievement in research, adopting MIS-HFET structure to obtain GaN enhanced power device is a kind of desirable technology path, but by ICP in area of grid etched recesses, or the method for ion is injected at area of grid, although device can be made to realize often closing characteristic, also bring following problem: be first the requirement that the threshold voltage of device prepared by said method can not reach practical application; The lattice damage that next plasma treatment raceway groove to area of grid causes, impacts the reliability and stability of device.
Summary of the invention
The technical problem that the present invention solves overcomes the deficiencies in the prior art, provides a kind of stability and the high and GaN enhancement mode MIS-HFET device with high threshold voltage and preparation method thereof of reliability.
For solving the problems of the technologies described above, the technical solution used in the present invention is:
A kind of GaN enhancement mode MIS-HFET device, comprise grid, source electrode, drain electrode, insulating medium layer and substrate (1), described substrate is provided with from lower to upper successively stress-buffer layer, the first GaN layer (3) and growth selection layer, described growth selection layer comprises the second GaN layer and the heterosphere on it; Have through recess channel in the middle part of described growth selection layer, be coated with p-type GaN layer in recess channel bottom surface, the thickness of described p-type GaN layer is less than or equal to the thickness of the second GaN layer; Two side positions of heterosphere upper surface are coated with metal ohmic contact and form source electrode and drain electrode respectively, and insulating medium layer is covered in the region of upper surface except source electrode and drain locations of device, and grid is covered in the recess channel place on insulating medium layer.
The preparation method of above-mentioned GaN enhancement mode MIS-HFET device, comprises the following steps:
Step one, on substrate, growth stress resilient coating, the first GaN layer and p-type GaN layer successively;
Step 2, in p-type GaN layer, homoepitaxial one deck dielectric layer, then etches the dielectric layer of access area, retains the dielectric layer of area of grid as mask layer;
The p-type GaN layer of step 3, etching access area, retains the p-type GaN layer of area of grid;
Step 4, grow the second GaN layer and heterosphere in access area, the thickness of the second GaN layer is more than or equal to the thickness of p-type GaN layer, thus form the recess channel of area of grid;
Step 5, etching mask layer, manifest the interface of p-type GaN layer;
Step 6, form source electrode and drain electrode respectively at the source and drain areas evaporation ohmic metal of heterosphere upper surface both sides;
Step 7, except source electrode and drain locations, all deposit dielectric, as the insulating medium layer of grid at the upper surface of device;
Step 8, at insulating medium layer upper groove channel location place evaporation ohmic metal as grid.
The implication of above-mentioned access area is that the grid in the middle part of device and the region between the source electrode in device both sides and drain electrode (do not comprise the recessed channel region below grid, but comprise the region of source electrode and drain electrode below), the namely region of device upper groove raceway groove both sides.
Wherein, in described step one, in the growing method of stress-buffer layer, high resistant GaN layer and p-type GaN layer and step 4, the growing method of the second GaN layer and heterosphere is Metalorganic Chemical Vapor Deposition (MOCVD) or molecular beam epitaxy (MBE).
In described step 2 dielectric layer and step 7, the growing method of insulating medium layer is physical vaporous deposition (PVD), plasma enhanced chemical vapor deposition method (PECVD), atomic layer deposition method (ALD) or magnetic control sputtering plating method.
Further, described heterosphere is one in AlGaN, AlInN, AlInGaN, AlN material or any several combination, and described heterosphere is non-doped layer or N-type doped layer; Heterosphere thickness range is 1 ~ 50nm.If the combination of multiple material, then multiple material adopts the mode be layering to combine, instead of the form combination of mixture.Implication such as represented by AlGaN/AlN combination is as heterosphere together with AlGaN material layer superposes with AlN material layer.
Further, described first GaN layer is high resistant GaN layer.
Further, the material of described insulating medium layer is SiO
2, SiNx, Al
2o
3, AlN, HfO
2, MgO, Sc
2o
3, Ga
2o
3, any one or combinations several arbitrarily in AlHfOx, HfSiON; Insulating medium layer thickness range is 1 ~ 50nm.
Further, the thickness range of described p-type GaN layer is 1 ~ 500nm, and the thickness range of described second GaN layer is 1 ~ 500nm.
Further, the ohmic metal of described formation source electrode and drain electrode is Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; The ohmic metal of described formation grid is Ni/Au alloy, Pt/Al alloy or Pd/Au alloy.Wherein the implication of source electrode and drain electrode alloy material is described for Ti/Al/Ni/Au alloy.The implication of " Ti/Al/Ni/Au alloy " is evaporation last layer Ti, one deck Al, layer of Ni and layer of Au successively from the bottom up, by the composite bed (i.e. alloy) of these four layers of metals as source electrode and drain electrode.This form of presentation had both illustrated that this alloy contained this four kinds of metals, also contains a kind of ordinal relation simultaneously.Similar, the implication of " Ti/Al/Ti/Au alloy " is evaporation last layer Ti, one deck Al, one deck Ti and layer of Au successively from the bottom up, by the composite bed (i.e. alloy) of these four layers of metals as source electrode and drain electrode.The implication of Ti/Al/Mo/Au alloy is the same.The implication of the ohmic metal material of grid is also the same.
Further, described substrate is Si substrate, SiC substrate or Sapphire Substrate.
With utilize compared with prior art, the invention has the beneficial effects as follows: GaN enhancement mode MIS-HFET device of the present invention, by in area of grid introducing p-type GaN layer, in conjunction with dielectric layer and the gate metal electrode of area of grid deposition, form p-type substrate MIS structure, under grid is in zero-bias or back bias voltage state, p-type GaN layer is majority carrier with hole and cannot forms electronic conduction raceway groove, and device is in off state; Only have when grid applies larger forward voltage, p-type GaN layer is forming electron inversion layer near the interface of dielectric layer, and this inversion layer is as electronic conduction raceway groove, and now device is in opening.So the introducing of p-type GaN layer, the normal pass characteristic of device can be realized, and effectively improve threshold voltage.Simultaneously, device manufacture method of the present invention, in order to coordinate the structure of introducing p-type GaN layer, special design adopts the technique of selective area growth to retain the p-type GaN layer of area of grid, namely by the mode of selective etch, p-type GaN layer except area of grid is all etched away, and then heterostructure can be grown in access area, to replace the method in area of grid etched recesses or ion implantation in prior art, the lattice damage avoiding plasma to cause impacts raceway groove, improves device reliability and stability.Simultaneously at access area growth heterostructure, the two-dimensional electron gas of high concentration can also be obtained, reduce access resistance, reduce the conducting resistance of device on the whole, improve device output power.In addition, access area is by secondary epitaxy mode regrowth one deck GaN layer (i.e. the second GaN layer), the lattice surface damage brought when can repair etching p-type GaN layer, achieve being separated of two-dimensional electron gas interface, access area and etching interface, reduce the impact that etching technics comes access zone, improve device reliability and stability further.
Accompanying drawing explanation
Fig. 1-Fig. 9 is the process schematic representation of the preparation method of the GaN enhancement mode MIS-HFET device of the embodiment of the present invention 1.
Figure 10 is the GaN enhancement mode MIS-HFET device architecture schematic diagram of the embodiment of the present invention 2;
Embodiment
Embodiment 1
Be illustrated in figure 9 the structural representation of the GaN enhancement mode MIS-HFET device of the present embodiment, comprise grid, source electrode, drain electrode, insulating medium layer and substrate 1.Substrate selects Si substrate or SiC substrate or Sapphire Substrate usually.Substrate is provided with stress-buffer layer 2, first GaN layer 3 and growth selection layer from lower to upper successively, and growth selection layer comprises the second GaN layer 7 and the heterosphere 8 on it.Wherein the first GaN layer is high resistant GaN layer.Have through recess channel in the middle part of growth selection layer, be coated with p-type GaN layer 6 in recess channel bottom surface, the thickness of p-type GaN layer 6 is less than or equal to the thickness of the second GaN layer 7.Two side positions of heterosphere 8 upper surface are coated with metal ohmic contact and form source electrode and drain electrode respectively.Insulating medium layer 10 is covered in the region of upper surface except source electrode and drain locations of device, and grid is covered in the recess channel place on insulating medium layer.
The thickness of heterosphere 8 needs to control to the two-dimensional electron gas that can either form high concentration at the interface of the second GaN layer 7, can reduce again source-drain electrode ohmic contact resistance and device on-resistance is optimum simultaneously.Through experimental verification, this heterosphere 8 THICKNESS CONTROL is optimum within the scope of 1 ~ 50nm.
The thickness of the insulating medium layer 11 of grid, had both been required to meet the conductive characteristic that grid 12 can control raceway groove very well, and had made device have larger mutual conductance, also required to keep good insulating properties.Through experimental verification, this thickness is that 1 ~ 50nm is for best.
Above-mentioned GaN enhancement mode MIS-HFET device making technics is as shown in figs 1-9:
Step one, utilize metal organic chemical vapor deposition (MOCVD), growth stress resilient coating 2, first GaN layer 3 and p-type GaN layer 6 successively on substrate; The thickness range of p-type GaN layer 6 is 1 ~ 500nm, as shown in Figure 1.
Step 2, in p-type GaN layer 6, by physical vapor deposition (PVD) or plasma activated chemical vapour deposition (PECVD) or homoepitaxial one deck dielectric layer 4 such as ald (ALD) or magnetic control sputtering plating, as shown in Figure 2, then the dielectric layer of access area is etched, and the dielectric layer retaining area of grid is as mask layer 5, as shown in Figure 3.
The p-type GaN layer of step 3, etching access area, retains the p-type GaN layer 6 of area of grid, as shown in Figure 4.
Step 4, utilize metal organic chemical vapor deposition (MOCVD), grow the AlInGaN heterosphere 8 of the second GaN layer 7 and undoped in access area.The thickness of the second GaN layer 7 is more than or equal to the thickness of p-type GaN layer 6, thus form the recess channel of area of grid; The thickness range of the second GaN layer 7 is 1 ~ 500nm, as shown in Figure 5.
Step 5, etching mask layer 5, manifest the interface 9 of p-type GaN layer 6, as shown in Figure 6.
Step 6, the source and drain areas evaporation Ti/Al/Ni/Au alloy of heterosphere 8 upper surface both sides formed respectively source electrode and drain electrode 10; Source electrode is interchangeable with drain electrode, if namely side is source electrode, that opposite side drains exactly, as shown in Figure 7.
Step 7, except source electrode and drain locations, all deposit one deck Al at the upper surface of device by physical vapor deposition (PVD) or plasma activated chemical vapour deposition (PECVD) or ald (ALD) or magnetic control sputtering plating etc.
2o
3, as the insulating medium layer 11 of grid, as shown in Figure 8.
Step 8, at insulating medium layer 11 upper groove channel location place evaporation Ni/Au alloy as grid 12, as shown in Figure 9.
Embodiment 2
As shown in Figure 10, for the another kind of structural representation of GaN enhancement mode MIS-HFET device of the present invention, it is substantially identical with the device architecture of embodiment 1, difference is only, when growth selection heterosphere by the doping of modulation N-type, namely form the heterosphere 13 of N-type doping, to reduce the ohmic contact resistance of source, drain region further, improve the current density of device.
Claims (3)
1. the preparation method of a GaN enhancement mode MIS-HFET device, comprise grid, source electrode, drain electrode, insulating medium layer and substrate (1), it is characterized in that, described substrate is provided with from lower to upper successively stress-buffer layer (2), the first GaN layer (3) and growth selection layer, described growth selection layer comprises the second GaN layer (7) and the heterosphere on it (8); Have through recess channel in the middle part of described growth selection layer, be coated with p-type GaN layer (6) in recess channel bottom surface, the thickness of described p-type GaN layer (6) is less than or equal to the thickness of the second GaN layer (7); Two side positions of heterosphere (8) upper surface are coated with metal ohmic contact and form source electrode and drain electrode respectively, insulating medium layer (10) is covered in the region of upper surface except source electrode and drain locations of device, grid is covered in the recess channel place on insulating medium layer, it is characterized in that, comprise the following steps:
Step one, on substrate, growth stress resilient coating (2), the first GaN layer (3) and p-type GaN layer (6) successively;
Step 2, in p-type GaN layer (6), homoepitaxial one deck dielectric layer (4), the dielectric layer of etching access area, retains the dielectric layer of area of grid as mask layer (5);
The p-type GaN layer of step 3, etching access area, retains the p-type GaN layer (6) of area of grid;
Step 4, grow the second GaN layer (7) and heterosphere (8) in access area, the thickness of the second GaN layer (7) is more than or equal to the thickness of p-type GaN layer (6), thus form the recess channel of area of grid;
Step 5, etching mask layer (5), manifest the interface (9) of p-type GaN layer (6);
Step 6, form source electrode and drain electrode (10) respectively at the source and drain areas evaporation ohmic metal of heterosphere (8) upper surface both sides;
Step 7, except source electrode and drain locations, all deposit dielectric at the upper surface of device, as the insulating medium layer (11) of grid;
Step 8, at insulating medium layer (11) upper groove channel location place evaporation ohmic metal as grid (12).
2. the preparation method of GaN enhancement mode MIS-HFET device according to claim 1, it is characterized in that, in described step one, in the growing method of stress-buffer layer (2), high resistant GaN layer (3) and p-type GaN layer (6) and step 4, the growing method of the second GaN layer (7) and heterosphere (8) is Metalorganic Chemical Vapor Deposition or molecular beam epitaxy.
3. the preparation method of GaN enhancement mode MIS-HFET device according to claim 1, it is characterized in that, in described step 2 dielectric layer and step 7, the growing method of insulating medium layer is physical vaporous deposition, plasma enhanced chemical vapor deposition method, atomic layer deposition method or magnetic control sputtering plating method.
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| CN104167441B (en) * | 2014-07-30 | 2017-08-25 | 西安电子科技大学 | A kind of enhanced MIS structure AlGaN/GaN HFETs |
| CN104167440B (en) * | 2014-07-30 | 2017-08-25 | 西安电子科技大学 | A kind of enhanced AlGaN/GaN HFETs |
| JP6304155B2 (en) * | 2015-07-14 | 2018-04-04 | 株式会社デンソー | Nitride semiconductor device |
| CN106328700B (en) * | 2016-08-22 | 2019-03-12 | 东南大学 | A kind of reinforced insulation buried layer AlGaN-GaN high electron mobility transistor |
| CN107785435A (en) * | 2017-10-24 | 2018-03-09 | 江苏华功半导体有限公司 | A kind of low on-resistance MIS notched gates GaN base transistors and preparation method |
| CN109755301A (en) * | 2019-01-15 | 2019-05-14 | 中山大学 | A kind of GaN MISFET device at high quality grid interface and preparation method thereof |
| CN113939917A (en) * | 2019-06-17 | 2022-01-14 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method thereof |
| US20220376038A1 (en) * | 2020-09-09 | 2022-11-24 | Innoscience (Suzhou) Technology Co., Ltd. | Semiconductor device structures and methods of manufacturing the same |
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